JPS57115019A - Clock pulse converting system - Google Patents
Clock pulse converting systemInfo
- Publication number
- JPS57115019A JPS57115019A JP56001120A JP112081A JPS57115019A JP S57115019 A JPS57115019 A JP S57115019A JP 56001120 A JP56001120 A JP 56001120A JP 112081 A JP112081 A JP 112081A JP S57115019 A JPS57115019 A JP S57115019A
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- terminal
- rate
- pulses
- selector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Mathematical Optimization (AREA)
- Mathematical Analysis (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To achieve rate conversion between pulses with different rate, by mixing an input pulse itself with frequency-divided or multiplied input pulse for a specified amount. CONSTITUTION:A frequency-division/multiplication circuit 2 outputs a pulse of no-conversion from a terminal TH, pulse of 1/2 frequency-division from a terminal DV, and doubled pulse from a terminal MP. To convert a pulse CP1 in clock rate f1 (2.048MHz) into a pulse in clock rate f2 (l.554MHz), 63 pulses in l.024MHz outputted from the terminal DV are transmitted through a selector 3, the selector 3 is switched by a D type FF5, and 130 pulses in 2.048MHz outputted from the terminal TH are transmitted through the selector 3. To convert the pulse in rate f2 into a pulse in rate f1, the output pulses at the terminals MP and TH are mixed similarly.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56001120A JPS57115019A (en) | 1981-01-09 | 1981-01-09 | Clock pulse converting system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56001120A JPS57115019A (en) | 1981-01-09 | 1981-01-09 | Clock pulse converting system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57115019A true JPS57115019A (en) | 1982-07-17 |
Family
ID=11492592
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56001120A Pending JPS57115019A (en) | 1981-01-09 | 1981-01-09 | Clock pulse converting system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57115019A (en) |
-
1981
- 1981-01-09 JP JP56001120A patent/JPS57115019A/en active Pending
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