JPS56119532A - Digital frequency dividing circuit - Google Patents
Digital frequency dividing circuitInfo
- Publication number
- JPS56119532A JPS56119532A JP2247480A JP2247480A JPS56119532A JP S56119532 A JPS56119532 A JP S56119532A JP 2247480 A JP2247480 A JP 2247480A JP 2247480 A JP2247480 A JP 2247480A JP S56119532 A JPS56119532 A JP S56119532A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- pulses
- output
- dividing circuit
- frequency dividing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/665—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by presetting
Landscapes
- Manipulation Of Pulses (AREA)
- Pulse Circuits (AREA)
Abstract
PURPOSE:To divide the frequency in the division ratio of an arbitary rational number, by giving the output of the one-bit delay delayed by one clock and the output of the programmable divider to the preset terminal of the programmable divider. CONSTITUTION:The pulse train input from input terminal 1 is divided in programmable divider PD3 by 1/3, and the output is fed back immediately to terminal PE of PD3 through OR gate 6. Meanwhile, bit rate multiplier BM4 outputs five pulses out of 10 input pulses, and these pulses are delayed by one bit and are fed back to terminal PE of PD3. Consequently, the period when 10 pulses are inputted to terminal IN of BM4 becomes one period of this frequency dividing circuit. During this one period, the number of pulses inputted to input terminal is 4X5+3X (10-5)=35, and the number of pulses outputted from output terminal 2 is 10. Consequently, the frequency division ratio is 35/10=3.5. Thus, the frequency dividing circuit has an arbitary frequency division ratio.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2247480A JPS56119532A (en) | 1980-02-25 | 1980-02-25 | Digital frequency dividing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2247480A JPS56119532A (en) | 1980-02-25 | 1980-02-25 | Digital frequency dividing circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56119532A true JPS56119532A (en) | 1981-09-19 |
JPS6211814B2 JPS6211814B2 (en) | 1987-03-14 |
Family
ID=12083707
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2247480A Granted JPS56119532A (en) | 1980-02-25 | 1980-02-25 | Digital frequency dividing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56119532A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6162599U (en) * | 1984-09-29 | 1986-04-26 |
-
1980
- 1980-02-25 JP JP2247480A patent/JPS56119532A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6162599U (en) * | 1984-09-29 | 1986-04-26 |
Also Published As
Publication number | Publication date |
---|---|
JPS6211814B2 (en) | 1987-03-14 |
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