SU1341634A1 - Random-duration pulse generator - Google Patents

Abstract

The invention relates to computing and can be used in static modeling. The purpose of the invention is to expand the class of tasks to be accomplished by obtaining the G-distribution. The generator contains elements 1, 2 delays, triggers 3, 4, generators 5, 6, dividers 7, -7f (., Frequencies, counters 8, -8, elements And, register 10. 2 Il. With 4 s with 4

Description

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The invention relates to computing and impulse technology, in particular, to devices for the formation of pulses, values that are random and distributed over the Z-distribution of the order of N.

The purpose of the invention is to expand the class of problems solved by the device by forming a stream of pulses with a distribution of their duration along the T-distribution of order N.

FIG. 1 shows a structural diagram of a pulse generator with a random duration; in fig. 2 - time diagrams of his work.

The generator contains the first 1 and second 2 delay elements, the first 3 and second 4 triggers, high-frequency 5 and low-frequency 6 pulse generators, divider group 7 (-7 fj, frequencies, pulse counters group, AND 9, -9k group elements, shift register 10 .

The generator works as follows.

When a trigger signal arrives (Fig. 2c (), the trigger 3 is set to one. At this point, the pulses from the output of the high-frequency generator 5 (Fig. 2S)) stop flowing to the input of the counter 8, pulses. At the same time, the pulses from the high-frequency generator 5 arrive through dividers 7, -7., frequencies to the inputs of pulse counters (Fig. 2, e). The division factors of dividers 7, -7 "-1 frequencies are chosen from the relation, i + 1s where i is the number of the divider. The trigger signal delayed by the first delay element 1 for the time required to complete transients in counters 8, -8k, goes to the combined inputs of the elements of group I. At the same time, the contents of the bits of counters 8, -8m from 1st to Kth are rewritten into the corresponding bits of shift register 10 from 2nd to q- y.

The contents of the bits of counters 8, -8f are fed to the inverse inputs of the group of elements AND to ensure that the condition for summing the probabilities of writing zeroes from both counters to the bits of the shift register is satisfied. The triggering signal is delayed by the second delay element 2 for the time required to complete the transients in shift register 10.

6342

sets trigger 3 to the zero state, while counters 8, -8 "continue to count pulses,

J. generated by a high-frequency generator, starting from the Kg code value that was recorded at the moment the trigger signal arrived. At the same time, the signal from the output of the second delay element 2 sets the trigger 4 to the zero state (Fig. 2b), while the pulses from the output of the low-frequency generator 6 (Fig. 2d) begin to go to the clock input

the shift register 10, shifted the code written in it towards the higher bits. If, when the next shift pulse arrives, it turns out that 1 is recorded in the high-order bit, then the signal from the output of the shift register 10 sets the second trigger 4 to one, thereby turning off the low-frequency

25th generator 6 from register 10 shift. At the same time, the same signal outside the bit of the shift register 10, except for the first one, is set to the zero state, and in the first bit of the entry 30, 1 is prepared to record the next value of the K code. Time, during which the second trigger 4 is in the zero state, depends on the value of the code og K and can be calculated by the formula (M + 1), where M is the number of most significant bits of the shift register 10, in which Podrad are written zeros.

With equal values of K (.

The 40 values of the pulse durations are governed by the Γ distribution of order w.

Thus, at zero output. the second trigger 4, which is the first generator 11 of the generator, impulses are formed with a random duration. At the same time at the output of the low-frequency generator 6, which is the second output 12 of the device,

50 a burst of pulses is formed, the number of which also randomly submits. G-distribution of order N. Ensuring uniform code values - K is achieved by choosing the ratio

55 trigger frequency, and

the frequency of the high-frequency generator .. fg from the condition fg / f, 2. The frequency of the low-frequency generator f is chosen from the required range

values of random pulse duration about c. The term low-frequency for this generator is conditional, as borrowed from the prototype. According to the functions performed, this is a clock pulse generator, and the frequency f can be either more or less than f. To prevent the generator from restarting during the formation of the next pulse with a random duration, it is necessary to choose the frequency of the trigger signals from the condition f ,.

Claims (1)

Invention Formula A pulse generator with a random duration containing two triggers, a low-frequency and high-frequency pulse generators, a shift register, two pulse counters, a frequency divider, two delay elements whose inputs are connected are the input of the generator and connected to the single input of the first trigger, the output The second delay element is connected to the zero input of the second trigger and the zero input of the first trigger, the zero output of which is connected to the Start input of the high-frequency pulse generator, the output of which n from the first counting input pulses and the first counter the frequency divider whose output is connected to the counting input of the second pulse counter, the zero output of the second trigger is the first generator output and is connected to the input. Starting the low-frequency pulse generator whose output is the second generator output and connected to the shift register shift input, the output of which is the last bit connected to the input Setting the shift register and to the single input of the second trigger, characterized in that, in order to expand the class of solved problems by obtaining the G-distribution of the order of N, it is contains a group of elements And, a group of pulse counters, a group of frequency dividers, the inputs of which are connected to the output of the high frequency generator, and the outputs of frequency dividers of the group are connected to the counting inputs of the corresponding pulse counters of the group, the outputs of which are connected to the inverse inputs of the elements of the group And, respectively, the first direct the inputs of which are connected to the outputs of the corresponding bits of the first pulse counter, and the second direct inputs of the elements AND of the group are connected to the output of the first delay element, the outputs of the el ments and the group connected to the inputs of the corresponding bits of the shift register. I I I I I I I I I d lllllll illllllllllllllll f I I I I I I M I I I I I I I II I I FIG. 2 mill I I I