JPS55124327A - Digital-analog converting circuit - Google Patents
Digital-analog converting circuitInfo
- Publication number
- JPS55124327A JPS55124327A JP3111079A JP3111079A JPS55124327A JP S55124327 A JPS55124327 A JP S55124327A JP 3111079 A JP3111079 A JP 3111079A JP 3111079 A JP3111079 A JP 3111079A JP S55124327 A JPS55124327 A JP S55124327A
- Authority
- JP
- Japan
- Prior art keywords
- counter
- signal
- output
- digital
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/82—Digital/analogue converters with intermediate conversion to time interval
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To secure the sufficient accuracy as well as facilitate an easy LSI formation of the circuit by decreasing the number of the analog circuits which give the direct effect to the output accuracy and then constituting most of the circuits with the digital circuits, thus realizing the miniaturization of the converting circuit. CONSTITUTION:The pulse row signal (1) of the fixed frequency is generated from oscillator 1, and signal (1) is divided into the fixed ratio through divider counter 2. This divided signal (2) is applied to RSFF4 as well as to preset counter 3 to which digital input IN to be converted is applied. At the same time, the output of gate 5 which gives gating to the output of signal (1) and FF4 is applied to counter 3. Then input IN of counter 3 is set in synchronization with the output of counter 2, and the time during which the set digital quantity is turned to zero via signal (1) is counted by counter 3, and then the ratio the counted time and the cycle of counter 2 is applied to buffer gate 6 via FF4. Then the signal converted into the analog quantity is delivered via filter 7.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3111079A JPS55124327A (en) | 1979-03-19 | 1979-03-19 | Digital-analog converting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3111079A JPS55124327A (en) | 1979-03-19 | 1979-03-19 | Digital-analog converting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55124327A true JPS55124327A (en) | 1980-09-25 |
Family
ID=12322255
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3111079A Pending JPS55124327A (en) | 1979-03-19 | 1979-03-19 | Digital-analog converting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55124327A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57188131A (en) * | 1981-05-15 | 1982-11-19 | Matsushita Electric Ind Co Ltd | Pulse width modulation circuit |
JPS5830227A (en) * | 1981-08-18 | 1983-02-22 | Matsushita Electric Ind Co Ltd | Pulse width modulating circuit |
JPS58168327A (en) * | 1982-03-29 | 1983-10-04 | Toshiba Corp | Pulse width modulating circuit |
JPS6158325A (en) * | 1984-08-29 | 1986-03-25 | Shimadzu Corp | D/a converter |
-
1979
- 1979-03-19 JP JP3111079A patent/JPS55124327A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57188131A (en) * | 1981-05-15 | 1982-11-19 | Matsushita Electric Ind Co Ltd | Pulse width modulation circuit |
JPS6258572B2 (en) * | 1981-05-15 | 1987-12-07 | Matsushita Electric Ind Co Ltd | |
JPS5830227A (en) * | 1981-08-18 | 1983-02-22 | Matsushita Electric Ind Co Ltd | Pulse width modulating circuit |
JPS58168327A (en) * | 1982-03-29 | 1983-10-04 | Toshiba Corp | Pulse width modulating circuit |
JPS6158325A (en) * | 1984-08-29 | 1986-03-25 | Shimadzu Corp | D/a converter |
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