JPS5830227A - Pulse width modulating circuit - Google Patents

Abstract

PURPOSE:To improve linearity of a pulse width modulating output, by counting an output of a means for gating a clock pulse in accordance with a control signal, and controlling an output of a counting value detector by a preset pulse. CONSTITUTION:A data value of a digital modulating signal di is detected by a detector 4, whether it is a prescribed data value or not is detected, and a signal (f) of H or L is outputted to an output generator 6. The signal di and a preset pulse (e) from a pulse generating circuit 7 are inputted to a presetting circuit 2, an FF of a binary counter 1 is set or reset, and an output from a clock gate 5 is counted. Subsequently, when the counting value becomes a prescribed value, the clock gate 5 is opened by an output (b) of a counting value detector 3. After that, when the output (b) is applied, a pulse width modulating output (h) is obtained from the output generator 6. In this case, in order to eliminate influence of a delay time of the output (b), the output (h) is controlled at the time point when the preset pulse (e) has been generated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse width modulation circuit that converts a double-encoded digital modulation signal into a pulse width modulation output, and particularly to improving the linearity of the pulse width modulation output. The purpose is to

Figure 1 is a basic configuration diagram of a conventional pulse width modulation circuit;
The figure is an operation waveform diagram of FIG. 1.

In FIG. 1, 1 is a binary kakunta, 2 is a preset circuit, and 3 is a count value detector, which detects the maximum count value No.=2n-1 of the binary kakunta 1 here.

Here, the data value d=Q of the digital modulation signal is detected by a four-digit data value detector. 6 is a clock gate, 6 is an output generator, and 7 is a preset pulse generation circuit. This operation will be explained based on FIG. It is detected whether the digital modulation signal di (i=1 to n) has a predetermined data value, and if Nd20, f=l (if Nd\0, f=L).

Further, the digital modulation signal di (i=1 to n) is as follows.

The signal is transferred to the preset circuit 2, and it is determined whether to output the cent input signal or the reset input signal to the set and resettable flip-flop of the binary counter 1. Regarding the flip-flop of the i-th bit of the binary kakunta 1, the outputs gi, gi of the preset circuit 2 become as follows by inputting the preset pulse e in accordance with the digital modulation signal di.

di=L72 If 1 gi=H, gi=Ldi=H then gi=L 7T=H However, preset pulse e
If not input, gi=, qi=L. If the reset input signal of the flip-flop is gi, and the set input signal is gi, then 7''1-1=C1-di (i21-n) due to the input of the sotobalse e.

Therefore, the digital modulation signal d1 is set in the binary counter by the preset circuit 2, and the binary counter has a count value Np (=, j: 2i-1
, di ), then i=] counting starts. The count value detector 3 detects that the count value N of the binary kakunta 1 has reached a predetermined count value NH.

If N==NH then b2L If N paralysis NH, set b=H.

NH in FIG. 2 is 2n-1.

When the precent value Np is set to binary kakunta 1 by the preset pulse e, the count value detector 3 outputs Np.
Since we are checking whether =NH or Np4NH, if NpkiNH, then b=Hf! Therefore, the clock gate 5 is in an open state, and the clock signal a passes through the clock gate 5 and is inputted as the clock signal a' into a binary counter, where it is counted from Np to NH. N p = N H
Then, since b=L, the clock gate 5 is in a closed state, holds the binary kakuntal 1-digit count value Np (=NH), and does not perform a counting operation.

FIG. 2 shows a case where the output generator 6 is constituted by a NOR gate which receives the output signal f of the count value detector 3 and the output signal f of the data value detector 4 as inputs.

Therefore, the pulse width modulation output is as follows.

If f=L, h is the inverted signal of b, If f==H, then h=L.

Therefore, the period Tl during which the pulse width modulation output becomes 11=l
Since l is the period of b=L, the following equation is obtained.

Th=2y-<1l-Np)/f2L= ('Np+
1')//f2La Next, the relationship between the preset operation and the <7 less width modulation output will be explained with reference to FIG. It is assumed that the preset clock pulse is generated by the preset clock pulse a in the preset clock pulse a, and when the pulse width is a period 141 of one clock, the period is 2n/c. This precent pulse e
The digital modulation signal Nd (=N
p) is preset, but in reality there is a delay of αb before the preset is reached, and a delay of αC from the time the preset is canceled until the end of the preset. Therefore, the binary counter 1 ignores one clock pulse a and counts from the next second pulse force until it reaches a predetermined count value NH. On the other hand, the output of the count value detector 3 becomes HK at the precented time, and becomes L at the time when the binary kakunta 1 reaches the count value NH. Here, the time at which the output of the count value detector becomes H is determined by the flip-flop most preset to 'f-<L' in the tri binary counter 1. During the b2H period, the clock pulse & passes through the clock gate 5 and is input to the binary kakuntal 1. Then, the preset operation is performed again with the next preset pulse e, and the same operation is repeated thereafter.

Here, the preset operation by the preset pulse e is accompanied by a delay time αb, and αb varies depending on the value of the modulation signal d due to variations in the propagation delay time of the flip-flop with set/reset and the preset circuit that constitute the binary kakunta. . Therefore, the pulse width modulation output is modulated by αb, and linearity is lost. That is, the period NP+2-αp of H when the binary counter 1 starts counting after being preset is also modulated by αb, resulting in non-linear distortion. For example, when integrating a pulse width modulation circuit, if the lower bits that operate at high speed are configured with high-speed flip-flops, and the upper bits that operate at low speed are configured with low-speed flip-flops, the difference in αb becomes large. Nonlinear distortion also becomes noticeable.

As explained above, the conventional pulse width modulation circuit has the drawback that the delay time αb at the time of presetting varies due to variations in each flip-flop of the binary counter 1 and the preset circuit, resulting in nonlinear distortion.

The present invention provides a pulse width modulation circuit that improves the above-mentioned drawbacks. FIG. 4 is a configuration example of the present invention, FIG. 6 is an operating waveform diagram when the first output generator is used in the present invention, and FIG. 6 is a diagram when the second output generator is used in the present invention. FIG.

The difference between the configuration example of the present invention shown in FIG. 4 and the conventional example shown in FIG. 1 is that a precent pulse e is input to the output generator 6. That is, in the present invention, as shown in FIG. 6, in order to eliminate the influence of the delay time αb on the output of the count value detector 3, the output generator 6 (first output generator), and is configured so that the output of preset pulse e is regulated (from H to
This is a second output generator configured such that the output of the output generator 6 is regulated at the time when the output voltage changes to L.

In this way, since the influence of αb can be removed, a pulse width modulated output with good linearity can be obtained.

FIG. 7 shows a specific circuit example of the present invention configured with a 5-bit binary counter, in which the first output generator 6 is used as the output generator, and its timing chart is shown in FIG.
It is a diagram.

Drawing numbers 1 to 6 in FIG. 7 correspond to FIG. 4. During the L period until the preset pulse e is generated, the outputs gi and gi of the preset gate 2 are L, and no preset operation is performed, but during the H period after the recent pulse e is generated, the contents of the digital modulation signal are By di, 9
Either i or gi becomes H, the binary kakunta 1 is reset, and Nd=10 becomes the preset value Np.
It is preset as . Here, the count value detector 3 is 2
When at least one bit of the binary counter 1 is "L", the output becomes H and the clock gate is opened, but when all bits reach HK, the output bFiLKfl clock gate is closed. Therefore, the output is H while counting up after a recent moment and reaches the maximum count value 31, but it becomes L after reaching the maximum count value 31 until the next recent moment, which corresponds to the digital modulation signal di. Since this is the output, if it is led to the output generator 6 and outputted via the NOR gate, the H period will be obtained as an output corresponding to the modulation signal di. Also, since the data value detector 4 outputs H when the data value Nd=o and L when the data value Nd4o, if this output f is used as the second input of the output generator 6, then Nd is ○. The output can be regulated to L only when Furthermore, if the preset pulse e is used as the third input of the output generator 6, the output can be set to L at the timing when the preset pulse e becomes H, so the output of the count value detector 3 is delayed at the moment of briscent. It is possible to eliminate variations in αb caused by the state becoming H after time αb.

FIG. 8 shows a specific circuit example of the second output generator that performs the operation shown in FIG. The output is pulse width modulated by a NOR gate inputting the inverted signal i, and during the period from the fall of the output of the count value detector 3 to the rise of the recent pulse e, the pulse width modulation output becomes h=H, and the pulse width modulation output becomes h=H. The configuration shown in FIG. 8 also provides the same effect as that shown in FIG. 7.

As described above, in the pulse width modulation circuit of the present invention, since the output of the count value detector is regulated by the preset pulse, the linearity of the amount of modulation of the pulse width modulation output is extremely excellent. Since the present invention can be adapted to shortened and faster clock pulses, it can provide a very effective means for digital-to-analog conversion of a digital modulation signal as a pulse width modulation output with high precision.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional pulse width modulation circuit, FIG. 2 is an operating waveform diagram of FIG. 1, FIG. 3 is an operating waveform diagram regarding nonlinear distortion of pulse width modulation output, and FIG. The block diagram of the pulse width modulation circuit, Figure 5 is an operating waveform diagram of the first output generator of the present invention, Figure 6 is an operating waveform diagram of the second output generator of the present invention, and Figure 7 is the operating waveform diagram of the second output generator of the present invention. FIG. 8 is a specific circuit example of the second output generator of the present invention. 1...Binary kakunta, 2...Blissent circuit, 3...Count value detector, 4...Data value detector, 5...・Clock gate, 6...
...output generator, a... river clock pulse, b...
...Count value detection signal, C...Counter count value, d...Digital modulation signal. e...Brecent pulse, f...group data value detection signal, w...preset circuit output, h...
...Pulse width modulation output. Name of agent: Patent attorney Masao Nakao, 1 person a1
2 illustrations 3 illustrations at the foot! Figure 4 Figure 5

Claims (1)

[Claims] ■ Gate means for gating clock pulses in accordance with a control signal, a binary kakunta for counting the output of the gate means, a pulse generation means for generating a preset pulse, and an output of the pulse generation means. presetting means for briscenting a digitally modulated signal encoded in binary into the binary kakuntas; count value detecting means for detecting that the count value of the binary kakuntas has reached a predetermined value; and the count value detecting means. means for applying the output of the gate as a control signal to the gate means, and an output means receiving as inputs the output of the count value detection means and the output of the pulse generation means, and the output means outputs a signal according to the digital modulation signal. A pulse width modulation circuit characterized in that it obtains a pulse width modulation output. (2) The output means includes means for detecting the data value of the digital modulation signal and regulating the pulse width modulation output to a low level or a high level using the detected output. Pulse width modulation circuit. The down counter is configured by using a down counter, the predetermined value of the count value detection means is set as the minimum value of the down counter, and the precent means is set to a flip-flop corresponding to the modulation signal. The pulse width modulation circuit according to claim 1 or 2, characterized in that the pulse width modulation circuit has a configuration in which: ■ The binary kakunta is configured with an amplifier kakunta using a resettable flip-flop, the mfJ count value detection means sets the constant value to the maximum value of the aso-bukakunta, and the preset means detects the aso-bukakunta only when the modulated signal is at the low level. 2. The pulse width modulation circuit according to claim 1, wherein the pulse width modulation circuit is configured to reset a flip-flop corresponding to the modulation signal. (2) The pulse width modulation circuit according to claim 1 or 2, wherein the preset pulse of the pulse generating means is generated by the output of the clock pulse generating means.