JPS6340926Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a modulation output control circuit used in a modulation/demodulation device.

FIG. 1 shows a modulation output control circuit used in a conventional modulation/demodulation device. When a binary 1 level signal is applied to the external control signal line 3, the output of the timer 6 is sent to the gate circuit 5 without delay, which opens the gate and sends the modulated output from the modulation circuit 4 to the output signal line 7. be done. When the signal applied to the external control signal line 3 changes to the binary 0 level, the output of the timer 6 is sent to the gate circuit 5 to close the gate after a certain period of time has elapsed since the signal changed to the binary 0 level. In this way, the gate is closed in consideration of the delay occurring in the modulation circuit 4.

This timer 6 is provided independently of the modulation circuit 4, and considering the stability of the modulation circuit 4, the delay time set in the timer 6 is longer than the delay time caused by the modulation process of the modulation circuit 4. It is necessary to set it for quite a long time.

However, if the delay time of timer 6 is increased,
When changing the communication speed, the faster the communication speed, the lower the communication efficiency will be. Furthermore, the method of switching the delay time for each communication speed has the disadvantage that the system configuration becomes complicated.

An object of the present invention is to provide a modulation output control circuit that eliminates the above-mentioned drawbacks.

The circuit of the present invention includes a gate circuit that controls passage or non-passage of a modulated output from a modulation circuit that changes communication speed by changing the frequency of a transmission timing pulse, and a gate circuit that is provided with the timing pulse and an external control signal. When a command to pass the modulated output is given by the external control signal, a gate control signal is immediately sent to the gate circuit to open the gate, and when a command not to pass the modulated signal is given by the external control signal. The synchronized timer is configured to count the timing pulses by a preset number and then send the gate control signal to the gate circuit to close the gate.

Next, the present invention will be explained in detail with reference to the drawings.

An embodiment of the present invention shown in FIG. 2 includes a gate circuit 5 that controls passage/non-passage of the modulated output from the multi-baseband modulation circuit 4, a timing pulse (given from the signal line 2), and an external control signal. (given from signal line 3) and a command to pass the modulated output is given by the external control signal, a gate control signal to open the gate is immediately sent to the gate circuit 5, and the modulated signal and a synchronous timer 6' configured to send a gate control signal to close the gate to the gate circuit 5 after counting the timing pulses by a preset number when a command not to pass is given from the external control signal. It is configured. Transmission data is given to a modulation circuit 4 from a signal line 1.

Next, the operation of this embodiment will be explained.

FIG. 3 is a circuit diagram showing FIG. 2 in more detail, and FIG. 4 is a time chart showing the operation of each part in FIG. In Figures 3 and 4,
The transmission data applied to the signal line 1 is sampled by the D flip-flop 41 by the output Q _A (signal 3) of the shift register 61 to which the timing pulse (signal 2) is input (signal 4). The sampled signal 4 is sent to the shift register 6 at the gate 42.
1's output Q _B and the gate circuit 42, it is inverted by the inverter 43 (signal 5) and the gate 44
given to. The AND gate 44 ANDs the exclusive OR output (signal 8) of the outputs Q _B (signal 6) and Q _C (signal 7) of the shift register 61 (signal 9) and supplies it to the flip-flop F/F 45.
F/F45 divides signal 9 by 1/2 (signal 1
0) Give to NOR circuit 5. On the other hand, the F/F 62, which together with the shift register 61 constitutes a timer 6', outputs an external control signal to the take-in gate 5 in response to the shift register output _Qo . Note that the clock of the shift register 61 uses a frequency sufficiently higher than that of the timing pulse. In this embodiment, the clock is ²⁴ times the timing pulse. In this way, the external control signal is synchronized with the timing pulse by the same clock using the common timer 6' with the modulation circuit 4, so that the delay times caused by the modulation circuit 4 can be made equal. That is, the synchronous timer 6' generates a gate control signal for immediately opening the gate of the gate circuit 5 in response to an external control signal applied from the signal line 3 changing from a binary 0 level to a binary 1 level. When the external control signal changes from a binary 1 level to a binary 0 level, the gate circuit counts timing pulses (given from the signal line 2) for a time equal to the amount of delay generated in the modulation circuit 5. A gate control signal is sent to close gate No. 5.

As described above, the present invention allows the delay time set in the timer to be equal to the delay time generated in the modulation circuit, and also maintains a constant ratio between the communication speed and the modulation output non-conduction control time even if the communication speed changes. This has the effect of improving communication efficiency. Furthermore, there is no need to consider the stability of the timer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional modulation output control circuit, and FIG. 2 is a block diagram showing an embodiment of the present invention. FIG. 3 is a detailed circuit diagram of FIG. 2, and FIG. 4 is a time chart showing waveforms at various parts of FIG. In the figure, 1, 2, 3, 7...signal lines, 4...modulation circuit, 5...gate circuit, 6, 6'...timer.

Claims (1)

[Scope of utility model registration request] a gate circuit that controls passage or non-passage of a modulated output from a modulation circuit that changes communication speed by changing the frequency of a transmission timing pulse; and a gate circuit that is supplied with the timing pulse and an external control signal and allows the modulated output to pass. When a command is given by the external control signal, a gate control signal to open the gate is immediately sent to the gate circuit, and when a command not to pass the modulation signal is given by the external control signal, a preset number of gates are sent to the gate circuit. A modulated output control circuit comprising: a synchronous timer configured to count timing pulses and then send the gate control signal to close the gate to the gate circuit.