JPS57121326A - Jhonson counter - Google Patents
Jhonson counterInfo
- Publication number
- JPS57121326A JPS57121326A JP667281A JP667281A JPS57121326A JP S57121326 A JPS57121326 A JP S57121326A JP 667281 A JP667281 A JP 667281A JP 667281 A JP667281 A JP 667281A JP S57121326 A JPS57121326 A JP S57121326A
- Authority
- JP
- Japan
- Prior art keywords
- stage
- ffs
- following stages
- output
- speed operation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
- H03K23/54—Ring counters, i.e. feedback shift register counters
- H03K23/542—Ring counters, i.e. feedback shift register counters with crossed-couplings, i.e. Johnson counters
Landscapes
- Shift Register Type Memory (AREA)
Abstract
PURPOSE:To make a high-speed operation possible, by connecting the output of an FF in the last stage of a shift register to the input of an FF in the first register and by setting the FF in the first stage and FFs in the second and following stages to states different from each other. CONSTITUTION:Four D (depletion) type FFs 11-14 are cascaded to constitute a shift register, and an output terminal Q of the FF14 in the last stage is connected to an input terminal D of the FF11 in the first stage. A clear signal is applied from a clear signal generating circuit 15 to a reset terminal S of the FF11 in the first stage and respective reset terminals of FFs 12-14 in the second and following stages to set the FF11 in the first stage and FF2 12-14 in the second and following stages to states different from each other. Clock pulses are applied to FFs 11-14, and the state of respective FFs is circulated. Consequently, since the output of each FF is inputted to the FF in the next stage directly, a high- speed operation is possible.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP667281A JPS57121326A (en) | 1981-01-20 | 1981-01-20 | Jhonson counter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP667281A JPS57121326A (en) | 1981-01-20 | 1981-01-20 | Jhonson counter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57121326A true JPS57121326A (en) | 1982-07-28 |
Family
ID=11644855
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP667281A Pending JPS57121326A (en) | 1981-01-20 | 1981-01-20 | Jhonson counter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57121326A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0638761U (en) * | 1992-11-12 | 1994-05-24 | 折谷 元征 | Hangers for clothing and personal items |
-
1981
- 1981-01-20 JP JP667281A patent/JPS57121326A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0638761U (en) * | 1992-11-12 | 1994-05-24 | 折谷 元征 | Hangers for clothing and personal items |
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