JPS57118425A - Digital pattern generating circuit - Google Patents

Digital pattern generating circuit

Info

Publication number
JPS57118425A
JPS57118425A JP56003050A JP305081A JPS57118425A JP S57118425 A JPS57118425 A JP S57118425A JP 56003050 A JP56003050 A JP 56003050A JP 305081 A JP305081 A JP 305081A JP S57118425 A JPS57118425 A JP S57118425A
Authority
JP
Japan
Prior art keywords
data
input
shift register
shift
input terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56003050A
Other languages
Japanese (ja)
Inventor
Mitsuyoshi Hashida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56003050A priority Critical patent/JPS57118425A/en
Publication of JPS57118425A publication Critical patent/JPS57118425A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/78—Generating a single train of pulses having a predetermined pattern, e.g. a predetermined number

Abstract

PURPOSE:To decrease the number of shift registers, by using a shift register in common and a set pattern to the shift register after switching the pattern. CONSTITUTION:In case a data input D1 of ''1'' is applied at a time point when the load input is set at L1, 00000101 is supplied to input terminals IA-IH of a shift register 3. The above-mentioned data set to these input terminals are successively read after a shift carried out by the clock signal. Thus serial data output of 10100000 is obtained through an output terminal OUT. When data input D2 of ''0'' is applied at a time point when the load input is set at L2, data of 00010011 is supplied to the input terminals IA-IH. This data is read after being shifted by the clock signal to obtain serial data of 11001000 through the terminal OUT. In other words, the function equivalent to two shift registers can be obtained by a shift register with use of loads L1 and L2 plus data D1 and D2.
JP56003050A 1981-01-14 1981-01-14 Digital pattern generating circuit Pending JPS57118425A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56003050A JPS57118425A (en) 1981-01-14 1981-01-14 Digital pattern generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56003050A JPS57118425A (en) 1981-01-14 1981-01-14 Digital pattern generating circuit

Publications (1)

Publication Number Publication Date
JPS57118425A true JPS57118425A (en) 1982-07-23

Family

ID=11546485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56003050A Pending JPS57118425A (en) 1981-01-14 1981-01-14 Digital pattern generating circuit

Country Status (1)

Country Link
JP (1) JPS57118425A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53105351A (en) * 1977-02-26 1978-09-13 Nippon Telegr & Teleph Corp <Ntt> Signal generator
JPS555544A (en) * 1978-06-28 1980-01-16 Matsushita Electric Works Ltd Timing pulse generation circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53105351A (en) * 1977-02-26 1978-09-13 Nippon Telegr & Teleph Corp <Ntt> Signal generator
JPS555544A (en) * 1978-06-28 1980-01-16 Matsushita Electric Works Ltd Timing pulse generation circuit

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