JPS57162850A - Code error detecting system - Google Patents

Code error detecting system

Info

Publication number
JPS57162850A
JPS57162850A JP56048255A JP4825581A JPS57162850A JP S57162850 A JPS57162850 A JP S57162850A JP 56048255 A JP56048255 A JP 56048255A JP 4825581 A JP4825581 A JP 4825581A JP S57162850 A JPS57162850 A JP S57162850A
Authority
JP
Japan
Prior art keywords
circuit
output
code error
terminal
outputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56048255A
Other languages
Japanese (ja)
Inventor
Koji Nishizaki
Masayuki Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56048255A priority Critical patent/JPS57162850A/en
Publication of JPS57162850A publication Critical patent/JPS57162850A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control

Abstract

PURPOSE:To detect code error in a half speed of a transmission clock, by reporting a count value of a count means in excess of a set value and controlling the addition means for the output of a frequency division circuit as inverting state. CONSTITUTION:Either one of frequency clocks outputted from a Q and a Q' terminal of an FF10 is selectively outputted from a switching circuit 11. An NAND circuit 12 outputs ''0'' when three inputs of frequency division clock to an FF8, an FF9 and the circuit 11 are at ''1''. An output of the terminal Q of an FF15 delayed by one time slot at a delay circuit 22 and an output of an inverter 16 are inputted to an NAND circuit 18. An output at the terminal Q' of an FF14 delayed by one time slot at a delay circuit, and an output of an inverter 17 are inputted to an NAND circuit 19. An integration circuit circuit 21 integrates an output signal of an NAND circuit 20 outputted when the generation of code error is detected, and switchingly controls the circuit 11 by generating an output if the code error frequently takes placed.
JP56048255A 1981-03-31 1981-03-31 Code error detecting system Pending JPS57162850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56048255A JPS57162850A (en) 1981-03-31 1981-03-31 Code error detecting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56048255A JPS57162850A (en) 1981-03-31 1981-03-31 Code error detecting system

Publications (1)

Publication Number Publication Date
JPS57162850A true JPS57162850A (en) 1982-10-06

Family

ID=12798329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56048255A Pending JPS57162850A (en) 1981-03-31 1981-03-31 Code error detecting system

Country Status (1)

Country Link
JP (1) JPS57162850A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59123343A (en) * 1982-12-29 1984-07-17 Sony Corp Method for encoding binary signal
JPS60100832A (en) * 1983-05-13 1985-06-04 ジ−メンス・アクチエンゲゼルシヤフト Method and device for decoding dc data stream endoced from n-bit code into (n+1)-bit code

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59123343A (en) * 1982-12-29 1984-07-17 Sony Corp Method for encoding binary signal
JPH0480576B2 (en) * 1982-12-29 1992-12-18 Sony Corp
JPS60100832A (en) * 1983-05-13 1985-06-04 ジ−メンス・アクチエンゲゼルシヤフト Method and device for decoding dc data stream endoced from n-bit code into (n+1)-bit code
JPS6366085B2 (en) * 1983-05-13 1988-12-19 Siemens Ag

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