JPS57179979A - Clock signal generating circuit - Google Patents
Clock signal generating circuitInfo
- Publication number
- JPS57179979A JPS57179979A JP56061434A JP6143481A JPS57179979A JP S57179979 A JPS57179979 A JP S57179979A JP 56061434 A JP56061434 A JP 56061434A JP 6143481 A JP6143481 A JP 6143481A JP S57179979 A JPS57179979 A JP S57179979A
- Authority
- JP
- Japan
- Prior art keywords
- level
- signal
- inverter
- output
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
Abstract
PURPOSE:To speed up the response speed to a change in a logical level of a bit signal of an address code signal, by outputting a clock signal synchronized with the address code signal. CONSTITUTION:When a logical level of a bit signal of an address code signal on an address line A0 changes from ''L'' to ''H'' level, the 1st signal S11 (output of an inverter 24) changes from ''H'' to ''L'' level. But the 2nd signal S12 (output of an inverter 25) remains ''L'' level because of a delay in the inverter 25. Thus, the output of an EXCLUSIVE-OR circuit 23 is reduced to ''L'' level, resulting in that an output terminal Pr is reduced to ''H'' level. After the time is elapsed by the delay of the inverter 25, the signal S12 changes from ''L'' to ''H'' level. Thus, the node of the circuit 23 is reduced to ''H'' and the output terminal Pr returns to ''L''.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56061434A JPS57179979A (en) | 1981-04-24 | 1981-04-24 | Clock signal generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56061434A JPS57179979A (en) | 1981-04-24 | 1981-04-24 | Clock signal generating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57179979A true JPS57179979A (en) | 1982-11-05 |
Family
ID=13170953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56061434A Pending JPS57179979A (en) | 1981-04-24 | 1981-04-24 | Clock signal generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57179979A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4710653A (en) * | 1986-07-03 | 1987-12-01 | Grumman Aerospace Corporation | Edge detector circuit and oscillator using same |
| JPS6337889A (en) * | 1986-07-31 | 1988-02-18 | Fujitsu Ltd | Memory device |
| US4879683A (en) * | 1987-09-28 | 1989-11-07 | Texas Instruments Incorporated | A gaas register file having a plurality of latches |
| JPH0495295A (en) * | 1990-08-10 | 1992-03-27 | Nec Ic Microcomput Syst Ltd | Memory circuit |
| US5264737A (en) * | 1991-08-06 | 1993-11-23 | Nec Corporation | One-shot signal generation circuitry for use in semiconductor memory integrated circuit |
-
1981
- 1981-04-24 JP JP56061434A patent/JPS57179979A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4710653A (en) * | 1986-07-03 | 1987-12-01 | Grumman Aerospace Corporation | Edge detector circuit and oscillator using same |
| JPS6337889A (en) * | 1986-07-31 | 1988-02-18 | Fujitsu Ltd | Memory device |
| US4879683A (en) * | 1987-09-28 | 1989-11-07 | Texas Instruments Incorporated | A gaas register file having a plurality of latches |
| JPH0495295A (en) * | 1990-08-10 | 1992-03-27 | Nec Ic Microcomput Syst Ltd | Memory circuit |
| US5264737A (en) * | 1991-08-06 | 1993-11-23 | Nec Corporation | One-shot signal generation circuitry for use in semiconductor memory integrated circuit |
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