JPS57188154A - Failure information signal detector - Google Patents

Failure information signal detector

Info

Publication number
JPS57188154A
JPS57188154A JP7321981A JP7321981A JPS57188154A JP S57188154 A JPS57188154 A JP S57188154A JP 7321981 A JP7321981 A JP 7321981A JP 7321981 A JP7321981 A JP 7321981A JP S57188154 A JPS57188154 A JP S57188154A
Authority
JP
Japan
Prior art keywords
signal
input signal
outputted
terminals
time slot
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7321981A
Other languages
Japanese (ja)
Inventor
Koji Tsutsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7321981A priority Critical patent/JPS57188154A/en
Publication of JPS57188154A publication Critical patent/JPS57188154A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/14Monitoring arrangements

Abstract

PURPOSE:To cope with an input signal with a failure information(AIS) signal detector independently of multiplexity of the input signal, by introducing a multiplex processing technology. CONSTITUTION:In a time slot B, an RAM 6 outputs the content (a) of an address 1 to DO1-DO4 as a signal 35. Since a signal 35 given to a terminal 8 is at H level, the output signal is inputted to terminals A-D of a counter circuit 7(AIS signal detection circuit) and (a) is outputted to terminals QA-QD as an output 39 of the counter circuit 7 with the 1st clock pulse. Further, since an input signal D1-2 is at H level, the value at the terminals QA-QD is counted by one with the 2nd clock pulse in the time slot B to the a+1 and stored in the address 1 newly. On the other hand, when an input signal 31 is at H level for 15 consecutive times, an H helvel is outputted to a CARRY terminal of the counter circuit 7 and it is held at ''15'' with a NAND gate 10 and an AND gate 2 and the AIS signal is outputted at a time slot D.
JP7321981A 1981-05-15 1981-05-15 Failure information signal detector Pending JPS57188154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7321981A JPS57188154A (en) 1981-05-15 1981-05-15 Failure information signal detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7321981A JPS57188154A (en) 1981-05-15 1981-05-15 Failure information signal detector

Publications (1)

Publication Number Publication Date
JPS57188154A true JPS57188154A (en) 1982-11-19

Family

ID=13511827

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7321981A Pending JPS57188154A (en) 1981-05-15 1981-05-15 Failure information signal detector

Country Status (1)

Country Link
JP (1) JPS57188154A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59112743A (en) * 1982-12-20 1984-06-29 Fujitsu Ltd Ais detecting circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59112743A (en) * 1982-12-20 1984-06-29 Fujitsu Ltd Ais detecting circuit
JPH0223103B2 (en) * 1982-12-20 1990-05-22 Fujitsu Ltd

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