JPS6251829A - Parallel interpolation dpcm coding circuit - Google Patents

Abstract

PURPOSE:To apply high speed interpolation DPCM coding with a low speed element by expanding an input signal into m-phase and applying forecast coding at each phase from the input signal and the result of operation from a predetermined other phase. CONSTITUTION:The input signal is split into 4-phase, and each is fed to one sample delay elements 111-114, 121-124 via delay elements 101-104 respectively the coding point signal of the own phase is generated from the one-sample delay elements 111-114, the value of the left side of the own phase is generated from the delay elements 101-104 and the value of the right side of the own phase is generated from the one-sample delay elements 121-124 to send the coding point signal of the own phase to the other phase and a forecast error signal of the own phase is extracted from subtractors 151-154. In this case, signals from other phases are given to adders 131-134. Since the forecast error signal of each phase is outputted in parallel at each coding point of time, the interpolation DPCM coding for a high speed picture signal is attained.

Description

[Detailed description of the invention] [) Already required] By configuring a conventionally known interpolation DPCM encoding method to enable parallel processing of unit time-series input signal sequences, an interpolation DPCM code for ultra-high-speed signals can be created. This was achieved using a small, low-speed circuit.

[Technical field of invention]

The present invention relates to a parallel interpolation DPCM encoding circuit, and more specifically, it is possible to perform interpolation DPCM encoding of ultra-high-speed signals such as high-definition TV signals with a band of 20 MHz or the like using a small-scale circuit consisting of low-speed arithmetic elements. Parallel interpolation DPC using
This relates to an M encoding circuit.

In data transmission, the transmission path may not have the bandwidth necessary for data transmission. As a means of transmitting data to be transmitted using such a transmission line to a receiving side, a means of compressing the data to within the bandwidth of the transmission line has been adopted.

One such means is an interpolation DPCM encoding method.

Even with this interpolation DPCM encoding method, as the signal to be encoded becomes faster, the circuit elements for interpolation DPCM encoding processing are required to have higher speed.

Therefore, there has been a need to develop means that can realize high-speed interpolation DPCM encoding of signals to be encoded, even though the circuit scale is relatively small and the elements used therein are low-speed.

[Conventional technology]

The encoding in a typical conventional interpolation DPCM encoding method for image signals is as follows. That is,
A method in which the four points of the left and right values of the same scanning line, the immediately above value belonging to the upper scanning line, and the immediately below value belonging to the lower scanning line are used to generate a predicted value and its encoding is performed. It is.

This system, as shown in FIG. 4, consists of a subtracter 50, a quantizer 51, an adder 52, a 1/4 multiplier 53. 1 line-1 delay element 54, 55. 1 sample delay element 56. 57.

[Problem that the invention seeks to solve]

According to the configuration shown in Fig. 4, the sampling frequency is 20MHz.
In the case of a weak signal, the intended interpolation DPCM encoding can be achieved relatively easily using TTL or MOS devices.

However, when the bandwidth of the input image signal becomes a high-definition TV signal such as 20 MHz, the sampling frequency becomes at least 4
Since the frequency exceeds 0 MHz, TTL or MOS devices cannot realize the intended interpolation DPCM encoding. Also, E
Even if a CL device is used, it is difficult to realize this in terms of operating speed.

The present invention was created in view of such problems, and provides a parallel interpolation DPCM encoding circuit that can perform interpolation DPCM encoding of an ultra-high-speed encoded signal using a small-scale circuit consisting of low-speed elements. It's about doing.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention. The present invention is configured such that a unit time-series input signal sequence is expanded into its own phase, and interpolation DPCM encoding is performed in parallel for each phase. For each phase, a prediction error signal generation circuit (encoder) 11 (
i=1.2. 32,...m) are provided. This prediction error signal generation circuit 11 is configured as follows.

That is, a signal generation circuit 21 receives a corresponding unit time series phase input signal and generates a coding point signal and a predicted value generation signal.
and the generation of a prediction error signal for the own phase among the predicted value generation signals generated by the signal generation circuit of the own phase and the signals generated from the signal generation circuit of the phase that has a predetermined phase relationship with the own phase. The subtracter 41 subtracts the predicted value of the current phase from the encoded point signal of the current phase, and the quantizer 51 quantizes the output signal of the subtractor 4I. It consists of

[Effect]

Each unit time-series phase input signal of the unit time-series input signal sequence expanded into the own phase is supplied to the signal generation circuit of the own phase, and a coding point signal and a predicted value generation signal are generated. The encoded point signal is supplied to the subtracter of the same phase, and the predicted value generation signal is supplied to the predicted value generation circuit. The predicted value generation circuit is also
Among the signals generated from the signal generation circuit of the phase having a predetermined phase relationship with the own phase, a signal useful for generating a prediction error signal of the own phase is also supplied. By supplying this latter signal to the signal generation circuit in parallel for each phase, the predicted value generation signals required for each phase can be prepared at the same time.

In this way, the predicted value is subtracted from the coding point signal in each phase, the difference signal is quantized, and a prediction error signal can be generated in parallel at each code dead center time, so it is possible to generate a high-speed unit. Interpolative DPCM encoding of a time-series input signal sequence can be performed under a small-scale circuit using slow elements.

[Embodiment] FIG. 2 shows an embodiment of the present invention. In this embodiment, each phase image signal of an image signal developed into four phases is interpolated in parallel.
This is an example of M encoding.

The encoder for each phase includes a 1-line-1 delay element 101 that receives the phase image signal, 1-sample delay elements 111 and 121 connected in series to the output of the 1-line-1 delay element 101, and the left value of the scanning line of the own phase. and an adder 13+ that receives the values on the right side, the immediately above value belonging to the upper scanning line, and the immediately below value belonging to the lower scanning line, and a 1/4 multiplier 14i that multiplies the output signal of the adder 131 by 1/4. 1 sample delay element 11i
1/4 multiplier 1 from the output signal of the self-phase coding point signal.
a subtracter 151 that subtracts the output signal of 4□, that is, the predicted value;
The subtracter 151 includes a quantizer 161 that quantizes the output signal of the subtracter 151. Then, the adder 13 receives the output signal of the 1 line-1 delay element 101 as the left value,
It receives the output signal of the 1-sample delay element 121 as the value on the right, receives the input signal to the l-line-1 delay element 104 as the value immediately above it, and receives the input signal to the l-sample delay element 112 as the value directly below it.
receives the output signal of Adders 132 and 133 add 1 of the own phase.
Output signals of line-1 delay elements 102 and 103 (values on the left), output signals of 1-sample delay elements 122 and 123 (
value on the right), 1 sample delay element 111, 112 of the previous phase
It receives the output signal (directly above value) and the output signal (directly below value) of the next-phase 1-sample delay elements 113 and 114. Also, the adder 134 calculates 1 line - 1 delay element 10 as the left value.
4 output signal as the right value, 1 sample delay element 1
24 output signal as the immediate value, 1 sample delay element 1
13 output signal as a direct value, 1 sample delay element 1
2. It receives the output signal of the 1-line-1 delay element 14 connected to the output of the 1-line-1 delay element 14. Note that when the accuracy of the predicted value is allowed to be low, the fourth phase image signal is supplied to the adder 13°, and the output signal of the 1 line-1 delay element 14 is supplied to the adder 134. It may be configured so that it is not performed.

Next, the present invention with the above configuration will be explained in detail.

Each phase image signal of the image signal expanded into 4 phases is 1 of the corresponding phase.
Line-1 delay elements 101, 102, 103, 104 and 1 sample delay element 111゜11, a+ lls
, l14; 121, 122, 123°124. As a result, the one-sample delay elements 111, 112 .
113.114 generates the encoding point signal of the own phase, and ■Line-1 delay elements 101, 102, 103,
From 104, the value on the left side of the self-phase is also 1 sample delay element 1
21°122, 123, and 124 generate values on the right side of the self-phase. In addition, the directly above value is used as the fourth phase image signal in the first phase, and in the second to fourth phases, the one-sample delay element II1.11 is used, respectively.
2.113 output signals, and the immediate value is the 1 sample delay element 112 for the first to third phases
．． 113,11. In the fourth phase, it is used as the output signal of the 1-line-1 delay element 14.

In this way, each of the logical arithmetic units 131 to 134 can be supplied with the predicted value generation signals at the same time, so that each of the logical arithmetic units I
The output signals from L to 134 are sent to the corresponding 1/4 multiplier 1
The predicted values are multiplied by a 1/4 coefficient in steps 41 to 144 and supplied to corresponding subtracters 151 to 154 as predicted values. Each predicted value is subtracted from the coding point signal of each phase by corresponding subtracters 151 to 154, and the difference signal is quantized by quantizers 161 to 164 and output as a prediction error signal. Generalizing this prediction error signal, we get
It will look like this:

Image data is expressed as a matrix of pixel values with M rows and N columns (S (
i, j) I 0515M-1, O≦j≦N-1)
The prediction error signal e (
IIJ ) is e (i, j ) = S (i, j ) −−(S (
i-1,j)+S(i,j-1)+S(i,j
+1) +S (i+1.j))32,...(1) It can be expressed as follows.

These prediction error signals for each phase are output in parallel for each encoding point signal, so high-speed image signal interpolation DP
CM encoding can be performed under a small-scale circuit made up of low-speed elements.

Figure 3 shows a parallel interpolation DPC that receives the parallel prediction error signal generated by the circuit in Figure 2 and generates four-phase parallel reproduction signals.
This is an M decoding circuit. This decoding circuit receives prediction error signals of each phase in parallel and generates reproduction signals for each phase. Generalizing this decoding process, by transforming equation (1), the reproduced signal S (i+1.j) becomes S (i+1.j) = 43 (i, j) -4e
(Lj)−(S(i−1,j)+S(i,
j-1) +S (i, j+1) )32,...(2) It can be expressed as: In order to obtain the reproduced signals of each phase expressed by equation (2) in parallel, the parallel interpolation DPCM decoding circuit is configured as follows.

In the first phase, the prediction error signal is transmitted to the 4 multiplier 20
1 to the subtracter 231, and is subtracted from the values shown by the first and third terms of equation (2) from the subtracter 241, and is subtracted from the values shown by the first and third terms of equation (2). The signal is then output as a playback signal. The value of the first term of equation (2) to the subtracter 241 is sent from the output signal of the 1-sample delay element 26 via the 4-multiplier 29, and the value of the third term of equation (2) is It is sent from the 1 line-12 sample delay element 61 and the 1 sample delay element 25, 27. The input of 1 sample delay element 25 is connected to the output of 1 line-12 sample delay element 62.

In the second phase as well, the signal output as the first phase reproduction signal and the signal used to generate the first phase decoding point signal are delayed by one sample period. is used to generate the second phase decoding point signal. In other words, by supplying the output signal of the 1 sample delay element 31 to the subtracter 242 via the 4 multiplier 37, equation (2)
The first term of 1-sample delay element 28, 30.32
The output signal of is taken as the third term of equation (2). In this way, the decoding point signal generated from the subtracter 24
02 is subtracted by the value of the second term of equation (2), and the 1-sample delay elements 39 to 42 and the 2-sample delay element 43 are subtracted.
．． 44 and output as a reproduction signal.

This second phase decoding point signal is generated in the third and fourth
This also applies to the phase of That is, subtractor 2 in the third phase
The value of the first term of equation (2) to 43 is 1 sample delay element 4
The output signal of 0 is supplied via the 4 multiplier 45, and the formula (2
) is the value of the 1-sample delay element 33, 39.41
Supplied from. Also, the value of the first term of equation (2) to the subtractor 244 in the fourth phase is supplied by the output signal of the one sample delay element 49 via the four multiplier 58, and the value of the third term of equation (2) is The value of is provided by the one sample delay element 42.48.50.

The third phase decoding point signal generated from the subtracter 243 is sent to the 2-sample delay element 46 in the subtracter 233.
．． 47 and the value of the second term of equation (2) after passing through the 4-multiplier 203, and is output as a reproduced signal via the 1-sample delay elements 48-51 and the 2-sample delay element 52. Further, the fourth phase decoding point signal generated from the subtracter 244 is sent to the 2-sample delay element 54 in the subtracter 234.
The output signal of ~56 is subtracted by the value of the second term of equation (2) after passing through the 4 multiplier 204, and the output signal is subtracted by the value of the second term of equation (2) through the 4 multiplier 204,
60 and output as a reproduction signal.

In this way, the decoding point signals of each phase can be parallelized by using the signals that are generated in the phases that have a predetermined phase relationship with each phase and are useful for generating the decoding point signal of that phase. Since the parallel prediction error signal is generated automatically and used to generate a reproduction signal, a high-speed image signal can be generated from a parallel prediction error signal from a small-scale circuit composed of low-speed elements.

Although the above embodiment describes an image signal expanded into four phases, other signals expanded into multiple phases may be used. Also, for one scanning line among the four scanning lines developed in four phases, P
When CM encoding is performed or when only values on the same scanning line are used as predicted values, an encoding circuit can be configured with four-phase signals without giving a delay of one scanning line to the input signal. This relationship also applies to other phase numbers.

〔Effect of the invention〕

As described above, according to the present invention, high-speed interpolation DPCM encoding of unit time-series signals can be realized with a small-scale circuit composed of low-speed elements.

[Brief explanation of drawings]

Fig. 1 is a diagram illustrating the principle of the present invention, Fig. 2 is a diagram showing an embodiment of the present invention, Fig. 3 is a diagram showing an example of a parallel interpolation DPCM decoding circuit, and Fig. 4 is a conventional diagram. It is a figure showing an example of a circuit. In Figure 1, 21.22. 32,...2m is a signal generation circuit, L, 3
2. 32,...3m is a predicted value generation circuit, 41.4□,
32,...4m is a subtractor. 51.52. 32,...5m are quantizers. Conventional circuit diagram Figure 4

Claims (1)

[Claims] A signal generator for generating a coding point signal and a predicted value generation signal in response to a corresponding unit time series phase input signal for each phase of a unit time series input signal sequence expanded into m phases. Circuit (2_1,
2_2,...2_m) and the predicted value generation signal generated by the signal generation circuit of the own phase and the signal generated from the signal generation circuit of the phase that has a predetermined phase relationship with the own phase. A predicted value generation circuit (3_1, 3_2,
...3_m), a subtractor (4_1, 4_2, ...4_m) that subtracts the predicted value of the own phase from the encoded point signal of the own phase, and a quantum that quantizes the output signal of the subtractor (4_1, 4_2, ...4_m). A parallel interpolation DPCM encoding circuit comprising encoders (5_1, 5_2, . . . 5_m).