JPH0473352B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a band compression processing device for image signals.
In particular, it relates to an encoding circuit that performs band compression and encoding at ultra-high speed.

[Conventional technology]

Various types of encoding methods have been proposed to band-compress and encode image signals.
A typical example is DPCM (Differential pulse
code modulation) encoding method. The DPCM encoder has a basic configuration as shown in _FIG .
By subtracting p _i , the prediction error e _i is temporarily held in flip-flop (FF) 2, and then read out in the next sampling period and quantized by quantizer (Q) 3. Prediction error Q(e _i )
is output as The predicted value p _i is temporarily held in the flip-flop (FF) 4, and then read out in the next sampling period and added to the quantized prediction error Q(e _i ) in the adder 5, so that
The predicted value p _i corresponding to the current input is obtained at its output. Since the predicted value p _i is generated based on the prediction function, the frequency of occurrence of the difference value from the input signal changes, and therefore the quantized prediction error Q(e _i ) has less information than the input signal. This results in bandwidth compression.

In a DPCM encoder, the operations of each part must be completed during the sampling period for its operation, and in the case of the encoder shown in FIG. , is determined by the sum of the operation times of subtracter 1 and flip-flop 2. For this reason, if the input signal is a very high-speed signal, it will not be possible to process it as it is, so it will have to be expanded into multiple phases and processed as low-speed data, as shown in FIG.

FIG. 2 shows an example of a DPCM encoder that performs calculations by expanding into three phases. In the figure, reference numeral 6 denotes a speed converter, which expands an input signal having an operating speed f _s into three phases to obtain three outputs a, b, and c each having an operating speed f _s /3. 7, 8, and 9 are DPCM encoder blocks each having the same configuration as in FIG. 1, and process outputs a, b, and c, respectively, to generate an output of a quantized prediction error.

In the DPCM encoder shown in FIG. 2, each of the DPCM encoders 7, 8, and 9 only needs to have an operating speed that is 1/3 of the operating speed of the input signal. Although it is possible to process signals at higher speeds, the circuit size increases.

The DPCM encoder shown in FIGS. 1 and 2 performs encoding using the difference value between data one sampling period before and input data.
A DPCM encoder that performs encoding using a difference value between data n sampling periods before and input data may be required. Such an encoder is, for example,
This is necessary when trying to give the encoder filter characteristics whose transfer functions match the DC component (f = 0) of the color television signal and the subcarrier signal _fsc , and the required The filter characteristics are realized by choosing the sampling frequency f _s to be n/2f _sc .

FIG. 3 shows a conventional example of such an encoding circuit, and shows the basic configuration when encoding is performed using a difference value between data five sampling periods before and input data. In the figure, the same parts as in Figure 1 are indicated by the same numbers, 10, 11.
are each flip-flop (FF×5).

FIG. 3 shows that in the encoding circuit, flip-flops 10 and 11 each consist of 5 steps;
Data is held and output until after 5 sampling periods. As a result, calculations are performed in the same manner as described with reference to FIG. 1, and a quantized prediction error can be obtained as an output. And in this case, corresponding to a high definition television (HDTV) signal having a subcarrier signal frequency f _sc =24.3MHz,
By selecting 2.5 f _sc as the sampling frequency, it is possible to realize filter characteristics in which the transfer function matches the DC component and the subcarrier frequency f _sc .

However, as with the case of FIG. 1, the encoding circuit of FIG. 3 cannot process extremely high-speed signals. That is, in FIG. 3, the operating speeds of subtracter 1, adder 5, and quantizer 3 are set to 10 ns, respectively.
10ns and 20ns, the upper limit of the input frequency at which the encoder in Figure 3 can operate is 25MHz, which is
It is not possible to process input signals that have a data rate of 60MHz (13ns) in the signal.

FIG. 4 shows an example of a circuit when the encoding process of FIG. 3 is implemented in a divided configuration. In this figure, the same parts as in FIG. 1 are indicated by the same numbers.
12 and 13 are flip-flops (FF×
4).

In the encoding circuit of FIG. 4, flip-flops 12 and 13 each consist of four steps;
The data is held and output until after 4 sampling periods. In this case, the quantizer 3 is disposed between the flip-flop 12 and the flip-flop 2, and only needs to operate between the clocks of the final step of the flip-flop of the flip-flop 12 and the clocks of the flip-flop 2. The speed is determined by the sum of the operating speeds of subtracter 1 and adder 5 or the operating speed of quantizer 3. Similarly to Figure 3, the operating speeds of subtracter 1, adder 5, and quantizer 3 are set to 10ns, 10ns, and 20ns, respectively.
Then, the upper limit of the input frequency at which the encoding circuit in Figure 4 can operate is 1/(10×10 ^-9 +10×10 ^-9 )Hz or 1/(20×10 ^-9 )Hz, or 50MHz. , this still cannot process input signals with a data rate of 60MHz.

FIG. 5 shows an example of the configuration of the encoding circuit in a parallel configuration. In the same figure, 14 is a serial/parallel conversion circuit (S/P), 15 _-1 ,..., 15 _-5 is a DPCM
It is an encoder block.

In FIG. 5, a serial-to-parallel conversion circuit 14 converts the input signal into five-phase signals a, b, c, d, and e, and outputs the resultant signals. DPCM encoder block 15 _-1 ,...,
_15-5 each have a similar configuration to the DPCM encoder shown in FIG. 1, and each has a processing speed of 25 MHz. Therefore, although the encoding circuit of FIG. 5 has a processing speed of 25.times.5 MHz as a whole and can process an input signal having a data rate of 60 MHz, on the other hand, the circuit scale is extremely large.

As described above, conventional encoding circuits have had the problem that the circuit size increases when attempting to process ultra-high-speed signals.

[Problem to be solved by the invention]

The present invention attempts to solve the problems of the prior art, and its purpose is to
In addition to improving processing speed in the encoder,
An object of the present invention is to provide an encoding circuit that prevents an increase in circuit scale.

[Means to try to solve the problem]

The structure of the present invention for achieving the above object is as shown below. That is, the present invention provides a speed conversion circuit that converts serial input data into m-phase parallel outputs with a speed of 1/m (m is an integer), and converts the output of one phase of the m-phase parallel outputs into input data. and m encoders that perform encoding by quantizing the difference between input data and predicted values, and the encoded outputs of the m encoders are used as the first inputs to obtain local decoded outputs. m adders, the local decoded outputs of each of the m adders are successively inputted as predicted values of the encoder of the other phase, and the input of the adder of the same phase as the encoder of the other phase is provided. In addition, each encoder and each adder are connected so that the input data of each encoder and the predicted value are n sampling periods (n is an integer) of the serial input data. It has a configuration as an encoding circuit characterized in that a delay element with a speed of 1/m is arranged at the input stage or the output stage.

〔Example〕

FIG. 6 shows, as an embodiment of the encoding circuit of the present invention, a configuration in which encoding is performed using the difference value between data five sampling periods before and input data, as in the case of FIG. 3. In the figure, 21 is a serial/parallel conversion circuit (S/P), 22 is a subtracter, 23,
24 is a flip-flop (FF), 25 is a quantizer
(Q), 26, 27 are flip-flops (FF), 28
is an adder, 29 is a subtracter, 30, 31 are flip-flops (FF), 32 is a quantizer (Q), 33, 3
4 and 35 are flip-flops (FF), and 36 is an adder. Further, FIG. 7 is a flowchart showing the processing order in the encoding circuit of FIG. 6. In the same figure, ,,,, a-e, b-
c indicates a signal of each part, and each signal is indicated by the same reference numeral at a corresponding position in FIG.

The serial/parallel conversion circuit 21 converts the input signal into a two-phase signal a, and outputs the signal a. In Fig. 7, when the input signals are in the order of A ₁ , B ₁ , C ₁ , D ₁ , E ₁ , A ₂ , ..., the signals are A ₁ , C ₁ , D ₁ , E ₁ , B ₂ ，
...and the signals become B ₁ , D ₁ , A ₂ , C ₂ .... In FIG. 6, a subtracter 22, a flip-flop 2
3, 24, quantizer 25, flip-flop 2
6, 27 and an adder 28 (hereinafter referred to as encoder block A), if the output signal of the adder 28 is used as the predicted value signal in the subtracter 22, the encoder block (hereinafter referred to as encoder block A) is ₁ , B ₂ , ...), the predicted value is = (A' ₁ , C' ₁ ...), so the difference between the data two sampling periods before and the input data in the sampling period that has been slowed down to 1/2. It takes the form of an encoder that calculates the prediction error by . An encoder block (hereinafter referred to as encoder block B) consisting of a subtracter 29, flip-flops 30 and 31, a quantizer 32, flip-flops 33, 34, and 35, and an adder 36
If the output signal of the flip-flop 35 is used as the predicted value signal in the subtracter 29, then (=B′ ₁ , D′ ₁ ...) for the inputs (=C ₂ , E ₂ , ...) Since this is the predicted value, the encoder is configured to calculate the prediction error from the difference between the input data and the data three sampling cycles ago at a sampling cycle that has been slowed down to 1/2.
However, in FIG. 6, the signal in encoder block A two sampling periods earlier is used as the predicted value signal in encoder block B, and the signal three sampling periods earlier in encoder block B is used as the predicted value signal in encoder block A. are used as input signals, respectively.
The difference signals ae and bc are obtained. The signals a-e and b-c are quantized by the quantizers 25 and 32, respectively, to obtain signal outputs of quantized prediction errors, but both outputs are data from five sampling periods ago. This is the prediction error determined by the difference from the input data.

In FIG. 6, the processing speed of encoder blocks A and B is determined by the sum of the operating speeds of adder 28 and subtracter 29 or by quantizer 25 or quantizer 32.

Similarly to FIG. 3, the operating speeds of the adder 28, subtracter 29, quantizer 25, and quantizer 32 are
10ns, 10ns, 20ns, 20ns, respectively 1/
(10×10 ^-9 +10×10 ^-9 )Hz or 1/(20×10 ^-9 )
It has a processing speed of Hz or 50MHz. 60M
An input signal having a data rate of Hz is converted into two phases by the serial-to-parallel converter circuit 21, and since both input signals have a data rate of 30MHz, the encoder shown in FIG. It is capable of processing input data with a data rate of 60MHz. In this way, according to the encoder of FIG.
Although the circuit scale is smaller than the encoder shown in the figure,
The required data processing speed can be easily achieved.

FIG. 8 shows the configuration of another embodiment of the encoding circuit of the present invention in which encoding is performed using the difference value between data 11 sampling periods ago and input data. In the figure, 41 is a serial/parallel conversion circuit (S/P) that converts the speed of input data into three phases. 42 is a subtracter, 43 and 44 are flip-flops (FF), 45 is a quantizer (Q), 46 and 47 are flip-flops (FF), 48 is an adder, and 49 is a flip-flop (FF). It constitutes the container block A. 50 is a subtractor, 5
1 and 52 are flip-flops (FF), 53 is a quantizer (Q), 54 and 55 are flip-flops (FF),
56 is an adder, and 57 and 58 are flip-flops (FF), which constitute encoder block B. 59 is a subtracter, 60, 61 are flip-flops (FF), 62 is a quantizer (Q), 63, 6
4 is a flip-flop (FF), 65 is an adder, 6
6 and 67 are flip-flops (FF),
These constitute encoder block C. FIG. 9 is _a flowchart showing the processing order in the encoding circuit of FIG.
When 2 ₁ , 3 ₁ , 4 ₁ , . be.

Figure 8 shows that in the encoding circuit, encoder block C uses the local decoded output (=7 ₁ , 8 ₁ ) of encoder block A as the predicted value for the input (= 7 ₂ , 10 ₂ , ...). Therefore, an encoder is formed that calculates the prediction error based on the difference between the input data and the data three sampling periods ago at a sampling period slowed down to 1/3, and encoder blocks A and B each calculate the prediction error using the difference between the input data and the data three sampling periods ago. This forms an encoder that calculates the prediction error based on the difference between the data and the input data.
The signal from encoder block A three sampling periods before is used as the predicted value signal at encoder block C, and the signal from encoder block C four sampling periods before is used as the predicted value signal at encoder block B. , the signal from encoder block B four sampling periods ago is used as the predicted value signal in encoder block A, and each encoder block A, B, and C each input signal using these predicted value signals. The system calculates the difference between the two and outputs a quantized prediction error signal. Therefore, in the encoding circuit shown in FIG. 8, each output is a quantized prediction error obtained from the difference between the data 11 sampling periods ago and the input data. FIG. 9 shows an example of the relationship between the input data of each encoder block A, B, and C and predicted values.

In FIG. 8, the processing speeds of encoder blocks A, B, and C are as follows: subtracters 42, 50, 59, adder 4;
8, 56, 65, and the operating speed of each element of quantizers 45, 53, and 62. Since the operating speed of a quantizer is usually lower than the operating speed of an adder or subtracter, the processing speed of encoder blocks A, B, and C is determined by the operating speed of the quantizer.

If the operating speed of the quantizer is greater than the sum of the operating speeds of the adder and subtracter, for example 15 ns, the processing speed of encoder blocks A, B, and C will be approximately 67 MHz.
Therefore, faster operation than the case shown in FIG. 6 can be realized.

〔Effect of the invention〕

As explained above, according to the encoding circuit of the present invention, serial data can be converted to m at a speed of 1/m (m is an integer).
m codes that perform encoding by converting into parallel outputs of phases, using the output of one phase among the parallel outputs of the m phases as input data, and quantizing the difference between the input data and the predicted value. and m adders which take the encoded outputs of the m encoders as first inputs and obtain locally decoded outputs, and sequentially convert the locally decoded outputs of each of the m adders into other phase signals. It is connected so that it is input as the predicted value of the encoder and the second input of the adder of the same phase as the encoder of the other phase, and the time difference between the input data of each encoder and the predicted value is A delay element with a speed of 1/m is placed at the input stage or output stage of each encoder and each adder so that the sampling period of the input data is n (n is an integer), so high-speed operation is possible with a small circuit scale. It is possible to realize an encoding circuit that can perform the following steps.

[Brief explanation of drawings]

Figure 1 shows the basic configuration of a DPCM encoder, Figure 2 shows the configuration of an encoder used for ultra-high-speed input, and Figure 3 shows the difference between data 5 sampling cycles ago and input data. Figure 4 is a diagram showing the principle configuration of an encoding circuit that encodes by value.
FIG. 5 is a diagram showing an example of a configuration when the encoding circuit shown in FIG. 3 is configured in a divided configuration; FIG.
FIG. 6 is a diagram showing the configuration of an embodiment of the encoding circuit of the present invention in which encoding is performed using the difference value between data five sampling periods before and input data, as in the case of FIG. 3; The figure is a flowchart showing the processing order in the encoding circuit shown in Figure 6, and Figure 8 is a flowchart showing the processing order in the encoding circuit of the present invention. FIG. 9 is a flowchart showing the processing order in the encoding circuit shown in FIG. 8. 1: Subtractor, 2: Flip-flop (FF),
3: Quantizer (Q), 4: Flip-flop (FF),
5: Adder, 6: Speed converter, 7, 8, 9:
DPCM encoder block, 10, 11: flip-flop (FF x 5), 12, 13: flip-flop (FF x 4), 14: serial/parallel conversion circuit (S/
P), _15-1 ,..., _15-5 : DPCM encoder block, 21: Serial-to-parallel conversion circuit (S/P), 22: Subtractor, 23, 24: Flip-flop (FF), 2
5: Quantizer (Q), 26, 27: Flip-flop (FF), 28: Adder, 29: Subtractor, 30, 3
1: Flip-flop (FF), 32: Quantizer
(Q), 33, 34, 35: Flip-flop (FF), 36: Adder, 41: Serial-to-parallel conversion circuit (S/P), 42: Subtractor, 43, 44: Flip-flop (FF), 45: Quantization Vessel (Q), 46,4
7: Flip-flop (FF), 48: Adder, 4
9: Flip-flop (FF), 50: Subtractor, 5
1, 52: flip-flop (FF), 53: quantizer (Q), 54, 55: flip-flop (FF),
56: Adder, 57, 58: Flip-flop (FF), 59: Subtractor, 60, 61: Flip-flop (FF), 62: Quantizer, 63, 64: Flip-flop (FF), 65: 2 adder, 66 ，
67: Flip Flop (FF).

Claims (1)

[Claims] 1 A speed conversion circuit that converts serial input data into m-phase parallel outputs with a speed of 1/m (m is an integer), and the output of one phase of the m-phase parallel outputs as input data; m encoders that perform encoding by quantizing differences with predicted values, and m adders that take the encoded outputs of the m encoders as first inputs and obtain locally decoded outputs. The local decoded outputs of each of the m adders are sequentially inputted as predicted values of the encoder of the other phase, and the second input of the adder of the same phase as the encoder of the other phase. The input stage or output stage of each encoder and each adder is connected so that the time difference between the input data of each encoder and the predicted value is n (n is an integer) sampling period of the serial input data. 1. An encoding circuit characterized in that a delay element having a speed of 1/m is arranged in the circuit.