JPS5932951B2 - DPCM encoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a DPC related to transmission band compression of color television signals.
M(DifferentialPulseCodeMo
This relates to the circuit configuration of the duration0 encoder.

FIG. 1 is a block diagram showing the circuit configuration of a conventional DPCM encoder that employs two-dimensional prediction.
, bit converter 4, latch circuit 5, adder 6, adder 1
, a predictor 8, a delay circuit 9, a predictor 10, an input signal terminal 11, an output signal terminal 12, a sampling signal input terminal 13, and a latch signal input terminal 14,
The video signal received at the input signal terminal 11 is converted into an A/D converter by the sampling signal from the sampling signal input terminal 13.
The output from the subtracter 2 of the digital output and the predicted signal that has passed through the latch circuit that receives the same latch signal as the sampling signal from the latch signal input terminal 14 reaches the quantizer 3, which is the digital output of the converter 1. , the output of the quantizer 3 passes through the bit converter 4 to obtain a desired PCM output signal from the output signal terminal 12.

However, in the circuit configuration of FIG.
is a previous value predictor, which determines a predicted value from the sample value of the previous sample in the same line in the same field, and the predictor 10 is a two-dimensional predictor, which determines the predicted value from the previous line or the line before the previous, etc. is a predictor that determines. Then, each output of the predictor 8 and the predictor 10 via the delay circuit becomes a predicted signal having a predicted value to be applied to the subtracter 2 and the adder 6 in the adder 7. Therefore, depending on the amount of time required to operate the loop circuit formed by cyclically connecting the subtracter 2, quantizer 3, adder 6, predictor 8, adder 7, and latch circuit 5 in this order, Each one cycle time of the sampling signal applied to the A/D converter 1 and the latch signal applied to the latch circuit 5 is limited. For this reason, in the circuit configuration shown in FIG. 1, the circuit components are integrated into ICs in an effort to make the loop circuit operate at high speed, but the frequency of the sampling signal is approximately 9M.
When the frequency was higher than Hz, the circuit operation became unstable. However, in the color television field, it is known that it is optimal to use a frequency of about 10.7 MHz, which corresponds to three times the color subcarrier, for the sampling signal in order to remove beads. Therefore, the DPCM of the circuit configuration shown in FIG.
The encoder was insufficient. In addition, to explain the predicted value of the predicted signal in the circuit configuration of FIG. 1, the A/D
If the output of the converter 1 is x and the predicted value at that point is (Regulation) Q + Gut. In the following explanation, assuming that this (x order) Q+g is q, the output of the adder 7, that is, the predicted value at the new sample is
Then, it becomes command+1-Plq+P2q, and intersection+1-q
(P, +P2).

Here, P1 is the coefficient of predictor 8, P2 is the coefficient of predictor 1
It is a coefficient of 0. The predicted values of the predicted signals related to FIG. 1 have the above relationship. The present invention provides a DPCM that solves the above drawbacks.
For this purpose, the number of circuit components of the loop circuit related to the operation of the predictor 8, which is the previous value predictor, is reduced, that is, the same A/ It is characterized by a loop circuit formed by cyclically connecting a subtracter receiving the D converter output, a quantizer, a first previous value predictor, a first adder, and a latch circuit in this order, and further , the latch circuit of this loop circuit is connected to the first adder via the second previous value predictor and the second adder sequentially, and the quantizer of this loop circuit is connected to the first predictor in common. and 2 for the third adder connected to the latch circuit.
A third predictor which is a dimension predictor and an adder 7 which is a delay
given to.

Next, if the output of the adder 7, that is, the predicted value at the new sample is ◇+1, then the circuit configuration in FIG. 2 and the circuit configuration in FIG. 1 described above are related to the predicted value of the predicted signal. It can be understood that the conditions are the same.

On the other hand, in the DPCM encoder having the circuit configuration shown in FIG. It is in a loop circuit connected to. Therefore, compared to the loop circuit configuration of FIG. 1 described above, the amount of hardware that is the circuit component of the loop circuit of FIG. 2 is smaller, and the same hardware as the loop circuit components of FIG. 1 is used. Since it is a loop circuit, the operation time of this loop circuit is shorter than that of the loop circuit of FIG. Note that the latch circuit 5 in FIG.
The circuit from 1 to the adder 16 via the predictor 15 also includes the predictor 15, which is a previous value predictor, but it is clear that the operation time of this circuit is less than that of the loop circuit. The DPCM encoder shown in FIG. 2 sets the predicted value of the predicted signal for two-dimensional prediction as described above, so the sampling frequency given to the A/D converter 1 is -:
Even at 10.7 MHz, which is higher than 9 MHz, the circuit operates stably and the intended purpose can be achieved.

Next, in the second embodiment of the present invention, the prediction signal of the two-dimensional prediction is determined by determining the predicted value from both the previous line and the line before the previous line in the same field, which is a plurality of lines. The DPCM encoder will be explained. That is, FIG. 3 is a block diagram showing the circuit configuration of this embodiment.
The input/output conditions of each hardware and signal relationship of the circuit components other than the predictor 17, delay circuit 18, and adder 19 in the figure are the same as in FIG. 2. In FIG. 3, the predictor 10 is related to the previous line, and the predictor 17 is related to the previous line, and the predicted value determining elements of these predicted signals are given to the adder 19, and the output of the adder 19 is added. The circuit operation is similar to that of the circuit configuration shown in FIG. 2 except that the signal is applied to the circuit 16. Therefore, even in this embodiment, the circuit operates stably even at a sampling frequency of 10.7 MHz, and furthermore, the DPCM shown in FIG.
The predicted value of the predicted signal can be set more accurately than in the case of an encoder. According to the present invention as explained above,
The time required for circuit operation related to the previous value predictor in the circuit configuration of a DPCM encoder that adopts two-dimensional prediction is the same as that of conventional DPCM.
Since the circuit configuration of the encoder is shortened compared to that of the encoder, the performance of the DPCM encoder that encodes the input color television video signal into PCM, performs bit conversion, and outputs the result is improved compared to the conventional DPCM encoder.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the circuit configuration of a conventional DPCM encoder, FIG. 2 is a block diagram showing a first embodiment of the present invention, and FIG. 3 is a block diagram showing a second embodiment. 1... A/D converter, 2... Subtractor,
3...Quantizer, 4...Bit converter, 5...Latch circuit, 6, 7, 16...
・Adder, 8, 10, 15... Predictor, 9...
...Delay circuit, 11...Video signal input terminal, 12...PCM signal output terminal, 13...
...Sampling signal input terminal, 14... Latch signal input terminal.

Claims (1)

[Claims] 1 DPC related to transmission band compression of color television signals, etc.
In the M encoder, a signal input/output path is formed by sequentially connecting an A/D converter, a subtracter, a quantizer, and a bit converter that receive a video signal and a sampling signal, and a signal input/output path that connects the output of the quantizer to the a first prior value predictor and a third adder received together with a bit converter; said first prior value predictor and a second prior value predictor;
a first adder receiving each output from the adder;
at least one two-dimensional predictor that receives the output of the adder; a delay circuit that receives the output of the two-dimensional predictor; and the second adder that receives the output after a certain delay time by the delay circuit; a latch circuit that receives the output of the first adder and a latch signal equivalent to the sampling signal; the subtracter that receives the output of the latch circuit; the third adder; and a second previous value predictor. A DPCM encoding circuit comprising: a second predictor, and a second adder receiving an output of the second predictor.