JPH04255113A - A/d converter - Google Patents

Abstract

PURPOSE:To obtain a stable data by adding a simple circuit to the A/D converter so as to prevent production of an error in an A/D conversion data due to noise. CONSTITUTION:A frequency of a clock pulse led from a clock pulse generating circuit 1 is multiplied by a frequency multiple circuit 3 as a multiple of an integral number and after an A/D converter 2 is in sampling operation by using a clock pulse whose frequency is increased, plural converted digital outputs are averaged by a signal averaging circuit 4 based on a clock pulse with the initial frequency an the averaged digital signal is outputted as an A/D conversion data.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to an analog/digital converter (hereinafter referred to as an A/D converter) for converting an analog signal such as an analog image signal into a digital signal in audio/visual equipment. More specifically, the present invention relates to an A/D converter that can obtain a stable digital signal by reducing the influence of noise irregularly added to an analog signal.

0002

[Prior Art] Typical prior art of A/D conversion devices used in video equipment such as televisions includes A/D converters.
A clock pulse generation means for deriving a clock pulse of a frequency corresponding to a sampling frequency for D conversion from an output terminal, an input terminal connected to an analog signal line, and a clock pulse input terminal connected to an output terminal of the clock pulse generation means. A typical example is a configuration that includes an A/D converter that samples the input clock pulse and converts it into a digital signal.

0003

[Problem to be Solved by the Invention] In such conventional examples, the noise mixed in the analog signal is directly introduced into the A/D conversion process. Since the analog part and the digital part coexist in the same circuit, noise is very likely to be added to the signal line, etc., and it is difficult to derive a high-quality digital signal that is not affected by noise.

[0004] From this point of view, measures have been taken such as making special arrangements for wiring on the board and adding LC filters, but these methods tend to complicate the equipment and increase equipment costs. There's a problem.

An object of the present invention is to overcome the problems of such conventional devices and obtain an output with extremely high stability against noise by simply adding a circuit with a simple configuration. An object of the present invention is to provide an A/D conversion device that can perform the following functions.

[0006]

SUMMARY OF THE INVENTION The present invention provides a clock circuit that derives a clock signal having a predetermined period, and a plurality of predetermined samplings within each period of the clock signal in response to the clock signal from the clock circuit. A multiplier circuit that derives the signal, an analog/digital conversion circuit that responds to the sampling signal from the multiplier circuit and converts the input analog signal into a digital signal in synchronization with the sampling signal, and a digital signal output from the analog/digital conversion circuit. responsive to a clock signal from a signal and clock circuit;
The present invention is an analog/digital conversion device characterized in that it includes an arithmetic circuit that calculates an average value of the plurality of digital signals within the predetermined period and derives a digital signal representing the calculation result. , a clock circuit that derives a clock signal having a predetermined period, and a plurality of analog/digital converters that respond to the clock signal from the clock circuit and convert commonly input analog signals into digital signals in synchronization with the clock signal. circuit, and in response to digital signals from the plurality of analog/digital conversion circuits and clock signals from the clock circuit, within the predetermined period, two
An analog/digital conversion device characterized in that it includes an arithmetic circuit that calculates an average value of two digital signals and derives a digital signal representing the calculation result.

The present invention further provides a clock circuit for deriving a clock signal having a predetermined period, a delay circuit for deriving a clock signal delayed by a predetermined time in response to a clock signal from the clock circuit, and a clock circuit. a first analog/digital conversion circuit that responds to a clock signal from the delay circuit and converts an input analog signal into a digital signal in synchronization with the clock signal; a second analog/digital conversion circuit that converts an analog signal commonly input to the circuit into a digital signal in synchronization with a clock signal from the delay circuit; and a digital signal and clock from the first and second analog/digital conversion circuits. in response to a clock signal from the circuit, within the predetermined period;
This is an analog/digital conversion device characterized by including an arithmetic circuit that calculates an average value of two digital signals and derives a digital signal representing the result of the calculation.

[0008]

[Operation] According to the present invention, A/D conversion is performed multiple times during one sampling period, which is a predetermined period for A/D conversion, such as during one pixel period of an analog image signal. A digital signal representing the average value is obtained. This reduces the relative magnitude of noise to the signal in one A/D conversion. Furthermore, by deriving the average of the digital signals in which the influence of these noises has been reduced, it is possible to prevent the digital signal from becoming unstable due to the influence of noise.

In the first aspect of the present invention, one A/D conversion circuit is activated a plurality of times within one predetermined period by a signal from a multiplier circuit, and then an average output is derived.

[0010] In claim 2, by operating a plurality of A/D conversion circuits in parallel, a plurality of A/D conversion circuits having some differences in inherent characteristics at the time of design, such as operation timing characteristics, can be used. These signals are taken out and the averaged output is derived.

[0011] In the third aspect of the present invention, the plurality of A/D conversion circuits are operated using a delay circuit so that a timing difference is generated in the conversion, and then an average output is derived.

As described above, the present invention calculates the average value of a plurality of digital signals by performing A/D conversion a plurality of times within a predetermined period in the A/D conversion process. This reduces noise-based errors in A/D conversion and enables more stable A/D conversion.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of an electric circuit according to an embodiment of the present invention.

The clock pulse generation circuit 1 derives from an output terminal a clock pulse P1 having a frequency corresponding to a sampling frequency for performing A/D conversion.

The analog signal SA is led out to the input terminal of the A/D converter 2 via an analog signal line 6. A/
The D converter 2 performs sampling to maintain the level of the analog signal SA introduced to the input terminal in accordance with the frequency of the clock pulse introduced to the clock pulse input terminal, and performs A/D conversion during the holding period. actuates and derives a digital signal from the output terminal.

Output terminal of clock pulse generation circuit 1 and A
The integer multiplier circuit 3 connected between the clock pulse input terminal of the /D converter 2 is formed as a double multiplier circuit in this embodiment, and the integer multiplier circuit 3 connected between the clock pulse input terminal of the /D converter 2 and the clock pulse P1 of the clock pulse generation circuit 1 introduced into the input terminal is By multiplying the frequency by twice, a clock pulse P2 having twice the frequency is derived as a sampling signal, and is applied to the clock pulse input terminal of the A/D converter 2.

The output terminal of the A/D converter 2 is connected to the input terminal of a signal averaging circuit 4, which is an arithmetic circuit.
/Digital signal S1 derived to the output terminal of the D converter 2
is averaged by the signal averaging circuit 4 and then outputted to the digital signal line 7 as a digital signal SD.

The signal averaging circuit 4 has a clock pulse input terminal, and this input terminal is connected to the output terminal of the clock pulse generation circuit 1, and the time difference between the signals introduced to the input terminals is calculated depending on the timing of the clock pulse P1 introduced. An operation is performed to obtain the average of the two digital signals S1 and S2, and a digital signal SD corresponding to this average value is derived from the output terminal.

FIG. 2 is a block diagram showing the configuration of the signal averaging circuit 4 shown in FIG. 1. This signal averaging circuit 4 consists of 4
The example is a bit. A first latch circuit 8 stores a digital signal that is introduced early in timing, an adder circuit 9 that adds the digital signal from this first latch circuit 8 and a digital signal that is introduced later in timing, and a clock pulse timing control circuit. and a second latch circuit 11 which is activated by a delayed clock pulse and derives a digital signal that is half of the digital signal derived from the adder circuit 9.

FIGS. 3A, 3B, and 3C are waveform diagrams for explaining the operation of the apparatus shown in FIG.

In FIG. 3(A), when noise is superimposed on the original analog signal shown by the two-dot chain line, it becomes like the solid line, and this synthesized analog signal SA is sent to the A/D converter. 2 is input.

When the A/D converter 2 performs sampling using the clock pulse of the doubler circuit 3, the digital output derived from the A/D converter 2 is as shown by the solid line in FIG. 3(b). On the other hand, the same digital output when sampling is performed using the clock pulse from the clock pulse generation circuit 1 without using the doubler circuit 3 is shown by a broken line in FIG. 3(b).

The digital signal SD obtained by averaging the former digital output sampled at twice the frequency by the signal averaging circuit 4 is as shown in the graph shown by the dashed-dotted line in FIG. The digital output of the latter is as shown in the graph indicated by the broken line, so when comparing the two, the former digital signal SD according to this embodiment is more similar to the original analog signal without noise. It is clearly shown that a signal is being formed.

FIG. 4 is a diagram showing the configuration of an electric circuit according to another embodiment of the present invention. This embodiment is similar to the previous embodiment, and corresponding parts are given the same reference numerals. The noteworthy configuration in this embodiment is the same type of A/D converter 2A,
The point is that two 2B units are used in parallel, and each A/D
In the converters 2A and 2B, each input terminal is connected to the analog signal line 6, and each clock pulse input terminal is connected to the output terminal of the clock pulse generation circuit 1, respectively.

On the other hand, the signal averaging circuit 4A has two systems of input terminals into which digital signals are input, and each of these input terminals is connected to each output terminal of the A/D converters 2A and 2B. .

FIG. 5 is a block diagram of the signal averaging circuit 4A in FIG. 4. This signal averaging circuit 4A is formed by an adder circuit and a latch circuit having the same configuration as the adder circuit 9 and second latch circuit 11 in FIG.

FIGS. 6A, 6B, and 6C are waveform diagrams for explaining the operation of the apparatus shown in FIG. 4. Figure 6 (
In b), the analog signal immediately before being digitally processed by the A/D converter 2A has noise superimposed on it, as shown in the curve shown by the dashed line, compared to the original analog signal shown by the two-dot chain line, and Similarly, the analog signal immediately before being digitally processed by the A/D converter 2B has noise superimposed thereon, as shown by the solid curve. In addition, both A/D
The difference in the input signals of converters 2A and 2B is that even if the converters are of the same type, there will be slight differences in the signal level and phase of the generated noise due to differences in the electrical characteristics of the internal circuit elements. It occurs from

As a result of sampling by the A/D converter 2A, the digital output S1 is as shown in the graph shown by the solid line in FIG. The digital signal SD obtained by averaging both digital outputs by the signal averaging circuit 4A is as shown in the graph shown by the dashed line in FIG. When compared with the digital output when digitally converted using the only A/D converter using the clock pulse of , which is shown by the broken line in FIG. 6(c) as a comparative example, the digital signal according to this example is It is clear that SD forms a signal that is more similar to the original analog signal without noise.

FIG. 7 is a block diagram showing an electrical configuration according to still another embodiment of the present invention. This embodiment is similar to the embodiment shown in FIG. 4, and corresponding parts are given the same reference numerals. What should be noted in this embodiment is that a time delay is added to the clock pulse introduced for sampling to one A/D converter 2A of the two A/D converters 2A and 2B. For this purpose, a delay circuit 5 is added, and the output terminal of the clock pulse generation circuit 1 and the A/D
A delay circuit 5 is connected between the clock pulse input terminal of the converter 2A, and the clock pulse P3 is introduced into the A/D converter 2A only for a predetermined extremely short time within the period of the clock pulse. It is P1 in A/D converter 2B
The system is designed to be introduced with a delay.

FIGS. 8A, 8B, and 8C are waveform diagrams for explaining the operation of the apparatus shown in FIG. Figure 8 (
In a), the analog signal SA shown by the solid line with noise superimposed on the original analog signal shown by the two-dot chain line is
As shown in FIG. 8(b), the digital output S2 of the graph shown by the broken line converted by the A/D converter 2B and the A/D converter 2A
The result is the digital output S3 shown in the graph shown by the solid line, and there is a difference in digital and timing between the two outputs.

The digital signal SD obtained by averaging both outputs by the signal averaging circuit 4A is as shown in the curve shown by the dashed line in FIG. When compared with the curve shown by the broken line, it becomes clear that the digital signal SD is more similar to the original analog signal.

FIG. 9 is a block diagram showing the configuration of a modification of the signal averaging circuit 4A according to the embodiment shown in FIG. 4 or 7. In FIG. Two types of digital outputs derived from both A/D converters 2A and 2B are processed by a well-known microcomputer consisting of a CPU 12, a RAM 13, and a ROM 14. The program written in the ROM 14 in this case is shown in a flowchart in FIG.

A/D converter 2A and A/D converter 2B
The digital outputs of are input to port 1 (15) and port 2 (16) in step m1 and step m2, respectively. This input value then moves to step m3 where an addition operation is performed, and then moves to step m4 where an average calculation of dividing by 2 is performed.

[0034] In the next step m5, this average value is output from port 3 (17) and led to digital signal line 7 as digital signal SD.

In all of the embodiments described above, two types of digital outputs are taken out and the average thereof is performed, but the present invention is not limited to two types, but also derives three or more types of digital outputs. A device for calculating the average may be used, and such modifications are naturally included in the present invention.

[0036]

As described above, according to the present invention, digital conversion of an analog signal is performed multiple times during one predetermined sampling period, such as during one pixel period of an analog image signal,
Since the average value is calculated and derived as a digital signal, it is possible to reduce the influence of noise as much as possible and extract stable data. Further, there is an advantage that the device configuration can be relatively easily configured by simply adding a circuit selected from A/D converters, integer multipliers, signal averaging circuits, etc.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit block diagram according to an embodiment of the present invention.

FIG. 2 is a block diagram of the signal averaging circuit in FIG. 1;

FIG. 3 is a waveform diagram for explaining the operation of the device shown in FIG. 1;

FIG. 4 is an electric circuit block diagram according to another embodiment of the present invention.

FIG. 5 is a block diagram of the signal averaging circuit in FIG. 4;

6 is a waveform diagram for explaining the operation of the device shown in FIG. 4. FIG.

FIG. 7 is an electric circuit block diagram according to still another embodiment of the present invention.

8 is a waveform diagram for explaining the operation of the device shown in FIG. 7. FIG.

9 is a block diagram showing a configuration of a modification of the signal averaging circuit according to the embodiment shown in FIG. 4 or 7; FIG.

FIG. 10 is a flowchart illustrating the operation of the signal averaging circuit of FIG. 9;

[Explanation of symbols]

1 Clock pulse generation circuit 2 A/D converter 3 Integer multiplier circuit 4 Signal averaging circuit 5 Delay circuit 6 Analog signal line

Claims (3)

[Claims] 1. A clock circuit that derives a clock signal having a predetermined period; a multiplier circuit that responds to the clock signal from the clock circuit and derives a plurality of predetermined sampling signals within each period of the clock signal; An analog/digital conversion circuit that responds to the sampling signal from the multiplier circuit and converts the input analog signal into a digital signal in synchronization with the sampling signal, and a digital signal from the analog/digital conversion circuit and a clock signal from the clock circuit. an arithmetic circuit that calculates an average value of the plurality of digital signals within the predetermined period in response to the above, and derives a digital signal representing the calculation result. 2. A clock circuit that derives a clock signal having a predetermined period, and a plurality of clock circuits that respond to the clock signal from the clock circuit and convert commonly input analog signals into digital signals in synchronization with the clock signal. In response to an analog/digital conversion circuit, a digital signal from the plurality of analog/digital conversion circuits, and a clock signal from the clock circuit, within the predetermined period,
An analog/digital conversion device comprising: an arithmetic circuit that calculates an average value of the plurality of digital signals and derives a digital signal representing the arithmetic result. 3. A clock circuit that derives a clock signal having a predetermined period, a delay circuit that responds to the clock signal from the clock circuit and derives a clock signal delayed by a predetermined time, and a clock signal from the clock circuit. a first analog/digital signal that responds to the signal and converts the input analog signal into a digital signal in synchronization with the clock signal;
a digital conversion circuit; and a second analog/digital conversion circuit that responds to the clock signal from the delay circuit and converts an analog signal input in common with the first analog/digital conversion circuit into a digital signal in synchronization with the clock signal from the delay circuit. The digital conversion circuit responds to the digital signals from the first and second analog/digital conversion circuits and the clock signal from the clock circuit, and calculates the average value of the two digital signals within the predetermined period. An analog/digital conversion device comprising: an arithmetic circuit that derives a digital signal representing a result.