JP3252298B2 - Sampling rate converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling rate converter used for digital audio and the like.

[0002]

2. Description of the Related Art Different sampling rates are used for digital signals used in digital audio and the like depending on the system. Therefore, in order to exchange data between different systems, it is necessary to convert the sampling rate. Such a device that converts the sampling rate while maintaining the identity of waveform signals such as audio signals is called a sampling rate converter.

[0003]

According to recent studies on hearing, it has been found that a sound is pleasantly felt by giving a so-called 1 / f fluctuation to a pitch.
However, such a point has not been taken into consideration in the conventional sampling rate converter.

An object of the present invention is to provide a sampling rate converter capable of improving sound quality auditoryly by 1 / f fluctuation.

[0005]

According to the present invention, a first signal at a first sampling rate is converted to a second signal at a second sampling rate.
A sampling rate converter for converting a signal into a signal, a sampling rate ratio calculating circuit for calculating a ratio between the first sampling rate and the second sampling rate, and an output data of the sampling rate ratio calculating circuit having a 1 / f characteristic spectrum distribution. An additional circuit for adding random signal data, a prediction circuit for predicting the output timing of the second signal based on output data from the additional circuit, and a prediction circuit for receiving the first signal and predicting the output timing of the second signal. An arithmetic circuit for calculating the value of the second signal at the predicted output timing of the second signal.

In the sampling rate converter, a comparison circuit is provided for comparing the predicted output timing of the second signal with the actual output timing of the second signal and generating predetermined correction data based on the error. The correction data may be further added in the additional circuit.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a sampling rate converter according to the present invention will be described below with reference to FIG.
For details of each component of the present embodiment, see 1 / f
Except for the fluctuations, most of the other components are described in Japanese Patent Application No. 5-1158 (filed on January 7, 1993) previously disclosed by the present applicant.

The sampling rate ratio calculating circuit 11 outputs data corresponding to the ratio between the input clock “Cin” and the output clock “Cou”, that is, data “corresponding to the ratio between the input sampling rate and the output sampling rate. a "is calculated. The 1 / f random signal generation circuit 12 generates random signal data “b” whose spectrum distribution has a 1 / f characteristic. Addition circuit 1
No. 3 adds random signal data "b" and correction data "c" to be described later to the data "a", and specifically performs addition and subtraction of these data. The prediction circuit 14 predicts the output timing of the output-side data “Dou” based on the data “d” from the addition circuit 13 and outputs predicted output timing data “e”.
The FIFO buffer 15 is for sequentially delaying the predicted output timing data “e” sequentially output from the prediction circuit 14. The comparison circuit 16 compares the predicted output timing data “f” sequentially output from the FIFO buffer 15 with the actual output timing data “g” of the output side data “Dou”, and corrects the correction data “g” based on the error between the two. c "is generated. The arithmetic circuit 17 receives the input data “Din” and the predicted output timing data “e”, performs an operation such as an interpolation operation, and calculates the value of the output data “Dou” at the predicted output timing of the output data “Dou”. Is calculated. The FIFO buffer 18 temporarily holds output data "h" sequentially output from the arithmetic circuit 17, and then sequentially outputs these data in synchronization with the predicted output timing.

Next, the operation of the embodiment shown in FIG. 1 will be described.

The sampling rate ratio calculating circuit 11 includes:
Input side clock “Cin” and output side clock “Cou”
Is input, and data “a” corresponding to the ratio between them (sampling rate ratio) is output. The data “a” corresponding to the sampling rate ratio is added by the adding circuit 13 to the random signal data “b” whose spectrum distribution has a 1 / f characteristic. Since the sampling rate ratio corresponds to the output timing of the output side data “Dou” (predicted output timing data “e”), the output timing has 1 / f fluctuation. Adder circuit 13
At the same time, the correction data "c" is subtracted. Prediction circuit 1
4, the output side data “Do” based on the addition data “d”
The output timing of “u” is predicted, and predicted output timing data “e” is output.

In the arithmetic circuit 17, the input side data "Din"
Then, an operation such as an interpolation operation is performed by inputting the predicted output timing data “e” and the value of the output data “Dou” at the time corresponding to the predicted output timing of the output data “Dou” is calculated. Normally, if the output-side data “Dou” can be calculated using the data “g” representing the actual output timing of the output-side data “Dou”, accurate output-side data “Dou” can be obtained. it can.
However, the actual output timing fluctuates due to the jitter of the clock signal (output timing signal) or the like, so that the exact output timing cannot be known until that time. That is, the value of the actual output timing data "g" is not known until the actual output timing signal is generated. Further, calculating the value of the output-side data “Dou” requires a calculation time. Therefore, it is essentially impossible to directly calculate the output side data "Dou" using the data "g" representing the actual output timing. Therefore, the calculation is performed using the predicted output timing data “e”. The predicted output timing data “h” sequentially output from the arithmetic circuit 17 is temporarily stored in the FIFO buffer 18 and then sequentially output in accordance with the predicted output timing.

On the other hand, predicted output timing data "e"
Are sequentially delayed by the FIFO buffer 15 and then compared with the actual output timing data “g” of the output side data “Dou” by the comparison circuit 16 to generate correction data “c” based on the error data. . This correction data "c"
It is input to the addition circuit 13 and increases or decreases the value of the addition data of the addition circuit 13. That is, negative feedback is applied to the predicted output timing data "e" by the correction data "c" to correct the error of the predicted output timing data "e" with respect to the actual output timing data "g", particularly the low frequency component of the error. This is because the magnitude of the error based on the random signal data “b” and the error due to the jitter of the input / output timing signal exceed the range allowed by the number of stages of the FIFO buffer, and the excess or deficiency of the output data occurs. This is to prevent it.

[0013]

According to the present invention, the sampling rate ratio is set to 1
By giving the / f fluctuation, it is possible to obtain a sampling rate converter capable of improving the sound quality aurally.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 11 Sampling rate ratio calculation circuit 13 Addition circuit (additional circuit) 14 Prediction circuit 16 Comparison circuit 17 Operation circuit Cin Input clock Cou Output clock Din Input data (First signal) Dou: output side data (second signal) b: random signal data c: correction data f: predicted output timing data g: actual output timing data

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-1753111 (JP, A) JP-A-4-329017 (JP, A) JP-A-3-38696 (JP, A) JP-A-2- 21712 (JP, A) JP-A-64-77327 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03H 17/00 621 G10L 21/04

Claims (2)

(57) [Claims] 1. A sampling rate converter for converting a first signal at a first sampling rate into a second signal at a second sampling rate, wherein a sampling rate ratio for calculating a ratio between the first sampling rate and the second sampling rate. A calculating circuit; an additional circuit for adding random signal data having a spectrum distribution of 1 / f characteristics to output data of the sampling rate ratio calculating circuit; output timing of the second signal based on output data from the additional circuit And a calculation circuit that receives the first signal and calculates the value of the second signal at the predicted output timing of the second signal predicted by the prediction circuit. 2. A sampling rate converter for converting a first signal at a first sampling rate to a second signal at a second sampling rate, wherein a sampling rate ratio for calculating a ratio between the first sampling rate and the second sampling rate. A calculating circuit, an additional circuit for adding random signal data whose spectrum distribution has a 1 / f characteristic and predetermined correction data to the output data of the sampling rate ratio calculating circuit, and the second circuit based on the output data from the additional circuit. A prediction circuit for predicting the output timing of the two signals; an arithmetic circuit for receiving the first signal and calculating a value of the second signal at a predicted output timing of the second signal predicted by the prediction circuit; The predicted output timing of the two signals is compared with the actual output timing of the second signal to determine the error. Sampling rate converter having a comparison circuit for generating the correction data based on.