JPH06216711A - Sampling rate converter - Google Patents

Abstract

PURPOSE:To improve an auditory tone quality by imparting the fluctuation of 1/f to a sampling rate ratio. CONSTITUTION:A sampling rate ratio calculating circuit 11 outputs data (a) corresponding to the ratio of an input side clock 'Cin' and an output side clock 'Cou', and an adding circuit 13 adds random signal data (b) whose spectral distribution becomes the 1/f characteristic and the data (a). Thus, the fluctuation of 1/f is imparted to an output timing. The adding circuit 13 substracts simultaneously correction data (c). A predictive circuit 14 predicts the output timing of output side data 'Dou', based on addition data (d), and obtains data (e). An arithmetic circuit 17 performs an operation to data 'Din' and (e), and calculates the data 'Dou' at the time point corresponding to a prediction output timing of the data 'Dou'. Data (h) outputted from the circuit 17 is outputted in accordance with the predictive output timing through a FIFO buffer 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling rate converter used for digital audio and the like.

[0002]

2. Description of the Related Art Digital signals used for digital audio or the like have different sampling rates depending on the system. Therefore, it is necessary to convert the sampling rate in order to exchange data between different methods. A device that converts a sampling rate while maintaining the identity of a waveform signal such as an audio signal is called a sampling rate converter.

[0003]

According to a recent research on hearing, it has been found that a feeling of audibility can be felt comfortably by giving a pitch a so-called 1 / f fluctuation.
However, the conventional sampling rate converter does not consider such a point.

An object of the present invention is to provide a sampling rate converter capable of auditorily improving sound quality by 1 / f fluctuation.

[0005]

SUMMARY OF THE INVENTION The present invention provides a first signal at a first sampling rate to a second signal at a second sampling rate.
In a sampling rate converter for converting into a signal, a sampling rate ratio calculation circuit for calculating a ratio between the first sampling rate and the second sampling rate, and a spectrum distribution of 1 / f characteristic in output data of the sampling rate ratio calculation circuit. And a prediction circuit for predicting the output timing of the second signal based on the output data from the addition circuit, and a prediction circuit for receiving the first signal and predicting the timing. And a calculation circuit that calculates the value of the second signal at the predicted output timing of the second signal.

In the sampling rate converter, a comparison circuit is provided which compares the predicted output timing of the second signal with the actual output timing of the second signal and generates predetermined correction data based on the error. The correction data may be further added in the addition circuit.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the sampling rate converter according to the present invention will be described below with reference to FIG.
For details of each component of this embodiment, refer to 1 / f
Except for the fluctuation-related matters, most of the others are described in Japanese Patent Application No. 5-1158 (filed on January 7, 1993) previously disclosed by the present applicant.

The sampling rate ratio calculation circuit 11 outputs data corresponding to the ratio of the input side clock "Cin" and the output side clock "Cou", that is, data corresponding to the ratio of the input side sampling rate and the output side sampling rate. a "is calculated. The 1 / f random signal generation circuit 12 is for generating random signal data “b” having a spectral distribution of 1 / f characteristic. Adder circuit 1
Reference numeral 3 is for adding random signal data "b" and correction data "c" described later to the data "a", and specifically, for adding and subtracting these data. The prediction circuit 14 predicts the output timing of the output side data “Dou” based on the data “d” from the addition circuit 13 and outputs the predicted output timing data “e”.
The FIFO buffer 15 is for sequentially delaying the prediction output timing data “e” output from the prediction circuit 14. The comparison circuit 16 compares the predicted output timing data “f” sequentially output from the FIFO buffer 15 with the actual output timing data “g” of the output side data “Dou”, and based on the error between them, the correction data “f”. c "is generated. The arithmetic circuit 17 inputs the input side data “Din” and the predicted output timing data “e” and performs calculations such as interpolation calculation and the value of the output side data “Dou” at the predicted output timing of the output side data “Dou”. Is calculated. The FIFO buffer 18 temporarily holds the output data “h” sequentially output from the arithmetic circuit 17, and then sequentially outputs these data at the predicted output timing.

Next, the operation of the embodiment shown in FIG. 1 will be described.

The sampling rate ratio calculation circuit 11 includes
Input clock "Cin" and output clock "Cou"
Is input, and data “a” corresponding to the ratio (sampling rate ratio) of both is output. The data “a” corresponding to this sampling rate ratio is added by the adder circuit 13 to the random signal data “b” whose spectrum distribution has a 1 / f characteristic. Since the sampling rate ratio corresponds to the output timing of the output side data "Dou" (predicted output timing data "e"), the output timing has a 1 / f fluctuation. Adder circuit 13
At the same time, the correction data “c” is subtracted at the same time. Prediction circuit 1
In 4, the output side data “Do” is added based on the addition data “d”.
The output timing of u "is predicted and the predicted output timing data" e "is output.

In the arithmetic circuit 17, the input side data "Din"
Then, the predicted output timing data “e” is input and calculation such as interpolation calculation is performed, and the value of the output side data “Dou” at the time corresponding to the predicted output timing of the output side data “Dou” is calculated. Originally, if the output side data “Dou” can be calculated using the data “g” representing the actual output timing of the output side data “Dou”, accurate output side data “Dou” can be obtained. it can.
However, the actual output timing fluctuates due to the jitter or the like of the clock signal (output timing signal), so the exact output timing cannot be known until that time. That is, the value of the actual output timing data "g" is unknown until the actual output timing signal is generated. Further, it takes a calculation time to calculate the value of the output side data “Dou”. Therefore, it is essentially impossible to directly use the data "g" representing the actual output timing to calculate the output side data "Dou". Therefore, the calculation is performed using the predicted output timing data "e". The predicted output timing data “h” sequentially output from the arithmetic circuit 17 is temporarily held in the FIFO buffer 18, and then sequentially output at the predicted output timing.

On the other hand, the predicted output timing data "e"
Is sequentially delayed by the FIFO buffer 15 and then compared with the actual output timing data "g" of the output side data "Dou" by the comparison circuit 16, and the correction data "c" is generated based on the error data. . This correction data “c” is
The value of the addition data input to the addition circuit 13 is increased or decreased. That is, negative feedback is applied to the predicted output timing data "e" by the correction data "c" to correct an error of the predicted output timing data "e" with respect to the actual output timing data "g", particularly a low frequency component of the error. This is because the size of the error due to the random signal data “b” and the error due to the jitter of the input / output timing signal exceeds the allowable range of the number of stages of the FIFO buffer, and the output data becomes insufficient. This is to prevent it.

[0013]

According to the present invention, the sampling rate ratio is 1
By providing the / f fluctuation, it becomes possible to obtain a sampling rate converter capable of auditorily improving the sound quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 11 ... Sampling rate ratio calculation circuit 13 ... Addition circuit (additional circuit) 14 ... Prediction circuit 16 ... Comparison circuit 17 ... Arithmetic circuit Cin ... Input side clock Cou ... Output side clock Din ... Input side data (First signal) Dou ... Output side data (second signal) b ... Random signal data c ... Correction data f ... Predicted output timing data g ... Actual output timing data

Claims (2)

[Claims] 1. A sampling rate converter for converting a first signal having a first sampling rate into a second signal having a second sampling rate, wherein a sampling rate ratio for calculating a ratio between the first sampling rate and the second sampling rate. A calculation circuit, an addition circuit for adding random signal data having a spectral distribution of 1 / f characteristic to the output data of the sampling rate ratio calculation circuit, and the output timing of the second signal based on the output data from the addition circuit. And a calculation circuit that receives the first signal and calculates the value of the second signal at the predicted output timing of the second signal predicted by the prediction circuit. 2. A sampling rate converter for converting a first signal having a first sampling rate into a second signal having a second sampling rate, wherein a sampling rate ratio for calculating a ratio between the first sampling rate and the second sampling rate. A calculation circuit; an addition circuit for adding random signal data having a spectral distribution of 1 / f characteristic and predetermined correction data to the output data of the sampling rate ratio calculation circuit; A prediction circuit that predicts the output timing of two signals; an arithmetic circuit that receives the first signal and calculates the value of the second signal at the predicted output timing of the second signal predicted by the prediction circuit; The predicted output timing of the two signals is compared with the actual output timing of the second signal, and the Sampling rate converter having a comparison circuit for generating the correction data based on.