JPS62264785A - Parallel processing circuit - Google Patents

Abstract

PURPOSE:To attain parallel processing by using m sets of delay elements to retard m phases in n phases of paralle input data thereby forming (n+m) phases of equivalent parallel input data equivalently. CONSTITUTION:The parallel processing circuit consists of delay elements 1001-100n giving a delay of one data length, delay elements 1011-101n giving a one-sample delay and forecast error signal generating circuits 1021-102n generating a forecast error signal. Parallel input data developing a time series input data string to n phases is inputted to the parallel processing circuit. The m sets of delay elements 1001-100m retard respectively m-phase parallel input data in the n-phase data by one data length respectively to output the m-phase retarded parallel input data. Further, the processing circuits 1021-102n process the (n+m)phase parallel input data comprising the n-phase parallel input data and the m-phase retarded parallel input data to generate the n-phase processing output.

Description

[Detailed Description of the Invention] [Summary] A parallel processing circuit that performs processing such as intraframe interpolation encoding of images, which delays m phases of n phases of parallel input data using m delay elements. By doing so, equivalent parallel input data of (n+m) phases is created and parallel processing is performed.

[Industrial application field]

The present invention relates to a parallel processing circuit for image signals, etc.

The parallel processing circuit of the present invention has a band of 20 M Ilz, for example.
It is possible to apply interpolation DPCM encoding of ultra-high-speed signals such as high-definition TV signals such as DPCM to a parallel processing circuit that can be relatively easily realized with a small-scale circuit consisting of low-speed arithmetic elements.

In image data transmission, the transmission path may not have the bandwidth necessary for data transmission.

As a means of sending data to be transmitted to a receiving side using such a transmission path, a means of compressing the data to within the bandwidth of the transmission path is adopted. One such means is, for example, an interpolation DPCM encoding method.

Even with this interpolation DPCM encoding method, as the signal to be encoded becomes faster, the circuit elements used for the interpolation DPCM encoding process are required to be faster.

Therefore, there is a need to develop means that can realize high-speed interpolation DPCM encoding of a signal to be encoded even though the circuit scale is relatively small and the elements used therein are of low-speed.

[Conventional technology]

As shown in FIG. 6, a typical image signal interpolation DPCM encoding method is based on the current value, a left value a2 and a right value a1 on the same scanning line, and an immediately above value a on the upper scanning line.
4, and directly below M a on the lower scanning line to generate a predicted value and perform differential encoding. Specifically, the average of each point a2 to a5 is taken to calculate the current value. value a
Find the predicted value for 1, and further combine this predicted value and the current value a.

The difference between the two is taken and encoded.

FIG. 7 is a block diagram showing an interpolation DPCM encoder for implementing the above method. In the figure, the encoder delays the input signal by (1 scanning line - 1 sample) and outputs the left value a3 and the value directly below a, respectively (1 line - 1 sample) delay elements 7 and 76, the input signal 1-sample delay elements 1 and 8 which output the current value a1 and right-side value a2 by delaying by one sample, an adder 4 which adds each piece a2 to a, and a predicted value by taking the average of each piece a2 to a. 174 multiplier 5 that performs calculations, a subtracter 3 that takes the difference (prediction error) between the predicted value and the current value, and a quantizer 6 that quantizes the prediction error from the subtracter 3.
It consists of:

According to the configuration shown in FIG. 7, when the sampling frequency is less than 20 MHz, the intended interpolation DPC can be achieved relatively easily using TTL or MOS devices.
M encoding can be realized.

However, when the input image signal becomes a high-definition TV signal with a bandwidth of about 20 MHz, the sampling frequency becomes at least 4
(More than 1 MIIz is required, and TTL or MOS devices cannot achieve the intended interpolation DPCM encoding from the viewpoint of operating speed.Also, even when using an ECL device, it is difficult to achieve the intended interpolation DPCM encoding from the viewpoint of operating speed.) is difficult.

Therefore, in Japanese Patent Application No. 198-198, the applicant proposed a parallel interpolation DPCM encoding circuit that can perform interpolation DPCM encoding of ultra-high-speed encoded signals using a small-scale circuit consisting of low-speed elements. Disclosed.

FIG. 4 is a block diagram showing such a parallel interpolation DPCM encoding circuit. This encoding circuit performs interpolation encoding using four pixels on the upper, lower, left and right sides by four-phase expansion. In other words, as shown in FIG.
PI, Nl to N,), and interpolation D P' CM encoding is performed in parallel for each phase. Its configuration consists of delay elements 71 to 7 that delay the input data of each phase, for example N1 to N4, by (1 scanning line - 1 sample) and output the right side value a2 in each phase (1 line - 1 sample).
4. One-sample delay element 11 that delays the input data in each phase by one sample and outputs the current value a, respectively.
-14, 1-sample delay elements 81 to 84 that delay the input data in each phase by 1 sample and output the left side value a3, and the output of the 4th phase 1-sample delay element 84 (1 scanning line - 1 sample) A delay element 75 that outputs the immediate value a4 for the first phase with a delay of 1 line (1 line - 1 sample), adders 41 to 44 that add each value a2 to a5 in each phase, and each value a2 to a in each phase. 1/4 multipliers 51 to 54 that calculate the predicted value by taking the average, subtractors 34 to 34 that take the difference (prediction error) between the predicted value and the current value in each phase, and subtractors 34 to 34 in each phase. It consists of quantizers 61 to 64 that quantize prediction errors.

According to this configuration, the parallel input data P of the current cycle,
~P4 is (l line - l sample) delay elements 71 to 74
Parallel input data N1 to N4 of the next cycle appear on the output side of the delay element 75, and input data L4 among the parallel input data of the previous cycle appears at the output of the delay element 75 (l line - l sample).

Therefore, the value a4 immediately above the current value a1 of the input data P1 is obtained from the output of the delay element 75 (1 line - 1 sample), and is the current value a of the input data P4.

The immediate value a for (1 line - 1 sample) is obtained from the input data N at the input end of the delay element 71, which enables interpolation D P CM encoding in each phase.

[Problem that the invention seeks to solve]

However, an encoding circuit having such a configuration requires many large-scale line memories as delay elements (1 line - 1 sample), leading to an increase in the size and cost of the device.

[Means for solving problems]

FIG. 1 is a principle diagram of a parallel processing circuit according to the present invention.

In the figure, 100+" 100m is a delay element that provides a delay of l data length, 101. and 101z are delay elements that provide a delay of l samples, and 102. to 102n are prediction error signal generation circuits that generate a prediction error signal. This is a processing circuit such as

This parallel processing circuit receives n time series input data sequences (n is 2
Parallel input data expanded into phases (an integer greater than or equal to) is input. m delay elements 100. ~100n outputs delayed parallel input data of m phases by delaying parallel input data of m (m is an integer greater than or equal to 2 and less than or equal to n) phase by one data length among n phases. Further, the processing circuits 1021 to 102n are
An n-phase processing output is generated using (n+m)-phase parallel input data consisting of n-phase parallel input data and m-phase delayed parallel input data.

[For production]

In addition to the parallel input data expanded into n phases, m delay elements 100. Using m-phase delayed parallel input data obtained from ~100n, equivalently create (n+m)-phase parallel input data. Then, using this (n+m) phase parallel input data, the delay elements 101 to 10h and the processing circuit 102. ~10
2n generates n-phase parallel output data such as a prediction error signal.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing a parallel processing circuit as an embodiment of the present invention. In the figure, 10 to 15. 80 to 83 are each one sample time delay element, 20 and 21 are each one scanning line delay element, 30 to 33 are each subtractors, 40 to 43 are each adders, 50 to 53 is 1/
4 multipliers, 60 to 63 are quantizers.

P1 to P are parallel input signals developed into four phases, respectively, and these parallel input signals P1 to P are connected to the delay elements 11 to
14, and the parallel input signals P3 and P- are respectively guided to delay elements 15 and IO via delay elements 20 and 21.

As a result, the output side of the delay element 20.21 receives parallel input signals 1. :+ and L- appear. As a result, Ll, L4,
P+ to P4 are equivalent to six-phase parallel input signals.

A parallel input signal L is connected to the input side of the delay elements 15.10 to 14.
3, L, a, the right side value a2 of PI~P4 appears, the current value a1 appears on the output side, and the parallel input signals L4, P1~
By further passing the current value a of P4 through delay elements 80 to 83, the left value a3 appears on the output side.

Adders 40 to 43 are circuits that add respective values a2 to as in the vicinity of the current value a1 of the fourth phase of the previous cycle and the current value a1 of each of the first to third phases of the current cycle, Each output signal of the addition 2S40 to 43 is sent to the 1/4 multiplier 5.
The predicted value (average value) is calculated by dividing the value into 1/4 by 0 to 53. '$i calculators 30 to 33 calculate the difference (prediction error) between this predicted value and the current value of each phase and send it to quantizers 60 to 6.
This is a circuit that outputs to 3.

The operation of the circuit of FIG. 2 will be explained below with reference to FIG.

FIG. 3 is a diagram showing parallel input signals expanded into four phases, where L1 to L4 are the parallel input signals of the previous cycle, P+-Pa
is the parallel input signal of the current cycle, and N, -N are the parallel input signals of the next cycle.

In this circuit, the immediate value a4 for calculating the predicted value of the current value a of the parallel input signal P+ is transferred to the delay elements 20 and 10.
The calculation is performed using the parallel input signal L4 corresponding to the fourth phase of the previous cycle obtained through the process.

The predicted value of the current value a of the parallel input signal L3 is similarly calculated using the parallel input signal L3 corresponding to the third phase of the previous cycle obtained through the delay elements 21 and 15. Note that the predicted values of the parallel input signals Pz and P3 of other phases are calculated using respective neighboring phases.

A parallel prediction error signal E is obtained as an output signal after obtaining a predicted value as described above and performing four-phase parallel interpolation encoding.

〜E3.

Various modifications are possible in carrying out the invention. For example, in the above-mentioned embodiment, an image signal expanded into four phases was explained, but other signals expanded into multiple phases may be used. Furthermore, the present invention can be applied to systems other than interpolation coding as described in the embodiments, and can be applied to a device that performs processing using information spanning multiple lines in a frame in parallel.
Can be used for dimensional filters, etc.

〔Effect of the invention〕

According to the present invention, an ultra-high-speed coded signal such as a high-definition image signal can be processed by [)PCM or the like using a small-scale circuit made up of low-speed elements. Furthermore, the device of the present invention does not require a large number of line memories, and the device can be made even smaller and less expensive.

[Brief explanation of drawings]

[Figure] is a principle diagram of the present invention, Figure 2 is a block diagram of a parallel processing circuit as an embodiment of the present invention, and Figure 3 is a diagram for explaining the operation of the circuit shown in Figure 2, which is developed in four phases. Figure 4 is a diagram showing parallel input signals obtained using parallel interpolation D as a related technique.
A block diagram showing the PCM encoding circuit, FIG. 5 is a diagram for explaining the operation of the circuit in FIG. 4, FIG. 6 is an explanatory diagram of the interpolation DPCM encoding method, and FIG. FIG. lO~15.80~84--1 sample time delay element 20.21--l scanning line delay element 30-34-subtractor 40-44-adder 50-1/4 multiplier 60-64-- Quantizer (n, m) phase equivalent parallel input data Diagram showing the principle of non-invention Figure 1 Parallel processing type differential encoder according to the embodiment of the present invention Figure 2 Figure 2 Diagram explaining the operation of the circuit Cap qF' fl Figure 4 Diagram explaining the operation of the circuit

Claims (1)

[Claims] Parallel input data (P_1 to P_4) obtained by expanding a time-series input data string into n phases (n is an integer of 2 or more) are input, and m of the n phases (m is 2 or more, m delay elements (101
_1 to 101_m) and (n+m) consisting of the n-phase parallel input data and the m-phase delayed parallel input data
)-phase parallel input data is used to generate the n-phase processing output (E_
n processing circuits (102_1 to 10
2_n), a parallel processing circuit comprising: