JPH03250995A - Dpcm coder for picture signal - Google Patents

Abstract

PURPOSE:To eliminate the restriction of a sampling period of an inputted moving picture signal by dividing longitudinal one pattern of the input moving picture signal into N, allocating the coding processing of the split pattern to N sets of signal processing units and applying parallel processing to the split patterns. CONSTITUTION:A speed conversion circuit 101 splits each line of a picture signal 132 being an input video signal into four partial line picture signals 142, 144, 146, 148 and each of them is subjected to time expansion up to one line period of the input video signal thereby converting the signal speed into 1/4 of the input video signal. One of the four partial line picture signals subjected to speed conversion is outputted as it is to a signal processing unit 102, and the other three signals are outputted to signal processing units 103, 104, 105 via delay circuits 107, 108, 109 respectively. The signal processing units 103, 104, 105 execute DPCM coding processing of the partial line picture signals at a rate of 1/4 of the original signals and the obtained four coding series signals 171, 172, 173, 174 are multiplexed by a multiplexer 106 and outputted from an output terminal 123.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image signal DPCM encoding device that performs intra-frame DPCM encoding of an image signal using a plurality of signal processing devices.

(Prior art) Intra-frame DPCM encoding processing of image signals is an encoding method that performs band compression of signals by utilizing spatial correlation of image signals, and includes generation processing of predicted signals and input image signal processing. This consists of quantizing the prediction error signal, which is the difference between the prediction signal and the prediction signal. For prediction signal generation processing and prediction error signal quantization processing, see "Image Digital Signal Processing", for example.
(Fukunuki, Nikkan Kogyo Sha Series, 1981) explains various methods in Chapter 9. According to the explanation in the same document, in order to avoid accumulation of quantization errors in the encoding loop,
The prediction signal is generally generated using a decoded signal. That is, the encoding process has already been completed, and a predicted signal is calculated using the value obtained by decoding. At this time, adjacent pixel values with a high correlation are used, but in most cases, the pixel located to the left on the screen, or the pixel directly above, in the upper right, or in contact with the upper left is used.

Several DPCM encoding devices that perform DPCM encoding on image signals have been put into practical use. These DPCM encoding devices use a single encoder to encode one pixel at a time in the scanning order of input image signals, and are similar to parallel processing based on screen division applied in other image signal processing. No implementation has taken place. This is because in DPCM encoding, as mentioned above, the decoding results of the surrounding area are required to generate the predicted signal, so even if multiple encoders are used, the waiting time in the encoders becomes long and the efficiency is reduced. This is a lick that was thought not to improve.

(Problem to be Solved by the Invention) When applying the conventional DPCM encoding processing method to a moving image signal, it is essential to finish the encoding processing of one pixel within the sampling period of the input image signal. . Normally, the sampling cycle of an image signal is about 10 MHz, so it is difficult to implement an encoder using a microprocessor or the like, and a specially designed signal processing circuit is required. However,
For high-definition images, the sampling period becomes even shorter, for example, 50 to 80 MHz for HDTV signals. In this case, TTLR? Since implementation of an encoder using a circuit using CMO3 is approaching its limit, restrictions on circuit implementation of a DPCM encoding device for high-definition image signals are increasing. As a result, the encoding algorithms that can be adopted are also subject to restrictions, and a problem arises in that it is not possible to sufficiently measure the improvement in encoding efficiency.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a DPCM encoding device that removes restrictions on the sampling period of an input moving image signal by introducing a parallel processing method with no actual efficiency.

(Means for Solving the Problems) The DPCM encoding device for an image signal of the present invention has N (N is an integer of 2 or more) partial image signals (hereinafter each partial image First, the signal is divided into partial image signals (=1..., N), and the signal speed of each partial image signal is time-expanded to 1/N times the speed of the image signal, and the signal is divided into partial image signals. A speed converting means for outputting N partial image signals, and N partial image signals outputted from the speed converting means are input, and for a first partial image signal for which the value of k is 2 or more, the image signal is A delay means for outputting the N partial image signals by applying a delay of (k-1> line period), and inputting the N partial image signals output from the delay means, respectively, and outputting the partial image signals. N signal processing means that perform predictive coding processing in rask scan order and output DPCM coded sequence signals, and N DPCM output from the N signal processing means.
a multiplexing means for multiplexing and outputting a CM encoded sequence signal; a signal processing means for firstly handling a partial image signal;
1 and a signal processing means in charge of the +1 partial signal, respectively.

(Function) Description of the parallel processing method for image signals according to the present invention In the present invention, one screen of an input moving image signal is divided into N pieces in the width direction, and the encoding process of the divided screens is performed by N signal processing. Allocate to devices and process in parallel. Screen division is obtained by dividing one line of the input image signal into N partial sections. Divide every line period, and each signal processing device! Then, by repeating the encoding process on one line of each divided partial image signal, real-time encoding process becomes possible. At this time, 1
It is possible to take a time corresponding to the sampling period N times the original signal per pixel.

FIG. 4 shows the allocation of signal processing devices (PE1: i=1...N) and the processing method within the signal processing device PE.

Each partial image signal divided in the vertical direction is sequentially processed from the left end to the signal processing device PE1. It is assigned as PE2. Within each signal processing device, encoding processing proceeds from the left pixel to the right in rask scanning order.

Pixel value X11. Predicted value for X1. , is the decoded signal (
The weighting obtained by multiplying y, , , ) by the number of weight threads α, β, γ1η is calculated as a sum using equation (1).

xIIv: αylI-1. w+βy,,v−+γ
y・1 ・−1+ η y・−1・−ku −<
1>Prediction error signal e5. and decoded signal y, 2. The relationship with <2> is expressed by equation (3).

e u, w ”X-view, -X*, w ”'
(2)y,,-=Q (e,,,)+x,,,-
(3) Here, Q(·) is the prediction error signal e11. This is a function that gives a value obtained by applying quantization/inverse quantization to . When encoding by the division process shown in FIG. 4, the necessary decoded signal 't t-1
, v l 3'11. v-113'm+1. v-1
Among 1ym-1 and v-1, 'I* and w-+ are located directly above the pixel to be encoded, so they are always calculated by the same signal processing device P E I in vertical division processing. Therefore, the decoded signal can be used by providing a shift register for one line in the signal processing device and storing the decoded signal. However, Xl
, is the leftmost pixel, then y, -13'm-1. v-
1 is the decoded signal obtained by the signal processing device PE1-+ on the left. Also, when Xl is the rightmost pixel, 'J
u+1. w-1 is required, and this result is the value obtained by the right signal processing device PE++1. Therefore, each signal processing device needs to proceed with processing while communicating the decoded signal (y, . . .) with the signal processing device in charge of the adjacent area.

In the present invention, in order to efficiently communicate subsequent signals between each signal processing device, the signal processing device P E + in charge of the left partial screen starts the signal processing device P E +.
Delay by one line period from −+.

For this reason, the signal processing device PE selects the leftmost pixel
2. Predicted signal for Ma11. 3'w- required for calculation of
1,v has been calculated by P E ,-, and the already calculated value can be used. Also, for 3'*-+, v-1, it is sufficient to store the value already transferred as 3'*-1, v one line cycle ago in the line memory in the PE, so there is no need to transfer it again. There isn't. Therefore, P E 1 is P
There is no need to wait for the processing of R,-, to finish.

On the other hand, when the signal processing device P E t encodes the rightmost pixel, V Il+1. w−+ must be transferred. Since the signal processing device f P E l++ in charge of the right side partial screen is activated one line period later than PE, ya+1. v-1 is PE
This results in fewer calculations within the same line period as encoding x, , with l. However, since processing proceeds in the order of rask scanning within each signal processing device, encoding ends at the beginning of one line period for P E , while P E
, processes the rightmost pixel at the end of one line period. Therefore, even in the rightmost processing, the signal processing device [PE
, no longer need to wait for PEs, , , to complete their processing.

As described above, in the parallel processing based on the vertical division of the screen adopted in the present invention, the N signal processing devices have the function of communicating decoded signals with the signal processing devices in charge of adjacent areas. By providing this, DPCM encoding processing can be continued without spending waiting time between signal processing devices.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a DPCM encoding device according to the present invention. In this embodiment, the number N of signal processing devices is set to 4 for the sake of simplicity and without loss of generality. In this figure, 101 is a speed conversion circuit that converts an image signal of an input video signal into four low-speed partial line image signals, and 102, 103, 104, and 105 are signal processing devices. 106 is a multiplexer, 107
108 and 109 are delay circuits.

The speed conversion circuit 101 receives a horizontal synchronizing signal 131 and an image signal 132 of the input video signal through terminals 121 and 122.
is input. By inputting "1" to the terminal 121, the start of one line of the input video signal is notified. The speed conversion circuit 101, as will be explained in detail later,
Image signal 132 of the input video signal input to the terminal 121
Each line is converted into four partial line image signals 142, 144
146.148, and time-expanding each partial line image signal to one line period of the input video signal.
Converts the signal speed to 1/4 of the input video signal. Also,
The horizontal synchronizing signal 131#J input to the terminal 122 is delayed according to the split screen position and output. One of the four partial line image signals whose speed has been converted in this manner is output to the signal processing device 102 as is. The other three are
After being delayed by delay circuits 107, 108, and 109, the signals are output to signal processing devices 103, 104, and 105, respectively. The delay circuit 107 provides a delay of one line period, and the delay circuits 108 and 109 provide a delay of two and three line periods, respectively. Signal processing devices 102, 103,
104 and 105 have the same configuration, and perform DPCM encoding processing on a partial area signal, that is, a partial line image signal, at a rate of 1/4 of the original signal, as will be explained in detail later. Outputs a sequence signal. The signal processing devices 102, 103, 104, 105 include a speed conversion circuit 1.
By setting 01, split screens are allocated in order from the top left to the right edge of the screen. A data transfer path is provided between adjacent signal processing devices to transfer locally decoded signals obtained by DPCM encoding processing. However, the decoded signal value outside the screen is considered to be "O", and "0" is always supplied to the transfer path to the signal processing device 102 in charge of the left edge of the screen and the signal processing device 105 in charge of the right edge. . Four coded sequence signals 171, 172 173.17 obtained from signal processing devices 102, 103, 104, 105
4 is multiplexed by the multiplexer 106 and sent out to the transmission line via the output terminal 123.

FIG. 2 is a block diagram showing the configuration of the speed conversion circuit 101. Horizontal synchronization signal 1 of input video signal from terminal 121
31 is supplied. 201, 202, 203, and 204 are time expansion circuits. In Figure 2, time dilation diagram #120
Although only the circuit configuration of 1 is depicted in detail, time expansion circuits 202, 203, 204 have the same configuration as 201. That is, each of the time expansion circuits 201, 202, 203, and 204 includes a line memory 211, a delay device 212, and a counter 213.

The line memory 211 is, for example, μPD421 manufactured by NEC.
FIFO configured using line buffers like 02
Memory can be written and read asynchronously. When "1" is applied to WEN of the line memory, the image signal 132 applied to DIN, for example, 8-bit data, is written in synchronization with the clock of the horizontal synchronizing signal 131 of the input video signal. At this time, an internal write address counter is incremented at the same time as writing. This write address counter is reset when 1 is given to R3TW.

Conversely, for reading, when "1" is applied to R3TR, the internal read address counter is reset. R
When EN is “1°, horizontal synchronization signal 1 of input video signal
It is read out in synchronization with a read clock at a speed of 1/4 of T.31. At this time, an internal read address counter is incremented at the same time as reading.

The delay device 212 delays the horizontal synchronizing signal 131 supplied to the terminal 121 by a predetermined number of clocks, and outputs it to R3TW, R8TR of the line memory 211 and the counter 21.
Output to 3. The counter 213 is reset by the horizontal synchronization signal delayed by the delay device 212, and counts the number of tallocks of the horizontal synchronization signal of the input video signal up to a predetermined value. Then, the counter 213 sets "1" to WEN in the line memory 211 while the counted value is less than the set value.
continues to be output, and when it exceeds the set value, outputs "0".

Therefore, the number of partial line image signals set in the counter 213 is written into the line memory 211, starting from a pixel delayed by the set value of the delay path 212 from the beginning of each line of the image signal 132 of the input video signal. On the other hand, since the read clock has a period four times that of the input, REN of the line memory 211 is always set to 0 or more, which always gives "1", and from each line signal of the image signal 132 of the input video signal, the delay circuit The partial line image signal determined by the settings of 212 and counter 213 is converted to a speed 1/4 of the input video signal and is supplied to each signal processing device.

FIG. 5 shows the setting values of the delay device 212 and the counter 213, and the time-expanded signal 102103 104 for each signal processing device.
105 is a diagram illustrating the relationship between signals supplied to 105. FIG. Here, let L be the number of pixels included in one line of the split screen. At this time, time expansion circuits 201, 202, 203, 204
O, L, 2L, and 31- are respectively set in the delay devices 212 in the image signal 132, and O, L, 2L, and 31- are set respectively from the rising edge of the horizontal synchronizing signal 131 among one line data of the image signal 132.
Loading into the line memory 211 starts at a time delayed by L. Furthermore, all the counters 213 are set to L, and the loading into the line memory 211 is started. Furthermore, L is set in each counter 213, which corresponds to the number of pixels written in the line memory 211. With these settings, the first line of the image signal 132 of the input video signal is divided into four partial line image signals a(k) as shown in FIG.
142, b (k) 144. c (k) 148, stored in the line memory 211 in each time expansion circuit 1201, 202, 203° 204, and read out after being time expanded four times. Further, the horizontal synchronizing signal 131 is output after being delayed by the set value of the delay device 212, and the horizontal synchronizing signal 141, 14 indicates the start of one line of each partial screen signal.
3. Each signal processing device 102, 103 as 145147
, 104.105.

FIG. 3 is a block diagram showing the four fI@ configuration of the signal processing device 103. Here, the signal processing device 103 will be explained as an example. 321 and 322 are terminals to which the horizontal synchronization signal 143 and the partial line image signal 144 are respectively input. 301 is a timing control circuit, 302 is a quantizer, 3
03 is an inverse quantizer. 3o4 is an L+1 stage shift register that outputs three values: L-1, L, and L+1 delay.

305 is a predictor which inputs the decoded signal (ym, -) and performs calculations corresponding to equation (1) of the action term. 306 is a data transfer register that transfers the decoded signal to the adjacent signal processing device 102, and its value is supplied to the signal processing device 102 via the terminal 325. 307 is a data transfer register that transfers the decoded signal to the adjacent signal processing device 104, and its value is transferred to the signal processing device 10 via the terminal 327.
4. 308 is a subtracter, 309 is an adder, 3
10 is a pipeline register, and 311 and 312 are two-manufactured selectors with one output.

Speed conversion port F! The partial line image signal 144 supplied from @101 to the terminal 322 of the signal processing device 103 via the delay circuit 107 is subtracted by a subtracter 308 to calculate the difference between it and the prediction signal output from the predictor 305, and generates a prediction error signal. obtain. The prediction error signal is quantized by quantizer 302 and then output to multiplexer 106 via terminal 323.

The quantized signal is simultaneously subjected to inverse quantization in an inverse quantizer 303, and then added to the predicted signal, which is the output of the predictor 305, in an adder 309 to obtain a locally decoded signal. The locally decoded color data is stored in the pipeline register 310 every operation cycle of the signal processing device, and is used to generate the next predicted signal. The timing control circuit 301 switches the selector 311 based on the position of the pixel to be encoded based on the horizontal synchronization signal 143 input from the terminal 321, and the horizontal synchronization signal 143 is input from the signal processing device 102 to the terminal 324. or the value of the pipeline register 310 is supplied to the predictor 305 and the shift register 304. The shift register 304 has a storage capacity for one line,
A decoded signal corresponding to the action term (1) is given to the predictor 305. However, the selector 312 is switched by the timing control unit 301, and the terminal 32 is switched from the signal processing device 104.
6 or a value delayed by L+1 in the shift register 304 is selected. The timing control port 8301 also controls the data transfer register 306.30.
7 data update is controlled. Although the configuration and operation of the signal processing device 103 have been explained above, the signal processing device 103
2, 104, and 105 have similar configurations and operations.

FIG. 6 is a timing chart mainly showing the operation of the signal processing device 103. Here, the number of pixels in one line is 32, so each partial line image signal has 142, 144,
The number of pixels of 146 and 148 is 8. In the figure, Xl,
, is the value of the image signal 132 of the V-th pixel of the U-th line,
yl, is X5. , shows the locally decoded signal for . The signal processing device 103 generates a partial line image signal 144 which is the second partial screen signal from the left, that is,
9. v to X16. In charge of Further, the signal processing device 102 calculates X a , v from the leftmost X (, w, and the signal processing device 104 calculates
21. In charge of Although FIG. 6 shows only the horizontal synchronizing signal 143 input to the terminal 321 of the signal processing device 103, other signal processing devices such as the one shown in FIG.
Each operates in synchronization with a different horizontal synchronization signal. Also,
Each partial line image signal is sent to a delay circuit 107, 108, respectively.
．． 109, each line is supplied with a different delay.

Therefore, in the illustrated line, the signal processing device W10
In 2, the data of the line is inputted, and from Xs, m to
s, whereas the signal processing device 10
3 is the data of the 11th line, Xs, from -+ to X
In the order of r+, -+, the signal processing device 104 first processes the data of the 12th line from X 9 to -x to X 16. k-
Each process is performed in the order of 2.

The timing control circuit 301 of the signal processing device W103 outputs two control signals 341342 shown as a and b in FIG. The control signal 341 is a control signal that matches the processing timing of the left end of the assigned area, and is sent to the selector 311 to
The input to the period terminal 324 for processing g and v is selected. As a result, 3'e and v already obtained by the signal processing device 102 are transferred to the shift register 304 and the predictor 30.
5. Further, the data transfer register 306 is updated at the rising edge of the control signal 341 and
The locally decoded signals yg and w obtained as the output of the adder 309 as a result of processing g and v are stored. The value of the data transfer register 306 is later changed to the signal X by the signal processing device 102.
It is used when calculating a, v++. On the other hand, the control signal 342 is a control signal that matches the processing timing of the right end of the assigned area, and causes the selector 312 to select input to the terminal 326 only during the processing period of XI and V. With this, the signal processing device! 3'+ already obtained in fl 04
6.1-1 is provided to the predictor 305. Furthermore, the data transfer register 307 is updated at the rising edge of the control signal 342, and the right end xr6. The locally decoded signal V+i obtained as the output of the adder 309 as a result of processing w
, v are stored. The value of the data transfer register 307 is later transferred to the signal processing device 104 or the signal X17. It is used when calculating V, and in the signal processing device 104, it is stored in the shift register 304 and used to calculate X17.11+1.

FIG. 7 is a block diagram showing a second embodiment of the DPCM encoding device according to the present invention. In this embodiment as well, the number N of signal processing devices is 4, and the operation period of the signal processing device is four times the sampling period of the input video signal. In this figure, 702, 703, 704, and 705 are signal processing devices. Speed conversion circuit 101, delay circuits 107, 108, 1
09, the multiplexer 106 is the same as in the first implementation shown in FIG. The difference from the first embodiment is that the signal processing devices are connected by one common bus 710.

＆′! FIG. 8 is a block diagram showing the structure of the signal processing device 703. The difference from the signal processing device 103 shown in FIG.
5,326,327 components. That is, a signal is supplied from the common bus 710 to the selector 311312 via the terminal 811 instead of the terminals 324 and 325 in FIG.

In addition, the outputs of the data transfer registers 306 and 307 are
It is connected to a common bus 710 via buffers 802 and 803. For this purpose, data transfer registers 306, 3
A timing control circuit 801 for controlling the output timing of 07 is added.

FIG. 9 is a diagram showing a timing chart of each signal in the signal processing device 703 of the second embodiment. here,
The selector 311312 of each signal processing device is connected to the common bus 71
The common bus 710 is used in a time-division manner by taking advantage of the fact that the timing of obtaining signals through 0 is different. Here, since the transmission rate of the common bus 710 is 8 per line period, one line period is time-division multiplexed into 8 slots to achieve the same bus rate as the operating period of the signal processing device. In general, in the calculation of equation (1) where the predicted signal is the action term, for the number N of signal processing devices, 2
It is sufficient to transfer data of N pixels between signal processing devices. By the control signal 821 of the timing control circuit 801, the value y9. of the data transfer register 306 is changed. ．． is the signal processing device 7
02, the control signal 58 of the timing control circuit 801 is outputted at the timing used for calculating Xa, v++.
22, the value '11b of the data transfer register 307
, w is the signal processing device 704 and X17. It is output at the timing used to calculate v. As a result, the signal processing device shown in the bottom row of FIG. 9! 702.

Transfer between 703.704.705 is realized.

(Effects of the Invention) As described in detail above, according to the present invention, the DPC can perform DPCM encoding processing even on high-speed image signals without being restricted by the sampling frequency of input moving image signals.
An M encoding device can be provided.

Furthermore, the DPCM encoding device of the present invention can set the operating cycle of each signal processing device depending on the number of signal processing devices used. Furthermore, since the DPCM encoding process for image input and output proceeds in parallel within one line period, the amount of human output buffer can be minimized, and the overall processing delay is small. Further, in communication between signal processing devices, it is sufficient to transfer only pixels in a boundary area within one line period, so the required transfer capacity is small.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the DPCM encoding device according to the present invention, and FIG. 2 is a block diagram showing a speed conversion port F#1101.
FIG. 3 is a block diagram showing the configuration of the signal processing device 103.
Figure 4 is a block diagram showing the circuit configuration of the circuit, Figure 4 is a diagram showing the assignment of image signals to each signal processing device, Figure 5 is the speed conversion port #1.
Figure 6 showing the time chart of each signal in 101
The figure shows a time chart of each signal in the signal processing device 103, FIG. 7 is a block diagram showing a second embodiment of the DPCM encoding device according to the invention, and FIG. 8 shows the circuit configuration of the signal processing device 703. FIG. 9 is a block diagram showing a time chart of each signal in the signal processing device 703. 101... Speed conversion circuit, 102, 103.104.
105,702,703,704,705 Signal processing numerals, 106...Multiplexer, 107°108.10
9...Delay circuit, 201, 202, 203.204.
・・Time expansion circuit, 211 ・・Line memory, 212
...Delay device, 213...Counter, 301801...
- Timing control circuit, 302... Quantizer, 303
... Inverse quantizer, 304 ... Shift register, 30
5...Predictor, 306.307...Data transfer register, 308...Subtractor, 309...Adder, 3
10...Pipeline register, 311.312...
・Selector, 710...Common bus, 802, 803・
··buffer.

Claims (3)

[Claims] (1) One screen of input image signals is vertically divided into N partial image signals (N is an integer of 2 or more) (hereinafter, each partial image signal is referred to as the k-th partial image signal, where k = 1,... , N), and the signal speed of each partial image signal is divided into 1 of the image signal.
/N times the speed and outputs the N partial image signals, and inputs the N partial image signals output from the speed converting means, and the value of k is 2 or more. a delay means for delaying a k-th partial image signal by (k-1) line periods of the image signal and outputting the N partial image signals; N signal processing means each input a partial image signal, perform predictive encoding processing on the partial image signal in raster scanning order, and output a DPCM encoded sequence signal; and N signal processing means output from the N signal processing means. A multiplexing means for multiplexing and outputting DPCM encoded sequence signals, a signal processing means for the k-th partial image signal, and a signal processing means for the k-1st and k+1th partial signals are connected, respectively. 1. A DPCM encoding device for an image signal, characterized in that it has a communication channel. (2) The DPCM encoding device for image signals according to claim 1, wherein the communication path is a local communication path that connects two adjacent signal processing means. (3) The DPCM encoding device for image signals according to claim 1, wherein the communication path is a common bus connecting the N signal processing means.