AU666442B1 - Image processing apparatus and method therefor - Google Patents

Description

I I- r_ 1 TITLE OF THE INVENTION IMAGE PROCESSING APPARATUS AND METHOD THEREFOR BACKGROUND OF THE INVENTION The present invention relates to an image processing apparatus for converting raster-sequential input image data into block-sequential image data and a method therefor.

As a conventional multi-value image compression technique, the JPEG (Joint Photographic Expert Group) method is a well known international standard mainly for the compression of natural image data. In this compression method, raster-sequential input RGB pixel components are converted into YUV pixel components (Y: luminance; U, V: chromaticity), and the resolution is lowered by sampling in some cases.

The YUV image data is subjected to discrete cosine transform (DCT) in units of 8 x 8 blocks, and is transformed to spatial frequency components. Data transformed into the spatial frequency components are 20 called DCT coefficients. TI, DCT coefficients are quantized in units of 8 x 8 blocks using two different 8 x 8 quantization tables respectively corresponding to e** luminance components and chromaticity components The quantization coefficients are subsequently 25 processed into variable length codes using the Huffman coding method.

*5 L I 2 As described above, since processing of the DCT is performed in units of 8 x 8 blocks, raster-sequential input pixels must be converted into block-sequential data prior to the DCT process. In order to realize this conversion process in a hardware manner, a memory for at least eight lines is used. Raster-sequenced pixel data is written to this memory, and after eight lines of data have been written, block-sequenced pixel data is read from this memory. The sequence of the write and read processes to this memory differs in accordance with the difference between the raster and block pixel data sequences. Also, in order to realize this conversion process in a conventional, real-time manner, two memories must be used, with each memory able to store at least eight lines of pixel data.

During a conventional, real-time conversion :*fee* process, the first memory is used to write rastersequenced pixel data, while the second memory is used S.to read block-sequenced pixel data. After eight lines •ego 20 of pixel data have been written to the first memory, the second memory is subsequently used to write rastersequenced pixel data, and the first memory is used to read block-sequenced pixel data. After another eight lines of pixel data have been written to the second •lee 25 memory, the conversion process cycle repeats so that tmtt the first memory is used to write raster-sequenced g .9

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-3pixel data, and the second memory is used to read block-sequenced pixel data.

SUMMARY OF THE INVENTION In accordance with one aspect of the present invention there is disclosed an image processing method for converting between raster-sequential image data and block-sequential image data, said blocks being composed of r rows of s pixels, and said image data comprising lines p pixels wide, said method comprising the step of reading and writing pixel data in parallel to a single r-line x p pixel memory buffer in a predetermined sequence to effect said conversion.

In accordance with another aspect of the present invention there is disclosed An image processing apparatus comprising: single memory means for storing raster-sequential, or block-sequential image data in units of n lines (n is an integer); means for dividing the image data stored in said memory means into n x k pixel groups (k is an integer) each consisting of I line x m pixels; means for determining addresses indicating read and write sequences of the image data in the n x k pixel groups; and conversion means for converting the n-line image data to eithe, x k block- •sequential order, or n line raster-sequential order by executing read and write accesses t to the image data buffer memory.

[N:\UIBoo]00709:IAD I I I~ I I 4 The capability of converting n x ast sequential image da o n x m block-sequential .ata.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the arrangement of a raster-block converter in an image processing apparatus according to an embodiment of the present invention; Fig. 2 is a view showing raster-sequential image data; Fig. 3 is a view showing block-sequential image data; Fig. 4 is a diagram showing the arrangement of a converter associated with data expansion in the first embodiment shown in Fig. 1; Fig. 5 is a flow chart showing a raster conversion sequence according to the first embodiment shown in S* Fig. 1; Fig. 6 is a view showing pixel group numbers of a 20 raster-block conversion line buffer according to the first embodiment shown in Fig. 1; Fig. 7 is a view showing the sequence of rasterblock conversion pixel groups according to the first embodiment shown in Fig. 1; e 25 Fig. 8 is a flow chart showing an inverse rasterblock conversion according to the second embodiment; ^ss^L~ r '1 I Fig. 9 is a view sh wing pixel group numbers of an inverse raster-block conversion line buffer acroding to the second embodiment; and Fig. 10 is a view showing the sequence of inverse raster-block conversion pixel groups according to the second embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

[First Embodiment] Fig. 1 is a block diagram showing the arrangement of a raster-block converter in an image processing apparatus (to be simply referred to as an apparatus hereinafter) according to the first embodiment of thb present invention. An address generation method in the raster-block converter will be described below with reference to Fig. 1.

Referring to Fig. 1, reference numeral 1 denotes .20 an address generation unit for raster-block conversion according to the apparatus of this embodiment; 2, a line buffer unit for realizing raster-block conversion; and 3, a color conversion unit for converting pixels of RGB components into YUV components. Reference numeral 25 4 denotes a DCT unit for executing DCT in units of 8 x8 pixels; 5, a quantization unit for quantizing DCT e*

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6 coefficients obtained by the DCT in the DCT unit 4; and 6, an encoding unit for encoding quantization coefficients.

In the raster-block converter shown in Fig. 1, image data is input in a raster sequence, corresponding to a left to right and top to bottom order of pixel data. The first pixel data is from the top left position of the image area, and the last pixel data is from the bottom right position of the image area (refer to Fig. 2) The raster-block converter partition; a two dimensional raster image into blocks of n x m pixels (refer to Fig. 3 where n m Pixel blocks are then output from the converter, in the order left to 15 right and top to bottom, beginning with the top left too* block and ending with the bottom right block. Within each block, pixel data is output in the order left to right and top to bottom, beginning with the top left pixel in a block and ending with the bottom right pixel ,ogo 20 of a block.

The raster-block converter achieves this "to conversion process by processing the image data in sections of n lines. A single memory buffer is used to temporarily store n lines of image data.

The image data which are converted into blocksequential data via the line buffer unit 2 are oodo IIC 7 sequentially supplied to the color conversion unit 3, and are then subjected to RGB YUV conversion.

Furthermore, the DCT in the DCT unit 4, quantization in the quantization unit 5, and coding in the encoding unit 6 are executed in turn, t us generating compressed data.

Fig. 4 is a diagram for explaining expansion of compressed data in the apparatus according to this embodiment. Referring to Fig. 4, reference numeral 11 denotes a decoding unit for performing an operation opposite to that in the encoding unit 6 shown in Fig.

1. Similarly, the converter comprises an inverse quantization unit 12 as opposed to the quantization unit 5, an inverse DCT unit 13 as opposed to the DCT unit 4, and an inverse color conversion unit 14 as opposed to the color conversion unit 3. Compressed data obtained by the converter shown in lig. 1 is expanded in a path opposite to that in compression.

That is, the compressed data is decoded by the decoding unit 11 shown in Fig. 4, is inversely quantized by the inverse quantization unit 12, is subjected to inverse DCT in the inverse DCT unit 13, and is then subjected to inverse color conversion in the inverse color conversion unit 14. Pixels which are converted into raw image data in this manner are converted from block- 8 sequential data into raster-sequential data via a line buffer unit In the apparatus according this embodiment, in order to realize raster-block ccnversion using a single line buffer, read and write accesses are made in one processing cycle. More specifically, a read access is made to a certain address during the first part of the process cycle, and a write access is made to the same address during the remaining part of the process cycle.

The apparatus according to this embodiment is capable of generating a sequence of memory addresses according to a defined algorithm (to be described later), necessary to achieve raster-block conversion in a realtime manner using a single n line memory buffer.

15 The raster address conversion in the apparatus of this embodiment will be described below.

Fig. 5 is a flow chart defining the raster address conversion sequence performed by the apparatus of this embodiment. An example of the raster address 20 conversion process according to this algorithm is shown in Fig. 6, and can be performed with the use of a memory line buffer sufficient to store data associated with 8 x 24 pixels. The 8 x 24 line buffer is divided into twenty-four 1 x 8 pixel groups (to be simply referred to as "PGs" hereinafter), and these groups are numbered from to as shown in Fig. 6.

9 Fig. 7 shows the sequence of PG addresses generated according to the definced algorithm that enable 1 x 8 pixel groups to be accessed. Note that individual pixel data within each pixel group are accessed using address offsets from the PG address according to the sequence 0, 1, 2, 6, 7.

Referring to Fig. 7, the first row shows the sequence of pixel group addresses for pixel data to be written to the memory buffer. The second and subsequent rows show the sequences of pixel group addresses for pixel data to be read from the memory buffer during the first part of each memory access cycle, and written to the S. memory buffer during the remaining part of each access cycle.

Gt 15 The raster address conversion in this embodiment will be described in detail below.

Referring to Fig. 5, when the line buffer has a pixel width of 24, as described above, and no subsampling is performed, is assigned to the number of e blocks (NB) for one line, and "24" is assigned to PG in step Sl. In step S2, since the processing routine is executed for the first time, the control sets: increment (.l.CREMENT) 1, predetermined value (VALUE) 0, group 'umber 1 I I 10 In step S3, since I is equal to or smaller than PG 24), YES is determined, and the flow advances to step S4. In step S4, VALUE is incremented: PG address 0, VALUE 1 Since PG address 0, the group number in the first row and the first column in the sequence of raster-block conversion pixel groups shown in Fig. 7 is In step S5, since VALUE 1) is neither equal to nor larger than PG 24), NO is determined, and the flow advances to step S6. In step S6, it is checked if I NB. In this case, since I 1) is not equal to NB the flow advances to step S9. More specifically, I is incremented by 1 to have I 2.

As a result of the above-mentioned processing, the flow returns to step S3. In this case as well, since I 2) is equal to or lower than PG 24), YES is determined in step S3. In step S4, the control sets: PG address 1, VALUE 2 Since PG address 1= the group number in the first row 20 and the second column in Fig. 7 is In step S5, since VALUE 2) is neither equal to nor larger than PG 24), NO is determined, and the flow advances to step S6. In step S6, since I 2) is not equal to NB NO is determined. The flow then advances to step S9 to set I 3.

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I LI r 11 When I 3, YES is determined in step S3 since the value is equal to or smaller than PG 24). In step S4, the control sets: PG address 2, VALUE 3 Since PG address 2, the group number in the first row and the third column in Fig. 7 is In step since VALUE 3) is neither equal to nor larger than PG 24), NO is determined, and the flow advances to step S6. In step S6, since I 3) is equal to NB YES is determined. As a result, in step S8, the control sets: next increment (NEXT INCREMENT) 3 In step S9, I is incremented to I 4.

Thereafter, similar processing is executed by 15 repeating a loop from step S3 to step S9. As a result, the group numbers in the first row and the fourth and subsequent columns in Fig. 7 are 1711 "11911 "23".

9* Upon completion of processing for the first row, 20 since I assumes a value of it is not determined in step S3 in Fig. 5 that I 25) is equal to or smaller than PG 24). Therefore, NO is determined in step S3, and the flow returns to step S2. As a result, the control sets: INCREMENT 3, VALUE 0, I 1 t,

T__

12 In step S3 next time, YES is determined since I 1) is equal to or smaller than PG 24). In step S4, the control sets: PG address 0, VALUE 3 Since PG address 0, the group number in the second row and the first column in Fig. 7 is In step S5, since VALUE 3) is neither equal to nor larger than PG 24), NO is determined. In step S6, since I 1) is not equal to NB the flow advances to step S9 to set I 2.

When the flow returns to step S3, since I 2) is equal to or smaller than PG 24), in step S4, the control sets: PG address 3, VALUE 6 S 15 In this case, since PG address 3, the group number in the second row and the second column in Fig. 7 is In step S5, since VALUE 6) is neither equal to nor larger than PG 24), NO is determined. Thereafter, in step S6, since I 2) is not equal to NB I 20 3 is set in step S9.

After I 3 is set, the flow returns to step S3 again. In step S3, since the value I is equal to or smaller than PG 24), YES is determined. In step S4, the control sets: PG address 6, VALUE 9 -13 In this case, PG address 6 means that the group number in the second row and the third column in Fig. 7 is In step S5, since VALUE 9) is neither equal to nor larger than PG 24), NO is determined. In step S6, since I 3) is equal to NB YES is determined. As a result, in step S8, the control sets: next increment (NEXT_INCREMENT) 9 In step S9, I 4 is set.

Thereafter, upon repetition of the above-mentioned processing loop from step S3 to step S9, the group numbers in the second row and the fourth and subsequent V columns are as shown in Fig.

4 7. 7 As a result of increment of I, if I 8 in step a. 15 S2, since this I is equal to or smaller than PG 24,' YES is determined in step S3. In step S4, the control sets: PG address 21. VALUE 24 Since PG address 21, the group number in the second *g row and the eighth column in Fig. 7 is "21".

In step S5, since VALUE 24) is equal to or larger than PG 24), YES is determined, and the flow advances to step S7. In step S7, VALUE 1 is set. In step S6, since I 8) is not equal to NB NO is determined. As a result, I 9 is set.

I I I 14 In step S3, since I 9) is equal to or smaller than PG 24), YES is determined, and in step S4, the control sets: PG address 1, VALUE 4 Since PG address 1, the group number in the second row and the ninth column in Fig. 7 is In step S5, since VALUE 4) is ne'.ther equal to nor larger than PG 24), NO is determined. In step S6, since I 9) is not equal to NB I 10 is set in step S9.

Similarly, upon repetition of the processing loop from step S3 to step S9, the group numbers in the second row and the tenth and subsequent columns in Fig.

7 are "23".

In this manner, when the above-mentioned processing operation is repeated up to the end pixel of an image, raster-block conversion is realized. In this case, upon execution of raster-block conversion for the last eight lines, only a read access to the line buffer 20 is made in one cycle, and no write access is made.

As described above, according to this embodiment, a read access is made to a given address at a certain clock and a write access is made to this address a half clock after the clock in a single line buffer, thereby realizing address generation for raster-block conversion. Therefore, the number of line memories can

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15 be reduced, and raster-sequential input image data can be converted into block-sequential data in a real-time manner.

The conventional method of raster-block conversion requires the use of separate memory buffers to perform write accesses of raster-sequential pixel data and read accesses of block-sequential pixel data. The method described above performs read and write accesses on the same memory buffer, and thereby requires half the menory capacity of the conventional me;,hod.

In the above embodiment, as shown in Fig. 1, the line buffer unit 2 is arranged at the input side of the color conversion unit 3. However, the present invention is not limited to this arrangement. For example, the line buffer unit 2 may be arranged between the color conversion unit 3 and the DCT unit 4. In the above embodiment, the width of input image data is set to be 24. However, the present invention is not limited to this.

20 Furthermore, in the above embodiment, the raster-

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block converted block size is set to be 8 x 8. However, when in PG NB 8 is changed to an arbitrary a.E value in step Sl in Fig. 5, the height of a unit block can be changed. Also, in the above embodiment, each pixel group size is set to be 1 x 8. However, when the pixel group size is set to be 1 x m (m is an

P-

16 arbitrary value), arbitrary block-sequence conversion in units of n x m blocks can be realized.

[Second Embodiment] Raster block conversion executed when compressed data is decompressed, will be described below in accordance with Figs. 8, 9 and 10 according to the second embodiment of the present invention.

Fig. 8 is a flow chart showing a sequence of inverse raster-block conversion. Fig. 9 is a view showing numerals of PIXEL GROUP (PG) of a line buffer.

This line buffer consisting of 24 PIXEL GROUP's, each of which has 1 x 8 pixels, is the same as that of the raster-block conversion for data compression, except for the numbering of the PIXEL GROUP.

Fig. 10 shows a sequence of pixel group adresses for the inverse raster-block conversion. In Fig. the first row shows the sequence of pixel group oo.. addresses for block-sequential pixel data to be written to memory in, and the second and subsequent rows show 20 the sequences of pixel group addresses for rastersequential pixel data to be read and block-sequential pixel data to be written to memory during each memory access cycle. Note that individual pixel data within each pixel group are accessed using address offsets from the PG address according to the sequence 0, 1, 2, 6, 7..

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17 The raster-block conversion in this embodiment will be described in detail below.

Referring to Fig. 8, since is assigned to the number of blocks (NB) for one line, PG becomes 24 3 x 8) and NEXT INCREMENT 1 in step S10, in step S11, the control sets: increment (INCREMENT) 1, predetermined value (VALUE) 0, group number 1 In step S12, since is smaller than PG 24), YES is determined, and the flow advances to step S13. In step S13, VALUE is incremented: PG address 0, VALUE 1 Since PG address 0, the group number in the first row and the first column in the sequence of inverse raster- S 15 block conversion pixel groups shown in Fig. 10 is In step S14, since VALUE 1) is neither equal to nor larger than PG 24), NO is rendered, and the flow advances to step S16. In step S16, it is checked if I 8. In this case, since I 1) is not equal to 8,

C.

20 the flow advances to step S18. More specifically, I is incremented by 1 to have I 2.

As a result of the above-mentioned processing, the 5 Sflow returns to step S12. In step S12, since I 2) is lower than PG 24), YES is determined. In step S13, the control sets: PG address 1, VALUE 2 I -I I 18 Since PG address 1, the group number in the first row and the second column in Fig. 10 is In step S14, since VALUE 2) is not larger than PG 24), NO is determined, and the flow advances to step S16. In step S16, since I 2) is not equal to 8, NO is determined. The flow then advances to step S18 to set I 3.

Thereafter, processing is executed by repeating a loop from step S12 to step S18. If it is determined that I 8 at step S16, the flow advances to step S17 and NEXT INCREMENT 8 is obtained. As a result, the group numbers in the first row and the third and subsequent columns in Fig. 10 are 16111 11"6" 7 "23".

Upon completion of processing above, data of the first eight lines has been written in to the line buffer. A method of generating address for a line 0s* buffer in which read/write operations are performed in one cycle will be described below.

20 After gaining PG ADDRESS 23 and executing to processings at steps S14, S16 and S18, it is determined in step S12 in Fig. 8 that I 25) is not smaller than

C.

PG 24) and NO is determined. Then, the flow returns to step S11. In step Sl, the control sets: INCREMENT 8, VALUE 0, I 1 ~C 19 In step S12 next time, YES is determined since I 1) is smaller than PG 24). In step S13, the control sets: PG address 0, VALUE 8 Since PG address 0, the group number in the second row and the first column in Fig. 10 is In step S14, since VALUE 8) is not larger than PG 24), NO is determined. In step S16, since I 1) is not equal to 8, the flow advances to step S18 to set I 2.

When the flow returns to step S12, since I 2) is smaller than PG 24), in step S13, the control S. sets: o* PG address 8, VALUE 16 15 In this case, since PG address 8, the group number in the second row and the second column in Fig. 10 is In step S14, since VALUE 16) is not larger than PG 24), NO is rendered. Thereafter, in step S16, since I 2) is not equal to 8, I 3 is set in step S18.

20 After I 3 is set, the flow returns to step S12 again. In step S12, since the value I is smaller than PG 24), YES is determined. In step S13, the o* control sets: PG address 16, VALUE 24 In this case, PG address 16 means that the group number in the second row and the third column in Fig.

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I -I 20 is In step S14, since VALUE 24) is larger than PG 24), YES is determined. In step S15, VALUE 1 is obtained by performing a calculation of 24-24+1.

In step S16, since I 3) is not equal to 8, NO is determined. As a result, in step S18, I 4 is set.

In step S12 again, since I is smaller than PG YES is rendered and the flow advances to step S13. In step S13, PG ADDRESS 1 and VALUE 9 are obtained.

In this case, the group number in the second row and the fourth column is as shown in Fig. In step S14, since VALUE 24) is not larger than PG 24), NO is determined, and the flow advances to Sstep S16. In step S16, since I 4) is not equal to 8, NO is determined. As a result, I 5 is set in step S18, and the flow returns to step S12 again.

Similarly, upon repetition of the processing loop from step S12 to step S18, the group numbers in the second row and the fifth and subsequent columns in Fig.

10 are "23".

In this manner, when the above--mentioned processing operation is repeated up to the end pixel of an image, inverse raster-block conversion is realized.

In this case, upon execution of inverse raster-block conversion for the last eight lines, only a read access 21 to the line buffer is made in one cycle, and no write access is made.

The present invention may be applied to either a system comprising a plurality of devices or an apparatus comprising a single device. The present invention may also be applied when the invention is achieved by supplying a program to the system or apparatus, as a matter of course, In this manner, when read and write accesses of image data are executed in accordance with addresses indicating read and write sequences of image data, which addresses are determined for n x k pixel groups, raster-sequentially input image data can be converted *fee into block-sequential image data, and also blocksequential input image drta can be converted into raster-sequential image data using a single memory.

Since only one memory is used, the apparatus cost can be reduced.

If integers n and k for defining n x k pixel 20 groups are variables, block-sequential conversion with arbitrary sizes can be attained.

As many apparently widely different embodiments of the present invention can ze made without departing from the spirit and scope thereof, it is to be understood that the invention is not limited to the -22 specific embodiments thereof except as defined in the appended claims.

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Claims (9)

1. An image processing method for converting between raster-sequential image data and block-sequential image data, said blocks being composed of r rows of s pixels, and said image data comprising lines p pixels wide, said method comprising the step of reading and writing pixel data in parallel to a single r-line x p pixel memory buffer in a predetermined sequence to effect said conversion.

2. image processing apparatus comprising: single memory means for storing raster-sequential, or block-sequential image data in units of n lines (n is an integer); S 10o means for dividing the image data stored in said memory means into n x k pixel groups (k is an integer) each consisting of 1 line x m pixels; means for determining addresses indicating read and write sequences of the image data in the n x k pixel groups; and conversion means for converting the n-line image data to either n x k block- 15 sequential order, or n line raster-sequential order by executing read and write accesses to the image data buffer memory.

3. The apparatus according to claim 2, wherein said conversion means performs the read access of the image data to a given address at a predetermined clock, and IN:\lIBolOO()09:IAD 24 performs the write access a half clock after the predetermined clock.

4. The apparatus according to claim 2, wherein numbers are assigned to the n x k pixel groups, and said conversion means performs the read and write accesses of the image data on the basis of the relationship between the numbers and the addresses.

5. The apparatus according to claim 2, wherein the n, m and k are variables. e S.

6. An image processing method comprising the steps *o0* of: 15 storing raster-sequentially input image data in a single memory in units of n lines (n is an irreger); dividing the image data stored in said memory into x k pixel groups (m is an integer) each consisting of 1 line x m pixels; 20 determining addresses indicating read and write f sequences of the image data in the m x k pixel groups; and converting the n-line image data into r x k block- sequential image data by executing read and write accesses of the image data in the pixel groups in accordance with the addresses. 25

7. An image processing method, comprising: a step of storing the number of blocks in one line; a step of storing the number of (1 x m) pixel groups (hereinafter simply referred to as pixel groups) in n lines; a step of storing address of the next pixel groups to be accessed; a step of storing the present add-on value; a step of storing an add-on value for the next n lines subjected to raster-block conversion; a step of storing a value indicating the present rtoo state of processing; 15 a step of writing in 1 as the add-on value for the next n lines subjected to raster-block conversion; a step of determining whether or not the value indicating the present state of processing is larger than said number of the pixel groups in n lines; 20 a step of substituting said add-on value for the next n lines subjected to raster-block conversion for said present add-on value, substituting 0 for said address of the next pixel groups to be accessed, and further making said value indicating the present state of processing 1; 26 a step of substituting said address of the next pixel groups to be accessed for the present address accessed by the pixel groups, and further substituting an add-on result of said address of the next pixel groups to be accessed and said present add-on value for said address of the next pixel groups to be accessed; a step of determining whether or not said address of the next pixel groups to be accessed is larger than said number of pixel groups in n lines; a step of substituting a result of adding 1 to a difference between said address of the next pixel groups to be accessed and said number of pixel groups gO in n lines for said address of the next pixel groups to be accessed; 15 a step of determining a relationship between said value indicating the present state of processing and said number of blocks in one line or a prescribed value; s a step of substituting said address of the next 20 pixel groups to be accessed for said add-on value for the next n lines subjected to raster-block conversion; and I a step of substituting a result of adding 1 to said value indicating the present state of processing for said value indicating the present state of processing. DATED this TWENTY-EIGHTH day of JUNE-k-UNF iCR Canon Kabushiki SPatent Att for the Applicant SPRUSON FERGUSON C7_ -27-

8. An image nrocessing method substantially as described herein with reference to Figs. 1 to 7, or Figs. 8 to 10 of the drawings.

9. Image processing apparatus substantially as described herein with reference to Figs. 1 to 7, or Figs. 8 to 10 of the drawings. DATED this Twentieth Day of November 1995 Canon Kabushiki Kaisha Patent Attorneys for the Applicant SPRUSON FERGUSON 1.* see 00*0 0 pp 0, p r O p p p IN:\Lllool(X)709:l AD Image Processing Apparatus and Method Therefor ABSTRACT An image processing apparatus according to this invention converts raster-sequentially input image into block-sequential image data using a single memory. In order to realize raster-block conversion by a line buffer unit read and write accesses are made in a single processing cycle. More specifically, a read access is made to a given address at a certain clock, and a write access is made to this address a half clock after the clock. An address generation unit is directed to address generation in the processing, and raster-block conversion is executed in a pipeline manner using a single line buffer in accordance with addresses generated by the address generation unit. *see (Figure 1) S S S S