JPH08251598A - Image encoding device and image decoding device - Google Patents

Abstract

PURPOSE: To provide an image encoding device and image decoding device which are flexibly adaptive to various encoding systems and decoding systems. CONSTITUTION: The device has an image division part 10 which divides a frame or field into M partial images, N encoding parts 11 to 14 which operate in parallel to one another to perform encoding, N frame memories 15 to 18 which store signals decoded in the respective encoding parts, and an encoding part bus circuit 20 which writes an (m)th partial image as a signal obtained by decoding a frame or field encoded by an (n)th encoding part, part of an (m-1)th partial image as a signal obtained by decoding a frame or field encoded at least by an (n-1)th encoding part, and a part of an (m+1)th partial image as a signal obtained by decoding a frame or field encoded at least by an (n+1)th encoding part in an (n)th frame memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image coding apparatus for coding and compressing an image and an image decoding apparatus for decoding a coded image signal, and more particularly to a bus structure between unit processors operating in parallel. The present invention relates to an image coding apparatus and an image decoding apparatus that can be configured without a complicated configuration and without being affected by the number of unit processors, and can flexibly support various coding methods and decoding methods.

[0002]

2. Description of the Related Art An example of a conventional image coding apparatus and image decoding apparatus apparatus is shown in FIG. This figure shows
It is a block diagram of the moving image encoding apparatus disclosed by Unexamined-Japanese-Patent No. 62-86464. This conventional example is a moving picture coding apparatus using a plurality of processors. However, since the present invention is characterized by the configuration of the bus interface between the unit processors that perform parallel processing, here, the unit processors The bus connection method or the bus configuration will be mainly described, and the configuration of each unit processor will not be described in detail.

The image coding apparatus of this conventional example is a multiprocessor type moving picture coding apparatus, in which one screen is divided into a plurality of units, and one unit processor is assigned to each screen. An image signal is encoded in parallel by unit processors.

In FIG. 6, 101 is an input bus for transmitting an input image signal such as a television signal, 102 is a feedback bus for transmitting an encoded / decoded partial screen signal, 1
03 is an output bus for transmitting the encoded result, 104,
105 and 106 are first, second and third unit processors, respectively.

FIG. 7 is an explanatory diagram showing an example of division of an image frame or field. In this conventional example, one screen is divided into a plurality of units and one unit processor is assigned to each screen. Here, the first, second and third unit processors 104, 105 and 106 are respectively shown in FIG. The divided screens A to C are to be shared and processed.

[0006] Each unit processor is internally provided with a capturing section 107, a processing section 108 and an output section 109.
In the acquisition unit 107, in synchronization with the acquisition command of the divided screen area in charge, an input image signal (partial image signal) of the divided screen area in charge is input from the input bus 101, and a code for neighborhood processing from the feedback bus 102. Each of the encoded / decoded signals is captured and stored. As for the neighborhood processing, there is a method disclosed in JP-A-62-266678.

The processing unit 108 also performs processing such as encoding / decoding on the image data stored in the capturing unit 107. Further, in the output unit 109, the encoded signal as the processing result in the processing unit 108 is sent to the output bus 103 in synchronization with the next captured signal, and the encoded / decoded signal is fed back as an auxiliary signal of the input image. It is sent to another unit processor via the bus 102.

Next, referring to the timing chart shown in FIG. 8, the operation of the conventional moving picture coding apparatus will be described. Here, as shown in FIG. 7, the entire screen is decomposed into three partial screens A to C, and these partial screens are processed by the first unit processor 104, the second unit processor 105, and the third unit processor 106, respectively. And

First, as shown in FIG. 8A, as the television signals corresponding to the partial screens A to C, the input partial screen signals S1 to S3 continuously flow in time on the input bus 101. For example, the first unit processor 104 is shown in FIG.
The input partial screen signal S1 on the input bus 101 is fetched and stored in the fetching section 107 at the fetching operation timing as shown in FIG. Here, each input partial screen signal S1 to S
3 is input at a constant cycle, the process for each input partial screen signal S1 to S3 must be completed by the next input partial screen signal S1 to S3.

On the other hand, the partial screen coded signal O1 obtained as a result of the processing of the processing unit 108 is the same as the acquisition of the next input partial screen signal S1 by the acquisition unit 107, and the output unit
09 to the output bus 103.

FIG. 9 is an explanatory diagram of a motion-compensated interframe coding system that is often applied as a high-efficiency image coding technique.
Shown in In the motion-compensated interframe coding method, coding is performed by taking the difference between the input image P and the image Q whose screen position is displaced by the amount of motion in the decoded screen that is one screen previous. For such encoding processing, an encoded / decoded screen in which the area is expanded by the amount of motion is required. Therefore, in the motion compensation interframe coding method, a screen signal in a wider range than the input partial screen signals S1 to S3 is required.

Further, the encoded / decoded partial screen signal F1
.About.F3 are output from the output unit 109 to the feedback bus 102, and are fetched and stored in the fetching unit 107 at the fetching operation timings shown in FIGS.
At this time, in the motion-compensated interframe coding method, since the data of a wider range than the input partial screen signals S1 to S3 is captured, the capture time becomes long. Therefore, the encoding process is executed while taking in the encoded / decoded partial screen signals F1 to F3 in a wider range than the allocated partial screen, and the signals O1 to O3 are output to the output bus 103.

[0013]

As described above, in the conventional image coding apparatus and image decoding apparatus, the code required for each unit processor is input via the feedback bus within the cycle in which the partial divided screen is input. It is necessary to transfer the encrypted / decoded partial screen signal. Therefore, if the number of unit processors connected to the feedback bus increases beyond a certain number, the amount of data to be transferred on the feedback bus also exceeds the limit, In order to complete all transfers within a fixed cycle time, it is necessary to increase the bus width. Therefore, if the number of unit processors operating in parallel greatly increases, the bus width becomes too large, which is inconvenient for the hardware configuration. There was a problem of becoming.

Even if the hardware can be configured, the optimum bus width differs depending on the number of unit processors operating in parallel. Therefore, if the number of unit processors changes, it is necessary to change the bus interface configuration of the unit processors. There was a problem.

The present invention solves the above-mentioned problems.
An image coding apparatus capable of configuring a bus structure between unit processors operating in parallel without complicated structure and without being influenced by the number of unit processors and capable of flexibly supporting various coding methods and decoding methods. Another object of the present invention is to provide an image decoding device.

[0016]

In order to solve the above-mentioned problems, the image encoding device of the first feature of the present invention is an image signal which is an image signal blocked in a frame or field and has already been encoded. Alternatively, in an image coding apparatus for quantizing a differential signal between a field-decoded signal and a current frame signal or field signal, and further performing variable-length coding, the frame or field from the first partial image to the Mth partial image An image dividing unit that divides the image into M (M is an arbitrary positive integer) partial image, and the first encoding unit to the Nth code for the M partial images from the first partial image to the Mth partial image. N (where N is a positive integer that satisfies N <M) encoding units that are cyclically corresponding to each other and operate in parallel with each other to encode; and from the first encoding unit to the Nth encoding unit. Each corresponds to the above N frame memories for storing signals obtained by decoding the coded frames or fields in each coding unit, and the frames or fields already coded by the n-th coding unit (n = 1 to N). M-th partial image (m = 1 to M) which is a signal obtained by decoding the above-mentioned signal, and the m-th signal which is obtained by decoding at least the already-encoded frame or field encoded by the (n-1) -th encoding unit. A part of the -1 partial image and at least a part of the m + 1 partial image which is a signal obtained by decoding the already coded frame or field encoded by the n + 1 encoding unit; And an encoding unit bus circuit for writing in a memory.

The image coding apparatus according to the second aspect of the present invention is the image coding apparatus according to claim 1, wherein the image division unit divides the frame or field for each slice. is there.

The image coding apparatus of the third feature of the present invention is the image coding apparatus according to claim 2, wherein when L is an arbitrary natural number, the number N satisfies the following equation. is there. (Number of effective lines in one frame or field) ≦ L × 16 × N ≦ (total number of lines in one frame or field; including vertical blanking interval) (1)

The image coding apparatus according to the fourth aspect of the present invention is the image coding apparatus according to claim 2, wherein when L is an arbitrary natural number, the number N satisfies the following equation. is there. (Number of effective lines in one frame) ≤ 2 x L x 16 x N ≤ (total number of lines in one frame; including vertical blanking interval) (2)

The fifth aspect of the image encoding device of the present invention is the image encoding device according to the second, third or fourth aspect, which is configured by including a clock generator for generating an operation clock, The frequency of the operation clock and the number N satisfy the following equation. (Clock frequency) = (Sampling frequency) x (3 or 2 or 1.5) / N (3)

The image decoding apparatus of the first feature of the present invention is the image signal blocked on the frame or field and already decoded, and the current frame signal or field signal. In an image decoding apparatus for quantizing a differential signal between the variable length coded image signal and the variable length coded image signal, the variable length coded frame signal or field signal is converted from the first partial image coded signal to the Mth partial signal. M up to image coded signal
A code division unit that divides into a plurality of (M is an arbitrary positive integer) partial image coded signal, and the first partial image coded signal to the M-th
The first decoding unit to the N-th decoding unit cyclically respond to M partial image coded signals up to the partial image coded signal, and N (N is N A positive integer that satisfies N <M) and the first to Nth decoding units, respectively, and stores the frame signal or field signal already decoded in each decoding unit. N frame memories and the n-th decoding unit (n =
1 to N), the m-th partial image (m = 1 to M) that is a frame or field decoded, and at least the m-1 th frame that is a frame or field decoded by the n-1 th decoding unit. A decoding unit bus circuit for writing a part of the partial image and at least a part of the (m + 1) th partial image which is a frame or field decoded by the (n + 1) th decoding unit into the nth frame memory; And an image combining unit that combines the partial images decoded by the individual decoding units into a frame or a field.

The image decoding apparatus according to the second aspect of the present invention is the image decoding apparatus according to claim 6, wherein the code division unit slices the encoded frame signal or field signal into one slice. It is to be divided into encoded signals of each encoded partial image.

The image decoding apparatus of the third feature of the present invention is the image decoding apparatus according to claim 7, wherein when L is an arbitrary natural number, the number N satisfies the following equation. is there. (Number of effective lines in one frame or field) ≦ L × 16 × N ≦ (total number of lines in one frame or field; including vertical blanking interval) (1)

The image decoding apparatus of the fourth feature of the present invention is the image decoding apparatus according to claim 7, wherein, when L is an arbitrary natural number, the number N satisfies the following equation. is there. (Number of effective lines in one frame) ≤ 2 x L x 16 x N ≤ (total number of lines in one frame; including vertical blanking interval) (2)

Furthermore, the image decoding device of the fifth feature of the present invention is the image decoding device according to claim 7, 8 or 9 and further comprises a clock generator for generating an operation clock, The frequency of the operation clock and the number N satisfy the following equation. (Clock frequency) = (Sampling frequency) x (3 or 2 or 1.5) / N (3)

[0026]

According to the image coding apparatus and the image decoding apparatus of the present invention, when a plurality of unit processors (encoding unit or decoding unit) operate in parallel, a certain unit processor is used for encoding or decoding an image. In the above, in order that the unit processor can use the partial image coded or decoded in the past and the partial image coded or decoded in the past around the partial image, the same number of frame memories and unit It is provided with an encoding bus circuit or a decoding bus circuit that connects between the processor and the frame memory, and each unit processor is in charge of encoding or decoding at the same position in each frame or field. .

In the image coding apparatus of the first feature of the present invention, the n-th coding unit always codes the m-th partial image at the same position for each frame or each field. Also nth
The n-th frame memory used by the encoding unit includes the m-th partial image of the already encoded frame or field, a part of the (m-1) th partial image, and a part of the (m + 1) th partial image by the encoding unit bus circuit. At least part is preserved.
Therefore, the n-th encoding unit can take the difference between the current frame or field and the already encoded frame or field at least within the range of the stored partial image. Therefore, the n-th encoding unit selects an appropriate prediction image from the already-encoded frame or field even for a boundary between the image included in the m-th partial image and the m-1th partial image. , It becomes possible to efficiently encode an image.

As a result, the bus configuration between a plurality of encoding units (unit processors) operating in parallel can be configured without a complicated configuration and without being affected by the number of unit processors, and various encoding systems can be used. It is possible to realize an image encoding device that can flexibly deal with.

Further, in the image coding apparatus of the second feature of the present invention, the image dividing unit divides the frame or field into slices and divides the partial image into slices, thereby performing each encoding. The unit sets the difference in load at the time of encoding to a maximum of 1 slice, and the frame or field is encoded by a plurality (N) of encoding units.

In the image coding apparatus of the third feature of the present invention, the number N of coding units is set to the number satisfying the expression (1) regarding the frame, and the time when there is no effective line included in the frame cycle time. Can be used, it is possible to code an image more efficiently in a frame unit as compared with an image coding apparatus including a number of coding units that do not satisfy the above formula (1).

Further, when the number N of coding units is set to the number satisfying the expression (1) regarding the above field,
Since it is possible to use the time when there is no effective line included in the field cycle time, it is possible to use the time more efficiently than the image coding apparatus including the number of coding units that do not satisfy the above expression (1). Images can be encoded in units.

Further, in the image coding apparatus of the fourth feature of the present invention, the number N of coding units is set to the number satisfying the expression (2) regarding the frame, and the time when there is no effective line included in the frame cycle time. Is used, it is possible to more efficiently encode the image in both the frame unit or the field unit, as compared with the image encoding device including the number of encoding units that do not satisfy the expression (2). be able to.

Further, in the image coding apparatus of the fifth feature of the present invention, the operation clock generated in the clock generator is set to the clock frequency satisfying the above expression (3), and the low frequency clock is used.

Further, in the image decoding apparatus of the first feature of the present invention, the n-th encoding unit is sure to encode the encoded signal of the m-th partial image at the same position for each frame signal or each field signal. Decryption of. In addition, the n-th frame memory used by the n-th decoding unit includes the m-th frame of the frame or field already decoded by the decoding unit bus circuit.
At least a partial image, a part of the (m-1) th partial image, and a part of the (m + 1) th partial image are stored. Therefore, the n-th decoding unit can take the sum of the current frame or field and the already decoded frame or field at least within the range of the stored partial image. Therefore, the n-th decoding unit selects an appropriate prediction image from the already-decoded frame or field even for the boundary between the image included in the m-th partial image and the m-1th partial image. , The image can be efficiently decoded.

As a result, the bus configuration between the plurality of encoding units (unit processors) operating in parallel can be configured without a complicated configuration and without being affected by the number of unit processors, and can be applied to various decoding systems. It is possible to realize a flexible image decoding device.

Further, in the image decoding apparatus of the second feature of the present invention, the code division unit encodes the encoded frame signal or field signal for each slice, and encodes a partial image of the encoded partial image. By dividing the partial image into slices and dividing the partial image into slices, each decoding unit sets the difference in load at the time of decoding to one slice at the maximum, and decodes the frame or field with a plurality of (N) decoding units. I am trying.

In the image decoding apparatus of the third feature of the present invention, the number N of decoding units is set to the number satisfying the expression (1) regarding the frame, and the time when the effective line included in the frame cycle time does not exist. Can be used, it is possible to more efficiently decode the image on a frame-by-frame basis, as compared with an image decoding apparatus including a number of decoding units that do not satisfy the above expression (1).

If the number N of decoding units is the number satisfying the expression (1) for the above field,
Since it is possible to use the time when there is no effective line included in the field cycle time, it is possible to use the time more efficiently than the image decoding apparatus including the number of decoding units that do not satisfy the above expression (1). Images can be decoded in units.

Further, in the image decoding apparatus of the fourth feature of the present invention, the number N of decoding units is set to the number satisfying the expression (2) regarding the frame, and the time when there is no effective line included in the frame cycle time. Is used, the image is decoded more efficiently in both the frame unit and the field unit as compared with the image decoding device including the number of decoding units that do not satisfy the above expression (2). be able to.

Further, in the image decoding apparatus of the fifth feature of the present invention, the operation clock generated in the clock generator is set to the clock frequency satisfying the above expression (3), and the low frequency clock is used.

[0041]

Embodiments of the present invention will now be described with reference to the drawings. Example 1. FIG. 1 shows a block diagram of an image coding apparatus according to a first embodiment of the present invention. In the figure, the image coding apparatus according to the present embodiment includes an image dividing unit 10 and four coding units (N =
4), four frame memories, an output bus 19, and an encoder bus circuit 20. still,
In the figure, 31 is an image signal and 32 is an encoded signal.

The four coding units are the first coding unit 11, the second coding unit 12, the third coding unit 13, and the fourth coding unit 1.
Each of the four frame memories is composed of a first frame memory 15, a second frame memory 16, a third frame memory 17, and a fourth frame memory 18. The encoding unit bus circuit 20 includes a first encoding bus 21, a second encoding bus 22, a third encoding bus 23, and a fourth encoding bus 24, and an encoded signal 32 from the output bus 19. Is output.

In the image division unit 10, one frame signal of HDTV, which is the image signal 31 to be encoded, is converted into a horizontal 1
It is divided into a total of 34 partial images of 920 pixels × 32 vertical lines. FIG. 2 shows how the frame is divided into 34 partial images of 32 lines.

Further, the first encoding unit 11 has a horizontal 1920
Of a total of 34 partial images divided into 32 pixels × vertical 32 lines, the first, fifth, ninth, thirteenth, seventeenth, twenty-first,
The 25th, 29th and 33rd partial images are encoded. The second encoding unit 12 selects, among the 34 partial images, the second, sixth, tenth, fourteenth, eighteenth, twenty-second, twenty-sixth,
The 30th and 34th partial images are encoded. Third
The encoding unit 13 selects the third, seventh, and
The 11th, 15th, 19th, 23rd, 27th and 31st partial images are encoded. Furthermore, the fourth encoding unit 14
Is the fourth, eighth, twelfth, first of the 34 partial images.
The sixth, the 20th, the 24th, the 28th and the 32nd encoding are performed.

Further, the first frame memory 15 stores the signal obtained by decoding the already encoded frame in each encoding unit, and the first frame memory 15 stores the signal in the first encoding unit 1.
A signal necessary for encoding with 1 is read out. The second frame memory 16 stores the signal obtained by decoding the already encoded frame in each encoding unit, and the signal necessary for encoding by the second encoding unit 12 is read from the second frame memory 16. Be done.

The third frame memory 17 stores the signal obtained by decoding the already encoded frame in each encoding unit, and the third frame memory 17 stores the signal in the third encoding unit 13.
A signal necessary for encoding is read out. Furthermore, the fourth
The frame memory 18 stores the signal obtained by decoding the already encoded frame in each encoding unit, and the signal necessary for encoding by the fourth encoding unit 14 is read from the fourth frame memory 18.

The image signal encoded by the first, second, third and fourth encoders 11, 12, 13 and 14 is output to the output bus 19 and becomes an encoded signal 32.

In the encoding unit bus circuit 20, the first encoding bus 21 is connected to the first, second and fourth encoding units 11 and 12.
And the partial image signal encoded and further decoded by
Write to the frame memory 15. In addition, the second encoding bus 2
2 is the first, second and third encoding units 11, 12 and 13
The partial image coded by and further decoded is written in the second frame memory 16. In addition, the third encoding bus 23 is
The partial images coded and further decoded by the third and fourth coding units 12, 13 and 14 are written in the third frame memory 17. Further, the fourth encoding bus 24 is connected to the first, third and fourth
The partial image coded by the coding units 11, 13 and 14 and further decoded is written in the fourth frame memory 18.

In general, an image signal blocked on a frame or field, a difference signal between a signal obtained by decoding an already encoded frame or field and a current frame signal or field signal is quantized, and a variable length code is further added. In the image encoding device for encoding, when taking the difference between the signal obtained by decoding the already encoded frame or field and the current frame signal or field signal,
A block of horizontal 16 pixels × 16 lines is often used as a unit, and this unit is called a macro block.

At this time, a macroblock on a current frame or field and a macroblock on a frame or field which has already been coded to obtain a difference from the macroblock often have different positions on the frame or field. Therefore, when the encoding unit encodes a partial image obtained by dividing the current frame or field, the block in the area other than the already-encoded partial image of the frame or field corresponding to the position of the partial image is calculated to obtain the difference. Must have access.

In the image coding apparatus of this embodiment, in order to make this possible, the plurality of frame memories 15-18 are used.
And a coding unit bus circuit 20, the signal of a region that may be accessed among the already-coded frame or field signals may be a region coded by another coding unit. The frame memory corresponding to each encoding unit is stored in advance.

Further, in the image coding apparatus according to the present embodiment, the number of pixels in the horizontal direction of the frame or field to be coded or the number of lines in the horizontal direction changes, or the number N of coding units operating in parallel changes. Even if the individual encoding unit 1
1 to 14, the frame memories 15 to 18, and the encoding bus circuit 20 can be dealt with without changing much.

Next, the operation of the coding apparatus of this embodiment will be described with reference to the explanatory diagram of FIG. 2 and the timing chart of the coding operation shown in FIG.

As shown in FIG. 2, the image dividing section 10 receives the input image signal 31, that is, the horizontal signal 19 as an effective signal.
A frame signal having 20 pixels × 1080 vertical lines is divided into a total of 34 partial images in which one partial image is horizontal 1920 pixels × vertical 32 lines. At this time, the third
The fourth 34th partial image includes an invalid line signal composed of invalid data for 8 lines.

The image dividing section 10 is shown in FIG.
As shown in (d), the first partial image S01 is assigned to the first encoding unit 11, the second partial image S02 is assigned to the second encoding unit 12, and the third partial image S03 is assigned to the third encoding in the order of occurrence of partial images. Conversion unit 13
The fourth partial image S0 to the fourth encoding unit 14, the fifth partial image S05 to the first encoding unit 11, the sixth partial image S06 to the second encoding unit 12, and the seventh partial image S07. Third encoding unit 1
3, the eighth partial image S08 to the fourth encoding unit 14, the ninth partial image S09 to the first encoding unit 11, and so on. It outputs to 14 circularly.

In the first encoding unit 11, as shown in FIG. 3A, the first partial image S01 input from the image dividing unit 10 is inputted.
Is divided for each macroblock, and the first for each macroblock
The difference is obtained with the macroblock of the already encoded frame read from the frame memory 15. Then, the difference signal is variable-length coded and output O01 is output to the output bus 19.

On the other hand, the coded signal of the variable-length-encoded first partial image is decoded by the first encoding unit 11, and is encoded by the encoding unit bus circuit 20 into the first, second, and fourth frame memories 15, It is stored in 16 and 18. The processing operations of the second, third, and fourth encoding units 12, 13, and 14 are basically the same as shown in FIGS. 3B to 3D, though the target partial images and frame memories are different. Is.

The first frame memory 15 outputs to the first encoding unit 11 a macroblock of an already-encoded frame which should be differentiated from the macroblock to be encoded by the first encoding unit 11 according to an instruction from the outside. . The processing operations of the second, third and fourth frame memories 16, 17 and 18 are basically the same although the target partial image and the encoding unit are different.

In the encoding section bus circuit 20, the first frame memory 15 is connected to the first and second frames via the first encoding bus 21.
And the partial images encoded by the fourth encoding units 11, 12 and 14 are stored in the second frame memory 15 in the second encoding bus 2
The partial images encoded by the first, second and third encoding units 11, 12 and 13 via the second frame memory 17 are stored in the third frame memory 17
The partial image encoded by the second, third and fourth encoding units 12, 13 and 14 via the third encoding bus 23, and the fourth encoding bus 24 in the fourth frame memory 18. The partial images encoded by the third, fourth, and first encoding units 13, 14, and 11 are respectively stored via the above.

The image coding apparatus according to the present embodiment is not limited to the above-described specifications and configuration, and the following various modifications can be considered. (1) In the above description, division into partial images is performed for an image in which one frame has horizontal 1920 pixels × vertical 1080 lines, but other sizes may be used. (2) In the above description, encoding was performed in frame units,
You may also go field by field. (3) In the above description, the partial image is divided every vertical 32 lines, but it may be divided with more lines. (4) In the above description, assuming that N = 4, the four coding units 11 to 11
Although the encoding is performed by 14, the number is not limited to four, and any integer can be similarly configured.

(5) In the above description, the n-th frame memory used by the n-th encoding unit for encoding the m-th partial image is used for the m-th frame of the already encoded frame or field.
Although the 1st partial image, the mth partial image, and the m + 1th partial image are saved, a part of the m−1th partial image and the m + 1th partial image may be saved. (6) In the above description, the encoding unit bus circuit 20 can write the image signal encoded by the (n-1) th encoding unit, the nth encoding unit and the (n + 1) th encoding unit into the nth frame memory. However, the image signal encoded by the (n−2) th encoding unit and the (n + 2) th encoding unit may be written, or the image encoded by another encoding unit may be written. .

(7) In the above description, each coding unit performs coding according to the generation order of partial images, but it may be controlled in frame or field units, or some partial images may be processed collectively. Alternatively, some encoding units may be operated simultaneously. (8) Furthermore, in the configuration of the present embodiment, the number of adjacent coding units is 2
Although the configuration is such that one encoding bus is used for connection, one bus may be used in a time division manner.

As described above, according to the image coding apparatus of the present embodiment, even if the image size of the frame or field or the number of coding units to be processed in parallel changes, the data is already transferred to each coding unit. The signal amount of the encoded partial image of the frame or field does not change so much, and the number of encoding units does not have to be a complicated bus configuration (encoding unit bus circuit 20) between the plurality of encoding units. It is possible to realize an image coding apparatus that can be configured without being affected by the above, and can flexibly support various coding methods.

Further, by enlarging the size of one partial image (in particular, increasing the number of lines or the number of slices), the macroblocks to be coded by the respective coding units without complicating the coding unit bus circuit 20. With respect to, there is an effect that the range in which the difference can be taken can be increased.

Example 2. The image coding apparatus of the present embodiment processes in units of slices, and its configuration is the same as that of the first embodiment, as shown in FIG. However, regarding the functions performed by the image dividing unit 10 and the four encoding units,
There are the following differences.

The image dividing section 10 uses a slice (horizontal 192
The frame is divided every 0 pixels x 16 vertical pixels) for a total of 6
Create 8 partial images. That is, in the image coding apparatus according to the present embodiment, the image dividing unit 10 divides a frame into slices to divide a partial image into slices, and the load difference between the encoding units is set to 1 slice at the maximum, and the number of frames is 4. This is coded by a single coding unit. FIG. 4 shows how a frame is divided into 68 partial images each having 16 pixels in the vertical direction.

Further, the first coding unit 11 selects the first, fifth, ninth, thirteenth, seventeenth, twenty-first, twenty-fifth, and twenty-ninth out of a total of 68 partial images divided for each slice. , Third
, ..., 61st, 65th partial images are encoded. The second encoding unit 12 selects, from the 68 partial images,
2nd, 6th, 10th, 14th, 18th, 22nd, 2nd
The 6th, 30th, 34th, ..., 62nd, and 66th partial images are encoded. The third encoding unit 13 selects, among the 68 partial images, the third, seventh, eleventh, fifteenth, nineteenth,
The 23rd, 27th, 31st, ..., 63rd, and 67th partial images are encoded. Further, the fourth encoding unit 14 selects, among the 68 partial images, the fourth, eighth, twelfth, sixteenth,
20th, 24th, 28th, 32nd, ..., 64th, 68th
The second partial image is encoded.

Next, the operation of the coding apparatus of this embodiment will be described. The operation of this embodiment is basically the same as that of the first embodiment except that the processing is performed in slice units. FIG.
As can be seen from the above, when performing the parallel processing, the difference between the sums of the images encoded by the encoding units is 1 slice at maximum.

As described above, in the image coding apparatus according to the present embodiment, the partial image is sliced so that the load distribution among the coding units can be more equalized and the processing delay can be reduced. Also, the number of clocks required for processing one frame is reduced.

The image coding apparatus according to the present embodiment is not limited to the above-described specifications and configuration, and various modifications such as the following are possible. (1) In the above description, division into partial images is performed for an image in which one frame has horizontal 1920 pixels × vertical 1080 lines, but other sizes may be used. (2) In the above description, encoding was performed in frame units, but it may be performed in field units. (3) In the above description, assuming that N = 4, the four coding units 11 to 11
Although the encoding is performed by 14, the number is not limited to four, and any integer can be similarly configured.

(4) In the above description, the n-th frame memory used by the n-th encoding unit for encoding the m-th partial image is used in the m-th frame of the already encoded frame or field.
Although the 1st partial image, the mth partial image, and the m + 1th partial image are stored, a part of the m−1th partial image and the m + 1th partial image may be stored. (5) In the above description, the encoding unit bus circuit 20 can write the image signal encoded by the (n-1) th encoding unit, the nth encoding unit and the (n + 1) th encoding unit into the nth frame memory. However, the image signal encoded by the (n−2) th encoding unit and the (n + 2) th encoding unit may be written, or the image encoded by another encoding unit may be written. .

(6) In the above description, each coding unit performs coding according to the generation order of partial images, but it may be controlled in frame or field units, or some partial images may be processed collectively. May be Furthermore, some encoding units may be operated simultaneously. (7) Further, in the configuration of the present embodiment, the distance between adjacent coding units is 2
Although the configuration is such that one encoding bus is used for connection, one bus may be used in a time division manner.

Example 3. FIG. 5 shows a block diagram of an image decoding apparatus according to the third embodiment of the present invention. In the figure, the image decoding apparatus according to the present embodiment includes a code division unit 50, four decoding units (N = 4), four frame memories, an output bus 59, and a decoding unit bus circuit. 60 and an image synthesizing unit 65. In the figure, 31 is an image signal.

The four decoding units are the first decoding unit 51, the second decoding unit 52, the third decoding unit 53 and the fourth decoding unit 5.
The four frame memories are composed of a first frame memory 55, a second frame memory 56, a third frame memory 57 and a fourth frame memory 58. The decoding unit bus circuit 60 includes a first decoding bus 61, a second decoding bus 62, a third decoding bus 63, and a fourth decoding bus 64. Furthermore, the output bus 59
The decoded image signals are output from the four decoding units and are supplied to the image combining unit 65.

The code division unit 50 finds the beginning of the partial image in the received encoded image signal and divides it into encoded partial images.

The first decoding unit 51 includes the first, fifth, ninth, thirteenth, seventeenth, twenty-first, and thirty-first, out of the total of thirty-four encoded partial images output from the code division unit 50. The 25th, 29th and 33rd partial images are decoded. The second decoding unit 52 decodes the 2nd, 6th, 10th, 14th, 18th, 22nd, 26th, 30th and 34th partial images of the 34 partial images. To do. Third decoding unit 53
Is the third, seventh, eleventh, first of the 34 partial images.
The 5th, 19th, 23rd, 27th and 31st partial images are decoded. The fourth decoding unit 54 uses the fourth, eighth, twelfth, sixteenth, twentieth, and second of the thirty-four partial images.
The fourth, 28th and 32nd partial images are decoded.

The first frame memory 55 stores the signal already decoded in the decoding unit, and the signal necessary for decoding by the first decoding unit 51 is read from the first frame memory 55. . In the second frame memory 56,
The signal already decoded in the decoding unit is stored, and the signal necessary for decoding by the second decoding unit 52 is read from the second frame memory 56.

The signal already decoded in the decoding unit is stored in the third frame memory 57, and the signal necessary for decoding by the third decoding unit 53 is read from the third frame memory 57. Further, the fourth frame memory 58 stores the signal already decoded in the decoding section, and the signal necessary for decoding in the fourth decoding section 54 is read out.

The image synthesizing unit 65 converts the image signals decoded by the four decoding units, that is, the first, second, third and fourth decoding units 51, 52, 53 and 24 into frame signals (images). Signal 31).

In the decoding section bus circuit 60, the first decoding bus 61 includes the first, second and fourth decoding sections 51, 52.
And the partial image signal decoded in 54 is written in the first frame memory 55. The second decoding bus 62 has the first and second
The partial images decoded by the second and third decoding units 51, 52 and 53 are written in the second frame memory 56. The third decoding bus 63 is connected to the second, third and fourth decoding units 5
The partial images decoded at 2, 53 and 54 are written in the third frame memory 28. Further, the fourth decoding bus 64 writes the partial images decoded by the first, third and fourth decoding units 51, 53 and 54 into the fourth frame memory 58.

Next, the operation of the decoding apparatus of this embodiment will be described. The code division unit 50 uses the horizontal 19 as an effective signal.
20 pixels × 1080 vertical lines, one frame of the encoded frame signal is 1920 pixels × horizontal 3
It is divided into coded signals of a total of 34 partial images, which is 2 lines. At this time, the encoded signal in charge of the 34th partial image includes an encoded signal obtained by encoding an invalid line signal for 8 lines composed of invalid data.

Further, the code division unit 50 decodes the coded signal of the first partial image into the first decoding unit 51 and the coded signal of the second partial image into the second decoding in the order of generation of the coded signal of the partial image. In the unit 52, the encoded signal of the third partial image is supplied to the third decoding unit 53.
Then, the encoded signal of the fourth partial image is input to the fourth decoding unit 54,
The encoded signal of the fifth partial image is sent to the first decoding unit 51 and
The coded signal of the partial image is sent to the second decoding unit 52, the coded signal of the seventh partial image is sent to the third decoding unit 53, the coded signal of the eighth partial image is sent to the fourth decoding unit 54, and The encoded signals of the nine partial images are sent to the first decoding unit 51, and so on.
The data is cyclically output to the second, third and fourth decoding units 51 to 54.

The first decoding unit 51 divides the coded signal of the first partial image input from the code dividing unit 50 into macroblocks, and reads out from the first frame memory 55 for each macroblock. The sum of the decoded frame and the macroblock is taken. Then, the decoded signal is output to the image synthesis unit 65.

On the other hand, the decoded first partial image is stored in the first, second and fourth frame memories 55, 56 and 58 by the decoding unit bus circuit 60. The same applies to the second, third and fourth decoding units 52, 53 and 54. In the first frame memory 55, the macroblock of the already decoded frame that should be summed with the macroblock to be decoded by the first decoding unit 51 is sent to the first decoding unit 51 according to an instruction from the first decoding unit 51. Output. The same applies to the second, third and fourth frame memories 56, 57 and 58.

In the decoding section bus circuit 60, the first, second and fourth decoding sections 51, 5 are stored in the first frame memory 55.
The partial images decoded in 2, 54 are stored in the second frame memory 56 in the first, second and third decoding units 51, 52 and 5 respectively.
The partial image decoded in 3 is stored in the third frame memory 57, the partial image decoded in the second, third and fourth decoding units 52, 53 and 54 is stored in the fourth frame memory 58, and the third image is stored in the third frame memory 57. The partial images decoded by the fourth and first decoding units 53, 54 and 51 are stored respectively.

The image decoding apparatus according to the present embodiment is not limited to the above specifications and configuration, and various modifications as described below are conceivable. (1) In the above description, division into partial images is performed for an image in which one frame has horizontal 1920 pixels × vertical 1080 lines, but other sizes may be used. (2) In the above description, decoding was performed in frame units,
You may also go field by field. (3) In the above description, the partial image is divided every vertical 32 lines, but it may be divided with more lines. (4) In the above description, N = 4 and four decoding units 51 to
Although the encoding is performed by 54, the number is not limited to four, and any integer can be similarly configured.

(5) In the above description, the n-th frame memory used by the n-th decoding unit for decoding the m-th partial image is stored in the m-th frame of the already decoded frame or field.
Although the 1st partial image, the mth partial image, and the m + 1th partial image are saved, a part of the m−1th partial image and the m + 1th partial image may be saved. (6) In the above description, the decoding unit bus circuit 60 can write the image signal decoded by the (n−1) th decoding unit, the nth decoding unit and the (n + 1) th decoding unit into the nth frame memory. However, the image signal decoded by the (n−2) th decoding unit and the (n + 2) th decoding unit may be written, or the image decoded by another decoding unit may be written. .

(7) In the above description, each decoding unit executes decoding according to the generation order of partial images, but it may be controlled in frame or field units, or some partial images may be processed collectively. Alternatively, several decoding units may be operated at the same time. (8) Further, in the configuration of this embodiment, the number of adjacent decoding units is reduced to 2
The configuration is such that one decoding bus is used for connection, but one bus may be used in a time division manner.

As described above, according to the image decoding apparatus of the present embodiment, even if the image size of the frame or field or the number of decoding units to be processed in parallel changes, the image is already transferred to each decoding unit. The signal amount of the decoded partial image of the frame or field does not change so much, and the number of decoding units does not have to be a complicated bus structure (decoding unit bus circuit 60) between the plurality of decoding units. It is possible to realize an image coding apparatus that can be configured without being affected by the above and can flexibly support various decoding methods.

Further, by increasing the size of one partial image (in particular, increasing the number of lines or the number of slices), the decoding unit bus circuit 60 is not complicated, and the macroblocks to be decoded by each decoding unit. There is an effect that it is possible to increase the area where the sum can be obtained.

Example 4. The image decoding apparatus of the present embodiment processes in units of slices, and its configuration is the same as that of the third embodiment, as shown in FIG. However, regarding the functions performed by the code division unit 50 and the four decoding units,
There are the following differences.

The code division unit 50 divides the coded image signal into coded signals of partial images which are slices (horizontal 1920 pixels × vertical 16 pixels) to generate coded signals of 68 partial images in total. . That is, in the image decoding apparatus according to the present embodiment, the code division unit 50 divides the frame signal into encoded signals of the encoded partial image for each slice, and the partial image is a slice. The frame is decoded by the four decoding units with the load difference being 1 slice at maximum.

Further, the first decoding unit 51, out of a total of 68 partial images divided for each slice, the first, fifth, ninth, thirteenth, seventeenth, twenty-first, twenty-fifth and twenty-ninth portions. , Third
Decoding of the 3rd, ..., 61st, and 65th partial images is performed. The second decoding unit 52, among the 68 partial images,
2nd, 6th, 10th, 14th, 18th, 22nd, 2nd
Decoding of the sixth, thirty-fourth, ..., The 62nd, and the 66th partial images is performed. The third decoding unit 53, among the 68 partial images, the third, seventh, eleventh, fifteenth, nineteenth,
The 23rd, 27th, 31st, ..., 63rd, and 67th partial images are decoded. Further, the fourth decoding unit 54, among the 68 partial images, the fourth, eighth, twelfth, sixteenth,
20th, 24th, 28th, 32nd, ..., 64th, 68th
Decode the th partial image.

Next, the operation of the decoding apparatus of this embodiment will be described. The operation of this embodiment is basically the same as that of the third embodiment except that the processing is performed in slice units. FIG.
As can be seen from the above, when performing the parallel processing, the maximum difference between the sums of the images to be decoded by each decoding unit is 1 slice.

As described above, in the image decoding apparatus according to the present embodiment, the partial image is sliced, so that the load distribution among the decoding units can be more equalized and the processing delay can be reduced. Also, the number of clocks required for processing one frame is reduced.

The image decoding apparatus according to the present embodiment is not limited to the above specifications and configuration, and various modifications as described below are conceivable. (1) In the above description, division into partial images is performed for an image in which one frame has horizontal 1920 pixels × vertical 1080 lines, but other sizes may be used. (2) In the above description, decoding is performed in frame units, but it may be performed in field units. (3) In the above description, N = 4 and four decoding units 51 to
Although the decoding is performed by 54, the number is not limited to four, and any integer can be similarly configured.

(4) In the above description, the n-th frame memory used by the n-th decoding section for decoding the m-th partial image is stored in the m-th frame of the already decoded frame or field.
Although the 1st partial image, the mth partial image, and the m + 1th partial image are stored, a part of the m−1th partial image and the m + 1th partial image may be stored. (5) In the above description, the decoding unit bus circuit 60 can write the image signal encoded by the n−1 th decoding unit, the n th decoding unit and the n + 1 th decoding unit into the n th frame memory. However, the image signal decoded by the (n−2) th decoding unit and the (n + 2) th decoding unit may be written, or the image decoded by another decoding unit may be written. .

(6) In the above description, each decoding unit executes decoding according to the generation order of partial images, but it may be controlled in frame or field units, or some partial images may be processed collectively. May be Furthermore, some decoding units may be operated at the same time. (7) Further, in the configuration of this embodiment, the number of adjacent decoding units is 2
The configuration is such that one decoding bus is used for connection, but one bus may be used in a time division manner.

Example 5. The configuration of the image coding apparatus according to the present embodiment is the same as that of the first and second embodiments, as shown in FIG. Note that the following discussion can be applied to the image decoding apparatus, and the configuration thereof is the configuration shown in FIG. 5 similarly to the configurations of the third and fourth embodiments.

Generally, in the case of processing a signal in real time, if the processing time required by one processing device is N times the minimum period of the input signal, N or more processing devices are operated in parallel. As a result, apparent real-time processing can be realized. If this is applied to the image coding apparatus of the second embodiment that codes frame signals in parallel on a frame-by-frame basis, the coding of one slice of a partial image (minimum period 16 line time of input signal) is 16 × N
Since it will be completed within the line time, N encoding devices will be processed in parallel.

By the way, the image coding apparatus of the second embodiment is
The encoding of the slice that is the first partial image for each frame is
Of the N encoding units that operate in parallel, the first encoding unit 11 must be used. For that purpose, from the start of processing of the slice that is the 65th partial image to be processed last by the first encoding unit 11 in the immediately preceding frame, until the slice that is the first partial image of the next frame is input, 16x
It is only necessary to be separated by N line cycle time or more.

This can be expressed by the following equation, where N is the number of coding units and L is an arbitrary natural number. (Number of effective lines in one frame) ≦ L × 16 × N ≦ (total number of lines in one frame, including vertical blanking interval) (4)

That is, if the number N of coding units is a number satisfying the expression (4) regarding the frame, all the slice cycle time can be effectively used for coding, and the slice cycle time does not have to be changed. Further, since the time in which the effective line does not exist, which is included in the frame cycle time, can be effectively used, as compared with the image coding apparatus including the number of coding units that do not satisfy the formula (4), An image can be efficiently coded in frame units.

The equation (4) can be applied to the image decoding apparatus of the fourth embodiment. In this case, N is the number of decoding units, which makes the image more efficient in frame units. It is possible to realize an image decoding device capable of decoding

Example 6. The configuration of the image coding apparatus according to the present embodiment is the same as that of the first and second embodiments, as shown in FIG. Note that the following discussion can be applied to the image decoding apparatus, and the configuration thereof is the configuration shown in FIG. 5 similarly to the configurations of the third and fourth embodiments.

Generally, in the case of processing a signal in real time, if the processing time required by one processing device is N times the minimum period of the input signal, N or more processing devices are operated in parallel. As a result, apparent real-time processing can be realized. If this is applied to the image coding apparatus according to the second embodiment, in which frame signals are switched in frame units or field units and coded in parallel,
Since the encoding of a partial image of one slice (minimum period of 16 lines of input signal time) is completed within 16 × N line time, N encoding devices are processed in parallel.

By the way, the image coding apparatus of the second embodiment is
The encoding of the slice, which is the first partial image for each frame or each field, must be performed by the first encoding unit 11 out of N encoding units operating in parallel. To this end, in the case of processing on a frame-by-frame basis, in the immediately preceding frame, the first encoding unit 11 starts processing the slice that is the 65th partial image, and then the first portion of the next frame. 16 until an image slice is input
It suffices if they are separated by more than × N line cycle time.

Further, in the case of processing on a field-by-field basis, since the processing of the slice which is the 33rd partial image to be processed last by the first encoding unit 11 is started in the immediately preceding field, the first field of the next field is processed. It is only necessary to be separated by 16 × N line cycle time or more until a slice that is a partial image is input.

This is expressed by the following equation, where N is the number of coding units and L is an arbitrary natural number. (Number of effective lines in one frame) ≦ 2 × L × 16 × N ≦ (total number of lines in one frame, including vertical blanking interval) (5)

That is, if the number N of coding units is the number satisfying the expression (5) regarding the frame, all the slice cycle time can be effectively used for coding, and the slice cycle time does not have to be changed. In addition, the time when there is no effective line included in the frame cycle time or the field cycle time can be effectively used, so that (5)
It is possible to more efficiently encode an image in both frame units or field units, as compared with an image encoding device including a number of encoding units that do not satisfy the formula.

The expression (5) can be applied to the image decoding apparatus of the fourth embodiment, and in this case, N is the number of decoding units, which makes it more efficient to use the frame unit or the field unit. It is possible to realize an image decoding device that can decode an image in both units.

Example 7. The configuration of the image coding apparatus according to the present embodiment is the same as that of the first and second embodiments, as shown in FIG. Note that the following discussion can be applied to the image decoding apparatus, and the configuration thereof is the configuration shown in FIG. 5 similarly to the configurations of the third and fourth embodiments.

Generally, in the case of processing a signal in real time, if the processing time required by one processing device is N times the minimum period of the input signal, N or more processing devices are operated in parallel. As a result, apparent real-time processing can be realized. If this is applied to the image coding apparatus of the second embodiment which codes field signals in parallel on a field-by-field basis, the coding of one slice of a partial image (minimum period 16 line time of input signal) is 16 × N. Since the process is completed within the line time, the N encoders are processed in parallel.

By the way, the image coding apparatus of the second embodiment is
The encoding of the slice that is the first partial image for each field must be performed by the first encoding unit 11 among the N encoding units that operate in parallel. To this end, in the immediately preceding field, the 33rd field that is processed last by the first encoding unit 11 is used.
It is only necessary to be separated by 16 × N line cycle time or more from the start of the processing of the slice which is the partial image until the slice which is the first partial image of the next field is input.

This can be expressed by the following equation, where N is the number of coding units and L is an arbitrary natural number. (Number of effective lines in one field) ≦ L × 16 × N ≦ (total number of lines in one field, including vertical blanking interval) (6)

That is, if the number N of coding sections is the number satisfying the expression (6) regarding the field, all the slice cycle time can be effectively used for coding, and the slice cycle time does not have to be changed. Further, since the time in which the effective line included in the field cycle time does not exist can be effectively used, compared with the image coding apparatus including the number of coding units that do not satisfy the expression (6), Images can be efficiently coded in field units.

The expression (6) can be applied to the image decoding apparatus of the fourth embodiment. In this case, N is the number of decoding units, which makes the image more efficient and field-wise. It is possible to realize an image decoding device capable of decoding

Example 8. The configuration of the image coding apparatus according to the present embodiment is the same as that of the first and second embodiments, as shown in FIG. Note that the following discussion can be applied to the image decoding apparatus, and the configuration thereof is the configuration shown in FIG. 5 similarly to the configurations of the third and fourth embodiments.

Generally, the maximum clock frequency when the image coding apparatus inputs the image signal (in the case of the image decoding apparatus, outputs the image signal) is the sampling frequency.
Therefore, if the image coding apparatus can be operated at this sampling frequency, parallel processing is often unnecessary. Conversely, if it is not possible to operate at the sample frequency, parallel processing is often required. Therefore, if the upper limit of the operation clock frequency inside the image encoding device is (sampling frequency) / N or less, the N encoding units are operated in parallel.

Therefore, the clock frequency given by the above equation (3) is often selected as the operation clock frequency as the lowest clock frequency of the image coding apparatus which operates in parallel in N coding units. Therefore, with respect to the image coding devices of the second, fifth, sixth and seventh embodiments,
By applying the equation (3), it is possible to select an appropriate number of encoding units of the encoding device that performs parallel processing and the minimum clock frequency at that time. As a result, the necessary and sufficient operation clock frequency can be used.

Further, by applying the expression (3) to the image decoding apparatuses of the fourth, fifth, sixth and seventh embodiments, the appropriate decoding of the decoding apparatus for parallel processing can be performed. The number of units and the lowest clock frequency at that time can be selected, and an image decoding apparatus that can use a necessary and sufficient operation clock frequency can be realized.

[0122]

As described above, according to the image coding apparatus of the first feature of the present invention, the n-th coding unit always codes the m-th partial image at the same position for each frame or each field. And the mth partial image of the frame or field already encoded by the encoder bus circuit in the nth frame memory used by the nth encoder, and the m-1th image.
Since it is decided to store at least a part of the partial image and a part of the m + 1th partial image, the n-th encoding unit encodes the current frame or field and the already-encoded code within at least the range of the stored partial image. It is possible to obtain the difference from the encoded frame or field, and it is appropriate for the image included in the m-th partial image from the already-encoded frame or field even if it is the boundary with the m-1th partial image. It is possible to efficiently select a predictive image and efficiently encode the image. As a result, the bus configuration between a plurality of encoding units that operate in parallel can be reduced to a unit number of processors without a complicated configuration. It is possible to provide an image encoding device that can be configured without being affected and can flexibly support various encoding methods.

Further, according to the image coding apparatus of the second feature of the present invention, the image dividing unit divides the frame or field into slices and divides the partial image into slices, thereby performing each encoding. Since the difference in the load of each unit is set to 1 slice at the maximum and a plurality of (N) encoding units are used to encode frames or fields, the total number of clocks required to process one frame or one field can be reduced. In addition, the processing delay time can be further reduced.

Further, according to the image coding apparatus of the third feature of the present invention, the number N of coding sections is set to the number satisfying the expression (1) for the above frame, so that all the slice cycle times are effective. It can be used for encoding, the slice cycle time does not need to be changed, and the time when there is no effective line included in the frame cycle time can be effectively used. An image can be encoded more efficiently in a frame unit as compared with an image encoding device including an encoding unit.

Further, according to the image coding apparatus of the third feature of the present invention, since the number N of coding units is set to the number satisfying the expression (1) regarding the above field, all the slice cycle times are made effective. It can be used for encoding, the slice cycle time does not have to be changed, and the time when there is no effective line included in the field cycle time can be effectively used. An image can be encoded more efficiently in a field unit as compared with an image encoding device including an encoding unit.

According to the image coding apparatus of the fourth feature of the present invention, the number N of coding units is set to the number satisfying the expression (2) regarding the frame, so that all the slice cycle times are coded effectively. The slice cycle time does not have to be changed, and the time when there is no effective line included in the frame cycle time or the field cycle time can be effectively used. It is possible to more efficiently encode an image in both a frame unit or a field unit, as compared with an image encoding device provided with an indefinite number of encoding units.

Further, according to the image coding apparatus of the fifth feature of the present invention, the operation clock generated in the clock generator is set to the clock frequency satisfying the above expression (3), and therefore the necessary and sufficient minimum clock frequency is obtained. Can be selected.

Further, according to the image decoding apparatus of the first feature of the present invention, the n-th coding section surely codes the m-th partial image coded at the same position for each frame signal or each field signal. The decoded signal is decoded, and the mth partial image of the frame or field already decoded by the decoding unit bus circuit and the m-1th partial image are written in the nth frame memory used by the nth decoding unit. Since at least the part and the part of the (m + 1) th partial image are stored, the n-th decoding unit includes the current frame or field and the already decoded frame at least within the range of the stored partial image. Or you can take the sum with the field,
For an image included in the mth partial image, even if it is a boundary with the m-1th partial image, an appropriate predicted image is selected from the already decoded frame or field, and the image is efficiently decoded. As a result, the bus configuration between the plurality of decoding units operating in parallel can be configured without a complicated configuration and without being affected by the number of unit processors, and can be flexibly adapted to various decoding methods. It is possible to provide a compatible image decoding device.

Further, according to the image decoding apparatus of the second feature of the present invention, the code division unit encodes the encoded frame signal or field signal into encoded signals of partial images encoded for each slice. By dividing the image into slices and dividing the partial image into slices, the load difference of each decoding unit is set to 1 slice at the maximum, and the frame or field is decoded by a plurality (N) of decoding units. The total number of clocks required for processing one frame or one field can be reduced, and the processing delay time can be further reduced.

Further, according to the image decoding apparatus of the third feature of the present invention, since the number N of decoding units is set to the number satisfying the expression (1) regarding the above frame, all the slice cycle times are made effective. It can be used for decoding, the slice cycle time does not need to be changed, and the time when there is no effective line included in the frame cycle time can be effectively used. As compared with the image decoding device including the decoding unit, the image can be decoded more efficiently in frame units.

Further, according to the image decoding apparatus of the third feature of the present invention, the number N of decoding units is set to the number satisfying the expression (1) regarding the above field, so that all the slice cycle times are effective. It can be used for decoding, the slice cycle time does not have to be changed, and the time when there is no effective line included in the field cycle time can be effectively used. As compared with the image decoding device including the decoding unit, the image can be decoded more efficiently in the field unit.

Further, according to the image decoding apparatus of the fourth feature of the present invention, the number N of decoding units is set to the number satisfying the expression (2) regarding the frame, so that all the slice cycle times are effectively decoded. The slice cycle time does not have to be changed, and the time when there is no effective line included in the frame cycle time or the field cycle time can be effectively used. It is possible to more efficiently decode an image in both the frame unit or the field unit as compared with an image decoding apparatus including an undecoded number of decoding units.

Further, according to the image decoding apparatus of the fifth feature of the present invention, the operation clock generated in the clock generator is set to the clock frequency satisfying the above expression (3). Therefore, the necessary and sufficient minimum clock frequency is obtained. Can be selected.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an image encoding device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram in which a frame or field is divided into 34 partial images for every 32 lines.

FIG. 3 is a timing chart of the encoding operation in the four encoding units of the first embodiment.

FIG. 4 is an explanatory diagram in which a frame or field is divided into 68 partial images each having 16 vertical pixels.

FIG. 5 is a configuration diagram of an image decoding apparatus according to a third embodiment of the present invention.

FIG. 6 is a block diagram of a conventional moving image coding apparatus.

FIG. 7 is an explanatory diagram showing an example of division of a conventional frame or field.

FIG. 8 is a timing chart of a moving image encoding device of a conventional example.

[Fig. 9] Fig. 9 is an explanatory diagram of a motion compensation interframe coding method.

[Explanation of symbols]

10 image division unit, 11 first encoding unit, 12 second encoding unit, 13 third encoding unit, 14 fourth encoding unit, 1
5 first frame memory, 16 second frame memory,
17 Third Frame Memory, 18 Fourth Frame Memory, 19 Output Bus, 20 Coding Section Bus Circuit, 21
First coding bus, 22 Second coding bus, 23 Third coding bus, 24 Fourth coding bus, 31 Image signal, 3
2 coded signal, 50 code division unit, 51 first decoding unit, 52 second decoding unit, 53 third decoding unit, 54
4th decoding part, 55 1st frame memory, 56 2nd
Frame memory, 57 Third frame memory, 58 Fourth frame memory, 59 Output bus, 60 Decoding unit bus circuit, 61 First decoding bus, 62 Second decoding bus, 63 Third decoding bus, 64 Fourth Decoding bus, 6
5 image composition unit, 101 input bus, 102 feedback bus, 103 (conventional example) output bus, 104 first unit processor, 105 second unit processor, 10
6 Third unit processor, 107 capture unit, 108 processing unit, 109 output unit.

Claims (10)

[Claims] 1. A variable-length code is obtained by quantizing a differential signal between a signal obtained by decoding an already encoded frame or field, which is an image signal blocked on a frame or field, and a current frame signal or field signal. In the image encoding device for encoding, the frame or field is converted from the first partial image to the Mth
An image dividing unit that divides into M partial images up to the partial image (M is an arbitrary positive integer), and a first encoding unit for the M partial images from the first partial image to the Mth partial image. From the Nth encoding unit, the Nth encoding units circulate and correspond to each other, and operate in parallel with each other to encode (N is N <M
Corresponding to the first to Nth encoding units, respectively.
N frame memories that store signals obtained by decoding the already-encoded frames or fields in each encoder, and the already-encoded frames by the n-th encoder (n = 1 to N). A m-th partial image (m = 1 to M) which is a field decoded signal, and at least the n-th
The m-1 th signal which is a signal obtained by decoding the already encoded frame or field encoded by the 1 encoding unit.
A part of the partial image and at least a part of the m + 1th partial image, which is a signal obtained by decoding the already encoded frame or field encoded by the n + 1th encoding unit, are stored in the nth frame memory. An image encoding apparatus, comprising: an encoding unit bus circuit for writing. 2. The image coding apparatus according to claim 1, wherein the image dividing unit divides the frame or field for each slice. 3. When L is an arbitrary natural number, said number N
The image coding apparatus according to claim 2, wherein the following expression is satisfied. (Number of effective lines in one frame or field) ≦ L ×
16 × N ≦ (total number of lines in one frame or field; including vertical blanking interval) 4. When L is an arbitrary natural number, said number N
The image coding apparatus according to claim 2, wherein the following expression is satisfied. (Number of effective lines in one frame) ≦ 2 × L × 16 × N ≦
(Total number of lines per frame; including vertical blanking interval) 5. The image coding apparatus according to claim 2, further comprising a clock generator for generating an operation clock, wherein the frequency of the operation clock and the number N satisfy the following equation. . (Clock frequency) = (Sampling frequency) × (3 or 2 or 1.5) / N 6. A differential signal between a frame signal or field signal, which is an image signal blocked on a frame or field and already decoded, and a current frame signal or field signal is quantized and further variable length coded. In the image decoding device for decoding the image signal, the variable-length coded frame signal or field signal from the first partial image coded signal to the M-th partial image coded signal (M is an arbitrary positive number) is used. An integer) partial image coded signal, and a first decoding unit for M partial image coded signals from the first partial image coded signal to the Mth partial image coded signal. From N to N decoding units that cyclically respond to each other and operate in parallel to perform decoding (N is a positive integer satisfying N <M), and the first to Nth decoding units. Decryption unit Corresponding to
N frame memories for storing frame signals or field signals already decoded in each of the decoding units, and frames or fields decoded by the n-th decoding unit (n = 1 to N). m partial image (m = 1 to 1
M), at least a part of the (m-1) th partial image that is a frame or field decoded by the (n-1) th decoding unit, and at least a frame or field that is decoded by the (n + 1) th decoding unit. A decoding unit bus circuit for writing a part of a certain m + 1 partial image to the n-th frame memory, and image combination for combining each partial image decoded by the N decoding units into a frame or field. Department,
An image decoding apparatus comprising: 7. The image according to claim 6, wherein the code division unit divides the coded frame signal or field signal into coded signals of coded partial images for each slice. Decoding device. 8. The number N, where L is an arbitrary natural number.
The image decoding apparatus according to claim 7, characterized in that (Number of effective lines in one frame or field) ≦ L ×
16 × N ≦ (total number of lines in one frame or field; including vertical blanking interval) 9. When L is an arbitrary natural number, said number N
The image decoding apparatus according to claim 7, characterized in that (Number of effective lines in one frame) ≦ 2 × L × 16 × N ≦
(Total number of lines per frame; including vertical blanking interval) 10. The image decoding apparatus according to claim 7, further comprising a clock generator that generates an operation clock, and the frequency of the operation clock and the number N satisfy the following equation. . (Clock frequency) = (Sampling frequency) × (3 or 2 or 1.5) / N