JPS6383875A - Picture processor - Google Patents

Abstract

PURPOSE:To apply the bit boundary processing to various memory systems having different length of a single word by using plural selectors to select the input data. CONSTITUTION:A barrel shifter 17 shifts the 2n-bit data received from selectors 15 and 14 by optional bits to extract and deliver the data as the n-bit data. The selector 15 selects the output data on a register 12 and at the same time the selector 14 selects the data on a bus line 11 under the control of the control signal. Thus this circuit can perform the bit boundary processing in response to the number of bits of the picture data received from a memory and transferred to the line 11. When the selector 14 has a control job to select the picture data transferred to a bus line 16, the bit boundary processing is possible with an optional multiple of the bit number (n) of the input picture data, i.e., in the units 2n, 3n....

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an image processing apparatus that performs image processing of images, and particularly relates to an image processing apparatus that performs bitmap image processing.

(Prior Art) Image processing devices that display or process image data bit by bit are becoming popular.

Conventionally, such image processing has often been performed on a bit-by-bit basis, but in recent years, with the aim of increasing speed, processing has been increasingly performed on a word-by-word basis.

In order to perform such image processing in units of words, a so-called bit boundary access function is required to extract image data in units of words from arbitrary bit positions.

Conventionally, a circuit as shown in FIG. 6 has been used to realize this bit boundary access. This circuit consists of a register 101 that latches multiple bits of input data 100, and the output data of this register 101.
102 and a barrel shifter 103 which receives input data 100.

The operation of this circuit will be briefly explained. It is now assumed that image data is stored in a memory (not shown) in a state as shown in FIG. Here, A, B, and C are data in word units on memory, D is data that exists across A and B and should be extracted by bit boundary access, and E is data that exists between A and B. This is data that exists across C and should be extracted by bit boundary access.

FIG. 8 is a timing chart showing the operation timing of the circuit shown in FIG. 6, in which 111 is a basic clock signal;
112 is input data, 113 is output data of the register 101, and 114 is output data of the barrel shifter 103. Since memory contents A and B are input in parallel to the barrel shifter 103 at the second timing of the clock signal 111, D can be extracted. Furthermore, at the third timing of the clock signal 111, the memory contents B and C are input in parallel to the barrel shifter 103, so that E can be extracted.

In this manner, the conventional circuit shown in FIG. 6 can perform bit boundary access while sequentially accessing the memory.

By the way, in systems that handle images with multiple colors or shading, multiple bits are generally assigned to one pixel to configure multiple color brains. In this case, as many circuits as there are brains are required to perform bit boundary access as shown in Figure 6, and these multiple circuits operate in parallel when performing bit boundary access. .

With the recent development of integrated circuit technology, integrated circuits that can perform bit boundary processing in parallel for image memory systems having multiple brains are also appearing, and this is expected to greatly contribute to reducing system costs.

However, the conventional circuit for realizing bit boundary processing lacks flexibility, which significantly limits the configuration of the memory system. For example, a system that uses 16 bits per word and processes 4 planes (4 branes) simultaneously can be used with other memory configurations, such as 8 bits x 8 planes, 32 bits x 2 planes, 64 bits x 1 plane, etc. It is impossible to try to achieve this. This is because the configuration of barrel shifter 103 is fixed depending on the number of bits in one word of the memory system.

(Problems to be Solved by the Invention) As described above, the conventional method has a drawback in that bit boundary processing cannot be performed using various memory systems having different word lengths.

The present invention has been made in consideration of the above-mentioned circumstances, and its purpose is to provide an image processing device that can perform bit boundary processing for various memory systems with different word lengths. It's about doing.

[Structure of the Invention] (Means for Solving the Problems) An image processing device of the present invention includes a first image data bus line to which image data is transferred, and a first image data bus line connected to the first image data bus line, a register for storing image data, first and second selectors to which the output line of the register and the first image data bus line are respectively connected, a second image data bus line, and the second image data bus line; A third selector to which the data bus line and the first image data bus line are connected is connected to the respective output lines of the second and third selectors, and outputs the output data of the second and third selectors to arbitrary bits. The image processing section includes at least one image processing section configured with a data shift means for shifting the data by a number of times and outputting the data.

(Function) In the image processing device of the present invention, the output data of the second selector is used as the output data from the register, and the output data of the third selector is used as the input data to the register. Width word length in bits
Boundary processing can be performed.

On the other hand, by selecting external input data as the output of the third selector, bit boundary processing can be performed in units of arbitrary multiples of the bus width of the input data to the register.

(Example) The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one image processing section used in an image processing apparatus according to the present invention. In the figure, 11 is a first pass line to which 1 word, n-bit image data is transferred. The image data transferred to this pass line 11 is stored in a register 12 having an n-bit configuration.
The signal is supplied in parallel to one input terminal of each of the first selector 13 and the third selector 14 and the other input terminal of the second selector 15 .

The output data of the register 12 is sent to the first selector 1.
3 and one input terminal of the second selector 15 in parallel. Further, image data to be transferred to the second pass line 16 is supplied to the other input terminal of the third selector 14 .

The first, second, and third selectors 13, 15, and 14 each selectively output data at one or the other input terminal based on a control signal. Then, the selection output data of the first selector 13 is output to the outside, and the selection output data of the second and third selectors 15 and 14 are supplied to the barrel shifter 17 in parallel. This barrel shifter 17 is the second
Then, the 2n-bit data from the third selector 15.14 is shifted by arbitrary bits, extracted as n-bit data, and output.

In the image processing section configured in this way, the second
This circuit is controlled by a control signal so that the selector 15 selects the output data of the register 12, and by controlling the third selector 14 to select the data of the first pass line 11 using a control signal. has a configuration equivalent to the conventional circuit shown in FIG. 6 above. That is, pass line 1
It is possible to perform bit boundary processing corresponding to the number of bits of image data from the memory to be transferred.

On the other hand, if the third selector 14 is controlled by the control signal to select the image data to be transferred to the second pass line 16, the third selector 14 selects the image data to be transferred to the second pass line 16. Bit boundary processing can be performed in units of... This will be explained below.

Figure 2 uses two image processing units shown in Figure 1 above,
FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention in which bit boundary processing can be performed on both a 1-word, 8-bit x 2-screen memory system and a 1-word, 16-bit x 1-screen memory system; . In the figure, 20 and 30
are respectively similar to those shown in FIG. 1 above.
The image processing section includes a pass line, a register, first, second, and third selectors, and a barrel shifter. and,
- In the image processing unit 20, the alphabet A is added to the end of the code for the parts corresponding to those in FIG.
is attached. In this case, the number n of bits of image data transferred on the first and second pass lines 11.16 is 8, and the register 12 and the first, second, and third selectors 13.15.14, respectively. is also composed of 8 bits,
The barrel shifter 17 has a 16-bit configuration, which is twice that number.

Here, the first selector 13 in one image processing section 20
The output data of A is supplied to the other input terminal of the third selector 143 via the second pass line 18B in the other image processing section 30, and
The output data of the selector 13B is sent to one of the image processing units 2
The signal is supplied to the other input end of the third selector 14A via the second pass line 16A within 0.

Next, the operation of the apparatus configured as described above will be explained.

First, in the image processing units 20.30 of one side and the other side, the second selectors 15A, 15B are connected to the registers 12A11.
The third selector 14A114B is controlled by the control signal to select the data of the first pass lines 11A and 11B, respectively. At this time, each of the one and the other image processing sections 20 and 30 has a configuration equivalent to the conventional circuit shown in FIG. 6.

That is, in this case, each pass line 11A
, 11B, bit boundary processing corresponding to the number of bits of image data transferred from the memory, that is, 8 bits, can be performed in parallel.

Here, FIG. 3(a) shows the arrangement state of data on the memory subjected to bit boundary processing in one image processing section 20, and FIG. - Indicates the arrangement of data in memory that is subject to boundary processing. That is, in FIGS. 3(a) and 3(b), Ax and Ay.

AZ, . . . are one word data of one brane having an 8-bit configuration, and Bx, By, Bz, .

Next, as shown in FIG. 4(a), one word contains 8-bit data Ap and Bp, Aq and Bq, . . .
The operation when performing bit boundary processing for a memory system of 1 word, 16 bits x 1 plane, which is constructed from the following, will be explained.

First, in the first cycle, the word data Aρ and Bp on the memory shown in FIG. The data Bp is stored in the first image processing unit 30 in the other image processing unit 30.
are output to the pass lines 11B, respectively.

In the second cycle, these data are stored in registers 12A, 1
2B and the next word data Aq on the memory shown in FIG. 4(a).

BQ is read out in parallel, pass lines 11A, 11B
are output respectively. At this time, one image processing section 2
0, the first selector 13A selects the first pass line 11
The second selector 15A transfers the data on A to the register 12.
Control signals are used to select the output data of A and the third selector 14A select the data of the second pass line 16A, respectively. Further, in the other image processing section 30, the first selector 133 receives the output data of the register 123, the second selector 153 receives the output data of the register 12B, and the third selector 143 receives the output data of the register 12B.
Each control signal is used to select the data of each. As a result, in the image processing section 20, the barrel shifter 17
Since 8-bit data AD and Bp are supplied to A, the barrel shifter 17A can extract 8-bit data Cp spanning both data Ap%Bp as shown in FIG. 4(b). can.

At the same time, the image processing unit 30 operates the barrel shifter 17B.
Since the 8-bit data Aq and Bp are supplied to the 8-bit data Aq and Bp, the barrel shifter 17B can extract the 8-bit data Cq'Ir spanning both the data AQ and Bp, as shown in FIG. 4(b). can.

In this way, bit boundary processing for 16-bit data can be executed within the second cycle period. Hereafter, by repeating the same operation, 1
Bit boundary processing for each word of 16-bit data is performed successively.

If the amount to be shifted exceeds 8 bits, by further performing a word-by-word shift after the bit boundary shift, processing of an arbitrary bit shift amount becomes possible.

In addition, in the above embodiment, this invention is applied to one word, 8 bits×
We have described a memory system that can perform bit boundary processing for both 2-screen and 1-word, 16-bit x 1-screen memory systems. , 1-word n-bit configuration, and 19-word (nXm) bit configuration.

Further, by appropriately inserting selectors between the image processing units, bit boundary processing can be performed for three types of memory systems having different word lengths.

FIG. 5 is a block diagram showing the configuration of an applied example of the present invention. In this application example device, four image processing sections 40, 50, 6o and 70 each independently performing bit boundary processing on, for example, 8-bit data are provided, and these are connected in series, and the image processing sections 60 and 50 are connected in series. Between the output data of the first selector 13 (not shown in FIG. 5) in the image processing section 60 and the output data of the first selector 13 (also not shown) in the image processing section 40, The output data of the first selector 13 (not shown) in the image processing section 60 and the first selector 13 (not shown) in the image processing section 40 are connected between the image processing sections 70 and 40. A selector 90 is provided for selecting output data (not shown).

In such a configuration, the selector 80 selects the image processing section 6.
By selecting the output data of the first selector 13 in 0 and selecting the output data of the first selector 13 in the image processing section 40 with the selector 90, this device
Performs bit boundary processing for a 2-pit x 1-plane memory system. On the other hand, the selector 80 selects the image processing section 4.
By selecting the output data of the first selector 13 in 0 and selecting the output data of the first selector 13 in the image processing section 60 with the selector 90, this device
Bit boundary processing is performed for a 6-bit x 2-plane memory system. Furthermore, by using each image processing section independently as described above, this system)
The device performs bit boundary processing for a memory system of 1 word, 8 bits x 4 sides. Therefore, this applied example device performs bit boundary processing for three types of memory systems having different word lengths.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide an image processing apparatus that can perform bit boundary processing on various memory systems having different word lengths.

[Brief explanation of the drawing]

FIG. 1 shows the image processing 11i according to the present invention.
Figure 2 is a block diagram showing the configuration of one embodiment of the present invention, and Figures 3 and 4 respectively explain the operation of the above-mentioned actual travel example device. 5 is a block diagram showing the configuration of an application example of the present invention, FIG. 6 is a block diagram of a conventional device, FIG. 7 is a diagram for explaining the above conventional device, and FIG. 8 is a block diagram showing the configuration of an application example of the present invention. It is a timing chart of a conventional device. 11...First pass line, 12...Register, 1
3...first selector, 14...third selector,
15... Second selector, 16... Second pass line, 17... Barrel shifter, 20.30... Image processing unit. Applicant's agent Patent attorney Takehiko Suzue Jll Figure 2 Figure 3 Figure 4rIA

Claims (2)

[Claims] (1) A first image data bus line to which image data is transferred, a register connected to the first image data bus line and storing the image data, an output line of the register and the first image data first and second selectors to which bus lines are connected, a second image data bus line, and a third selector to which the second image data bus line and the first image data bus line are connected. and a data shifting means to which the output lines of the second and third selectors are connected and which shifts the output data of the second and third selectors by an arbitrary number of bits and outputs the shifted data. An image processing device characterized by having one image processing device. (2) A plurality of the image processing sections are provided, and the second image data bus line of one image processing section is connected to the output of the first selector of the other image processing section. The image processing device described in .