JPH08336114A - Line conversion circuit for image processor - Google Patents

Abstract

PURPOSE: To perform line conversion by difference of a broadcast system with simple constitution and to speed up conversion speed when image data is processed in block unit. CONSTITUTION: The read clock of decoded image data is outputted from a clock generating part 6 to a codec 1, and sequentially read out data H1 -H7 are written on a line buffer 3. When the point values of registers 9, 10 show zeros, the data in the line buffet 3 is read out as it is. The data goes to a first line Y0 PL0 . Thence, a switch 2 is switched to buffer 4 side, and the next line Y0 L1 picture element data H0 is written on the address O of the buffer 4. Simultaneously, the picture element data H0 of the line Y0 L0 is read out, and inputted to an arithmetic circuit 8. The circuit 8 reads out the coefficient A0 of the register 9, and multiplies it by data Y0 L0 -H0 , and generates data Y0 L0 -H0 a. While, the data Y0 L0 -H0 is multiplied by the coefficient B0 of the register 10, and data Y0 L1 -H0 a is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, in an image processing apparatus for processing image data in block units, converts, in block units, a difference in pixel configuration due to a difference in broadcasting system between a sending side and a receiving side of image data. To a line conversion circuit for

[0002]

2. Description of the Related Art Generally, for example, when displaying image data of a pixel configuration of NTSC system by PAL system, as shown in FIG. 23, pixels of two lines adjacent to each other from the image memory without changing the data on the image memory. Is read out, calculated by linear interpolation, and output. PAL system to NTSC
The same applies when converting to a system. Figure 24 shows NTSC
The arithmetic expression in the arithmetic circuit for performing line conversion between the lines A to E of the system and the lines a to f of the PAL system is shown.

However, when the image data of the pixel structure of the NTSC system is converted into the image data of the pixel structure of the PAL system, since the number of lines increases, the original image data of the NTSC system is embedded in the converted data. Therefore, it is difficult to perform conversion on the same memory. Therefore, FIG.
As shown in FIG. 5, a line buffer for two lines is provided in the preceding stage of the arithmetic circuit, arithmetic is performed between the two lines of this line buffer, and the result is written in the PAL image memory. Since the conversion from the PAL system to the NTSC system is a conversion in which the number of lines is reduced, the original image data is not erased and therefore conversion on the same memory is possible.

By the way, image data is handled in units of blocks (plural m × n pixels) like the block interleave system of JPEG which is a color still image coding standard, and the luminance Y, color difference CB, CR ( In an image processing device that performs temporally alternate processing for each component (in the case of YUV components), when performing pixel configuration conversion between the NTSC system and the PAL system, block / line conversion for one macroblock line is performed. Block buffer is needed. FIG. 26 shows a configuration for converting NTSC data of the "Y: U: V = 2: 1: 1" block interleave system into PAL data.

[0005]

However, in the conventional configuration shown in FIG. 26, in the case where the image data decoded by the JPEG codec is converted into the pixel configuration and expanded on the image memory, one macroblock is used. Since a large-capacity block buffer for lines is required, it is not preferable because it increases the cost of the device.

Moreover, since conversion cannot be performed until the data for one macroblock line is complete, the throughput of data processing is reduced, and it cannot be applied to an application requiring a conversion speed. If a dual port buffer or the like is used to solve this inconvenience, the cost of the device will be further increased.

An object of the present invention is to block image data in block units.
It is an object of the present invention to provide a line conversion circuit capable of realizing line conversion due to a difference in broadcasting system with a simple configuration when processing data, and accelerating conversion speed.

[0008]

A line conversion circuit of an image processing apparatus according to a first invention of the present application is arranged in a horizontal direction for each component of a video signal in a pixel block unit consisting of a plurality of m × n pixel pixel data. In an image processing apparatus for continuously processing image data and storing it in an image memory, first and second pixel data for temporarily storing pixel data of each line forming a pixel block alternately for each line. A line buffer, a calculation coefficient setting means for setting a calculation coefficient for line conversion determined according to a line address on the image memory for the pixel data stored in the line buffer, first and second
While the pixel data is written in one of the line buffers of the first line buffer, the pixel data at the corresponding position of the other line buffer is read out and the operation coefficient for each pixel data of the first and second line buffers is calculated. An arithmetic means for performing the arithmetic operation and a memory address generating means for generating an address signal for storing the pixel data generated by the arithmetic means in the image memory in block units are provided.

A line conversion circuit of an image processing apparatus according to the second invention of the present application is arranged such that an image is alternately displayed in a horizontal direction and a vertical direction for each component of a video signal in a pixel block unit composed of a plurality of m × n pixel pixel data. In an image processing apparatus for processing data and storing it in an image memory, first and second line buffers for temporarily storing pixel data of each line forming a pixel block alternately for each line, A calculation coefficient setting means for setting a calculation coefficient for line conversion determined according to a line address on the image memory for the pixel data stored in the line buffer, and a point value of the calculation coefficient setting means for each block are held. A pointer buffer,
Pixel data is written into one of the first and second line buffers, and at the same time, pixel data at a corresponding position in the other line buffer is read out to obtain the first data.
And a computing means for computing using the computing coefficient for each pixel data of the second line buffer, and a memory address generation for generating an address signal for storing the pixel data generated by the computing means in block units in the image memory. And means are provided.

[0010]

According to the configuration of the present invention, for each component (eg, Y, CB, CR), such as a JPEG codec,
In addition, when image data is sequentially output in units of blocks (for example, 8 × 8 pixels), one line (8 pixels) forming the first block is written in the first line buffer and the next one line (8 pixels) is written. (Pixel) is written in the second line buffer, at the same time, the pixel data of the corresponding address in the first line buffer is read out, and the calculation with the calculation coefficient for each pixel set in advance by the calculation coefficient setting means is performed. Thus, the pixel data after the conversion of the number of lines is generated and stored in the image memory.

As a result, a large-capacity block buffer for one macroblock line is not required unlike the conventional case,
Line conversion can be performed with a configuration having only a minimum line buffer. Moreover, since the conversion processing can be continuously performed without stopping the flow of data, the throughput in the conversion does not decrease.

In addition, according to the configuration of the second invention of the present application, the blocks in the horizontal direction and the vertical direction are alternated, for example, as in the JPEG “Y: U: V = 4: 1: 1” block interleave system. It is also possible to perform line conversion in the case where it is processed as follows.

[0013]

1 is a block diagram showing a first embodiment of a line conversion circuit of an image processing apparatus according to the present invention. In this embodiment, a JPEG codec 1 for decoding image data by the JPEG block interleave method, a changeover switch 2, first and second line buffers 3 and 4, and write and read addresses to the line buffers 3 and 4 are generated. A line buffer / address counter 5, an R / W clock generator 6 for generating an R / W clock for reading / writing data from the JPEG codec 1, and an arithmetic coefficient register controller 7 for setting arithmetic coefficients. , An arithmetic circuit 8, an arithmetic coefficient register 9 corresponding to the first line buffer 3, and an arithmetic coefficient register 10 corresponding to the second line buffer 4, and the output of the arithmetic circuit 8 controls the memory address generation unit 11. In addition, it is configured to be stored in the image memory 12.

Next, the JPEG "Y: U: V = 2: 1:
The operation of converting the image data of the NTSC system obtained by decoding the data of the 1 "block interleave system into the image data of the pixel configuration of the PAL system as the input of the line conversion circuit according to the configuration of this embodiment will be described. To do.

In JPEG "Y: U: V = 2: 1: 1" block interleave system data, one macroblock is composed of four component blocks Y0, Y1, CB, and CR, as shown in FIG. And each component block is 8 × 8
It is composed of pixels (8 lines × 8 dots). For convenience of explanation, Y0L0 to Y0 are assigned to each line in the Y0 block.
In each line of the L7 and Y1 blocks, Y1L0 to Y1L7,
Codes CBL0 to CBL7 are attached to the lines of the CB block, and CRL0 to CRL7 are attached to the lines of the CR block. In addition, H0 is sequentially assigned to pixels in the horizontal direction in each line.
The symbol is ~ H7.

In the initial state, the arithmetic coefficient register pointer and the line buffer / address counter 5 in the arithmetic coefficient register control unit 7 are both zero. The changeover switch 2 is connected to the line buffer 3 side. After that, the line conversion operation is performed in the following procedure.

First, from the R / W clock generator 6 to the JPE
A 1-byte read clock of the decoded image data is output to the G codec 1 (procedure 1). Then
Line Y0L0 read from JPEG Codec 1
The pixel data H0 therein is written into address 0 of the line buffer 3. After that, the same operation is repeated sequentially, and the line Y
The pixel data H1 to H7 in 0L0 are written to the addresses 1 to 7 of the line buffer 3. Thus 1 of Y0 block
The writing of the pixel data H0 to H7 in the line Y0L0 to the line buffer 3 is completed. At this stage, the count value of the line buffer / address counter 5 is changed from 7 to 0,
The pointer point values of the arithmetic coefficient registers 9 and 10 are 0 (procedure 2).

When the point value of the arithmetic coefficient registers 9 and 10 is 0, the data written in the line buffer 3 is read as it is without performing arithmetic operation in the arithmetic circuit 8.
This becomes the first output line Y0PL0 (procedure 3).
The above operation is shown in FIG.

Next, as shown in FIG. 4, the changeover switch 2 is changed over to the line buffer 4 side, and the above-mentioned procedure 1 is performed.
Similarly to 2 to 2, the pixel data H0 of the next line Y0L1 is written in the address 0 of the line buffer 4. At the same time, the line Y0L0 which is the data of the address 0 of the line buffer 3
Pixel data H0 (hereinafter referred to as data Y0L0-H0) is read and each data is input to the arithmetic circuit 8 (procedure 4).

In the arithmetic circuit 8, since the pointers of the arithmetic coefficient registers 9 and 10 are 0, the arithmetic coefficient register 9
The coefficient A0 in the register 0 is read out and multiplied by the data Y0L0-H0 obtained in the procedure 4 to obtain the data Y0.
Generate L0-H0a. On the other hand, the data Y0L1-H0 obtained in the procedure 4 is multiplied by the coefficient B0 in the register 0 of the arithmetic coefficient register 10 to obtain the data Y0L1-H0.
a is generated. And the data Y0L0-
H0a and data Y1L0-H0a are added to output the data.
Y0PL1-H0 is generated (procedure 5).

Then, the operation of procedure 4 is repeated to write the pixel data H1 to H7 of the line Y0L1 to the addresses 1 to 7 of the line buffer 4 and at the same time.
The data Y0L0-H1 to H7 of the addresses 1 to 7 are read out, the operation circuit 8 performs the same operation as in step 5 to generate the output data Y0PL1-H1 to H7, and the output line Y0P
L1 is output (procedure 6).

Next, as shown in FIG. 5, the changeover switch 2 is set to the line buffer 3 side, the arithmetic coefficient register pointer of the arithmetic coefficient register control section 7 becomes 1, and
The count value of the line buffer / address counter 5 is 7
To 0. Then, as in steps 2 to 4, line Y0
The pixel data H0 to H7 of L2 are written in the line buffer 3 and the output line Y0PL2 is output (procedure 7).

Next, as shown in FIG. 6, the changeover switch 2 is set to the line buffer 4 side, and the arithmetic coefficient register pointer of the arithmetic coefficient register control unit 7 becomes 2.
Then, as in steps 2 to 4, the pixel data of the line Y0L3 is
The data H0 to H7 are written in the line buffer 4, and the output line Y0PL3 is output (procedure 8).

Next, as shown in FIG. 7, the changeover switch 2 is set to the line buffer 3 side, and the arithmetic coefficient register pointer of the arithmetic coefficient register control unit 7 becomes 3.
Then, as in steps 2 to 4, the pixel data of the line Y0L4 is
The data H0 to H7 are written in the line buffer 3, and the output line Y0PL4 is output (procedure 9).

Next, as shown in FIG. 8, the changeover switch 2 is set to the line buffer 4 side, and the arithmetic coefficient register pointer of the arithmetic coefficient register control unit 7 becomes 4.
Then, as in steps 2 to 4, the pixel data of the line Y0L5 is
The data H0 to H7 are written in the line buffer 4, and the output line Y0PL5 is output (procedure 10).

Here, since the arithmetic coefficient register pointer of the arithmetic coefficient register control unit 7 returns to 0, as shown in FIG. 9, the line Y0L written in the procedure 10 as in the procedure 3.
The pixel data of No. 5 is read out and output without performing arithmetic operation in the arithmetic circuit 8. This becomes the output line Y0PL6 (procedure 11).

At this point, all the above-mentioned calculations shown in FIG. 24 have been completed. After that, this process is repeated. However, since line Y0L6 and line Y0L7 still remain in the line data of one block, next,
The number of lines is converted using this.

First, as shown in FIG. 10, the changeover switch 2 is set to the line buffer 3 side, and the line Y0L is set.
At the same time that the pixel data of No. 6 is written in the line buffer 3, the pixel data of the line Y0L5 is read from the line buffer 4, and the arithmetic circuit 8 using the arithmetic coefficients A0 and B0 indicated by the register 0 of the arithmetic coefficient registers 9 and 10. And output the output line Y0PL7 (procedure 1
2).

Next, as shown in FIG. 11, the changeover switch 2 is set to the line buffer 4 side, and the arithmetic coefficient register pointer of the arithmetic coefficient register control unit 7 becomes 1. Then, at the same time that the pixel data of the line Y0L7 is written in the line buffer 4, the pixel data of the line Y0L6 is read from the line buffer 3 and the operation coefficients A1 and B shown in the register 1 of the operation coefficient registers 9 and 10 are read.
The calculation circuit 8 performs the calculation using 1 and outputs the line Y0PL8 (procedure 13).

This completes the line conversion of the Y0 block shown in FIG. At this time, the count value of the line buffer / address counter 5 is set to 8 and the arithmetic coefficient register pointer is reset to 0. Further, the changeover switch 2 is changed over to the line buffer 3 side.

Thereafter, Y1 block, CB block, CR
By performing the same processing as in steps 1 to 13 on each of the blocks, the converted output lines Y1PL0 to Y1PL0
Y1PL7, output lines CBPL0 to CBPL7, and output lines CRPL0 to CRPL7 are sequentially generated and output.

The line buffer / address counter 5 is 1
Since it is incremented by 8 for each block processing, when the processing of this one macroblock is completed,
Its value is 32. That is, the value of the line buffer / address counter 5 is 8 for each block,
In one macroblock, the count is incremented by 32, and the arithmetic coefficient register pointer performs a loop count of 0 to 4 (when converting from the NTSC system to the PAL system).

When the conversion of the image data of one macroblock line read by the JPEG codec 1 is completed in this way, the value of the operation coefficient register pointer (3 in this case) is set in the pointer buffer part of the register. Save (not shown). At this point, the line buffer 4 has the data of the lowest line L7 before conversion of each block forming the first macroblock line.

Next, when converting the data of the second macroblock line, the following operation is performed. First, the value stored in the pointer buffer is read and set in the arithmetic coefficient register pointer. Next, the pixel data H0 to H7 of the line Y0L0 of the first macroblock of the second macroblock line is read from the JPEG codec 1 and written in the line buffer 3. In parallel with this, pixel data of addresses 0 to 7 stored in the line buffer 4 are sequentially read out, and for each data, the coefficient A3 set in the register indicated by the operation coefficient register pointer (here, 3) is set. , B3 are used for calculation, and the line Y
0PL9 is generated (procedure 14).

Next, the pixel data H0 to H7 of the line Y0L1 next to the second macroblock line is written to the line buffer 3 and, at the same time, the data Y0 of the line buffer 4 is written.
L0-H0 to H7 are read out, calculation is performed using the coefficients A4 and B4 stored in the calculation coefficient registers 9 and 10, and the line Y0PL10 is output (procedure 15).

Thereafter, the same processing as steps 1 to 13 is performed,
Perform line conversion. After the conversion of each block is completed, the value of the pointer buffer is set again in the arithmetic coefficient register pointer, and the processing of the next block is started. In this way, when the conversion of the second macroblock line is completed, the conversion process is sequentially performed according to the data format of the JPEG codec 1, such as the third macroblock line, the fourth macroblock line, .... This completes the line conversion processing in block units.

Next, a second embodiment of the line conversion circuit of the image processing apparatus according to the present invention will be described. In the present embodiment, blocks having different sampling ratios in the line direction (blocks having different numbers of blocks forming one image) like the block interleave method of JPEG “Y: U: V = 4: 1: 1” are used. This is an example of the case where the input is mixed.

FIG. 12 is a block diagram showing a second embodiment of the present invention, which includes a JPEG codec 21, a changeover switch 22, and first and second line buffers 23 and 2.
4. Line buffer / address counter 25 for generating write / read addresses to line buffers 23 and 24, R / W clock generation for generating R / W clock for reading / writing data from JPEG codec 21 Unit 26, arithmetic coefficient register control unit 27 for setting arithmetic coefficients, arithmetic circuit 28, first
First arithmetic coefficient register 29 corresponding to the line buffer 23, second arithmetic coefficient register 30 corresponding to the second line buffer 4, pointers for holding pointer values of arithmetic coefficient registers 29 and 30 Buffer 3
1, and the output of the arithmetic circuit 28 is stored in the image memory 33 under the control of the memory address generator 32.

Next, the JPEG "Y: U: V = 4: 1:
An operation for converting NTSC image data obtained by decoding 1 "block interleaved data into a PAL format pixel configuration as an input of the line conversion circuit according to the configuration of the present embodiment will be described.

In JPEG "Y: U: V = 4: 1: 1" block interleave system data, one macroblock is Y0, Y1, Y2, Y3, C as shown in FIG.
It is composed of 6 component blocks of B and CR, and each component block is composed of 8 × 8 pixels (8 lines × 8 dots). For convenience of description, Y0L0 to Y0L7 are assigned to each line in the Y0 block, and Y1L is assigned to each line in the Y1 block.
0 to Y1L7, Y2L0 to Y on each line of the Y2 block
Y3L0 to Y3L on each line of 2L7 and Y3 blocks
7, CBL0 to CBL7, C on each line of the CB block
Codes CRL0 to CRL7 are attached to each line of the R block. In addition, the horizontal pixels in each line are sequentially numbered H0 to H7.

In the initial state, the arithmetic coefficient register control unit 27
The value of all addresses in the calculation coefficient register pointer and the pointer buffer 31 and the line buffer / address counter 25 are all zero. The changeover switch 2 is connected to the line buffer 23 side. After that, the line conversion operation is performed in the following procedure.

First, from the R / W clock generator 26, JP
A 1-byte read clock of the decoded image data is output to the EG codec 21 (procedure 21). The read data Y0L0-H0 is stored in the line buffer 23.
Write to address 0 of. After that, the same operation is sequentially repeated, and the data Y0L0-H1 to H7 are transferred to the line buffer 2
Write to addresses 1 to 7 of 3. This completes the writing of one line in the Y0 block. At this stage, the value of the line buffer / address counter 25 is 7 to 0.
Further, the pointers of the arithmetic coefficient registers 29 and 30 are 0 (procedure 22).

Next, when the pointer values of the arithmetic coefficient registers 29 and 30 are 0, the data written in the line buffer 23 is read out without arithmetic operation in the arithmetic circuit 28. This is the first output line Y0P of the line conversion circuit.
It becomes L0 (procedure 23).

Next, the changeover switch 2 is changed over to the line buffer 24 side, and the data Y0L1 of the next line is set to the address 0 of the line buffer 24 as in steps 21 to 22.
At the same time as writing -H0, the data Y0L0-H0 at the address 0 of the line buffer 23 is read out, and the respective data are input to the arithmetic circuit 28 (procedure 24).

In the arithmetic circuit 28, the arithmetic coefficient register 29
Since the pointers of 30 and 30 are 0, the coefficient in the register 0 of the arithmetic coefficient register 29 is read out, and the procedure 24
The data Y0L0-H0 obtained in the above is multiplied and data Y is obtained.
0L0-H0a is generated. On the other hand, the data Y0L1-H0 obtained in step 24 is multiplied by the coefficient in the register 0 of the arithmetic coefficient register 30 to generate data Y0L1-H0a. Then, the data Y0L0-H which is the calculation result
0a and data Y1L0-H0a are added to output data Y
0PL1-H0 is generated (procedure 25).

Then, as in step 24, data Y0L1
-H1 to H7 are written to the addresses 1 to 7 of the line buffer 24, and at the same time, the addresses 1 to 7 of the line buffer 23 are written.
7 data Y0L0-H1 to H7 are read out and arithmetic circuit 2
Enter in 8. Then, the same calculation as in step 25 is performed to generate output data Y0PL1-H1 to H7, and the output line Y0PL1 is output (step 26).

Next, the changeover switch 22 is set to the line buffer 23 side, and the operation coefficient registers 29 and 30 are set.
The register pointer of 1 is changed to 1, and the line buffer address counter 25 is changed from 7 to 0. Then, steps 22 to 2
Similarly to 4, the pixel data of the line Y0L2 is written in the line buffer 23, and the output line Y0PL2 is output (procedure 27).

Next, the changeover switch 22 is set to the line buffer 24 side, and the operation coefficient registers 29 and 30 are set.
The register pointer of becomes 2. Then, steps 22 to 2
Similarly to 4, the pixel data of the line Y0L3 is written in the line buffer 24 and the output line Y0PL3 is output (procedure 28).

Next, the changeover switch 22 is set to the line buffer 23 side, and the operation coefficient registers 29 and 30 are set.
The register pointer of becomes 3. Then, steps 22 to 2
Similarly to 4, the pixel data of the line Y0L4 is written in the line buffer 23 and the output line Y0PL4 is output (procedure 29).

Next, the changeover switch 22 is set to the line buffer 24 side, and the operation coefficient registers 29 and 30 are set.
The register pointer of becomes 4. Then, steps 22 to 2
Similarly to 4, the pixel data of the line Y0L5 is written in the line buffer 24 and the output line Y0PL5 is output (step 30).

Next, the changeover switch 22 is set to the line buffer 23 side, and the operation coefficient registers 29 and 30 are set.
The register pointer of is returned to 0. Register pointer is 0
Returning to step 23, similarly to step 23, the pixel data of the line Y0L5 written in step 30 is read out, and the arithmetic circuit 28 outputs it without performing arithmetic operation. This is the output line Y0PL6
Becomes At this point, all the calculations shown in FIG. 24 have been completed. After that, this process is repeated. However, the line data for one block is still Y0L6
And the line Y0L7 remains, the number of lines is converted using this (step 31).

At the same time as writing the pixel data of the line Y0L6 into the line buffer 23, the pixel data of the line Y0L5 is read from the line buffer 24, and the calculation coefficient A0, which is indicated by the register 0 of the calculation coefficient registers 29 and 30,
B0 is used to perform calculation in the calculation circuit 28, and the output line Y
0PL7 is output (procedure 32).

Next, the pixel data of the line Y0L7 is written in the line buffer 24, and at the same time, the line buffer 23 is written.
The pixel data of the line Y0L6 is read from the calculation coefficient A shown in the register 1 of the calculation coefficient registers 29 and 30.
The arithmetic circuit 28 performs an arithmetic operation using 1 and B1 and outputs the output line Y0PL8 (step 33).

This completes the line conversion of the Y0 block. Line buffer address counter 2 at this point
5 is set to 8, and the arithmetic coefficient register pointer is stored in the address 0 of the pointer buffer 31 and then reset to 0. The changeover switch 2 is set on the line buffer 23 side.

Then, steps 21 to 21 are performed for the Y1 block.
Perform the same processing as 33 to output lines Y1PL0 to Y1.
Generate PL7. Here, the value of the line buffer / address counter 25 returns to 0. In the above-described first embodiment, this value is 16. That is, the buffering of the line data of the next CB block is performed at the address 16
It was meant to be used from. FIG. 14 shows a procedure for generating the output line Y1PL8 (procedure 34).

Next, the value (0 in this case) of the arithmetic coefficient register pointer is stored in the address 1 of the pointer buffer 31, and the changeover switch 22 is changed over to the line buffer 23 side. Then, the next Y2 block is processed as follows.

First, as shown in FIG. 15, the value P0 of the address 0 of the pointer buffer 31 is set to the arithmetic coefficient register 29.
And 30 arithmetic coefficient register pointers.
As a result, the value (3 in this case) of the arithmetic coefficient register pointer at the time of converting the line Y0L7 of the Y0 block is restored. Next, the first line data Y2L0-H0-H of the Y2 block is output from the JPEG codec 21.
7 is read and written in the line buffer 23. In parallel with this, the data Y0L7-H0 to H7 at addresses 0 to 7 stored in the line buffer 24 are sequentially read out,
The arithmetic circuit 28 performs arithmetic operation on each data using the arithmetic coefficients A3 and B3 set in the arithmetic coefficient register pointer described above, and outputs the output line Y2PL0 (step 35).

Next, as shown in FIG. 16, the changeover switch 22 is set to the line buffer 24 side, and the register pointers of the arithmetic coefficient registers 29 and 30 become 4. Then, the data Y2L1-H0 to H7 are transferred to the line buffer 2
4 and simultaneously the data Y2 of the line buffer 23
L0-H0 to H7 are read out, and the operation coefficient register 29,
Calculation is performed using the calculation coefficients A4 and B4 stored in 30 to generate the output line Y2PL1 (step 36).

Thereafter, similar processing is performed on the lines Y2L2 to Y2L7, and output lines Y2PL2 to Y2PL9.
Generate FIG. 17 shows a process of generating the output line Y2PL9 (procedure 37). At this point, the value of the arithmetic coefficient register pointer (0 in this case) is stored at address 0 of the pointer buffer 31. Further, the line buffer / address counter 25 becomes 8.

Next, in order to convert the Y3 block, as shown in FIG. 18, the value of the address 1 (3 in this case) P1 of the pointer buffer 31 is set in the arithmetic coefficient register pointer as in the case of the Y2 block. . And the de
Data Y3L0-H0-H7 to the line buffer 23 and data Y1L7-H0 of the line buffer 24 at the same time.
To H7 are read out, calculation is performed using the coefficients A3 and B3 stored in the calculation coefficient registers 29 and 30, and the output line Y3PL0 is generated (procedure 38).

Next, as shown in FIG. 19, the changeover switch 22 is set to the line buffer 24 side, and the data Y
3L1-H0-H7 are written in the line buffer 24, and at the same time, data Y3L0-H0-H in the line buffer 23 are written.
7 is read, calculation is performed using the calculation coefficients A4 and B4 stored in the calculation coefficient registers 29 and 30, and the output line Y3PL1 is output (procedure 39).

Thereafter, similar processing is performed on the lines Y3L2 to Y3L7, and output lines Y3PL2 to Y3PL9.
Generate FIG. 20 shows a process of generating the output line Y3PL9 (procedure 40). At this point, the value of the arithmetic coefficient register pointer (0 in this case) is stored in the address 1 of the pointer buffer 31. Further, the line buffer / address counter 25 becomes 16.

Next, before the conversion of the CB block, the value of address 2 of the pointer buffer 31 (in this case, the initial value 0) is set in the arithmetic coefficient register pointer. Then, the same processing is performed on the lines CBL0 to CBL7 to generate the output lines CBPL0 to CBPL8. Then, the value of the next arithmetic coefficient register pointer (here, 3) is stored in the address 2 of the pointer buffer 31.
FIG. 21 shows a process of generating the output line CBPL8 (procedure 41).

Then, the CR block is converted in the same manner as in step 41. That is, before conversion is performed, the pointer buffer 31
The value of the address 3 (in this case, the initial value 0) is set in the arithmetic coefficient register pointer. Then line CRL0
~ Do the same processing for CRL7 and output line CR
PL0 to CRPL8 are generated. Then, the value of the next arithmetic coefficient register pointer (here, 3) is stored in the address 3 of the pointer buffer 31. Output line C in FIG.
The generation process of RPL8 is shown (procedure 42).

This completes the line conversion of the first macro block. After that, the same data as in steps 21 to 42 is repeated to generate subsequent data. This allows line conversion processing in block units.

In this case, JPEG "Y: U: V =
The conversion processing in the case of storing the decoded data of the block interleave system of 4: 1: 1 ”in the image memory has been described. The data input to this conversion circuit is, for example, J
"Y: U: V = 4: 2: 2" of PEG and "Y: U: V =
4: 4: 4 ", etc., even when vertical blocks of an image are alternately sent, or even when horizontal blocks are continuously input as in the first embodiment. Is possible.

However, the value of the arithmetic coefficient register pointer must be saved every time the processing of one block is completed, and the number of buffers and control circuits for that purpose is increased as compared with the first embodiment. When the input is limited to the first embodiment, it is preferable to use the configuration of the first embodiment.

In the above embodiment, the conversion from the NTSC image data to the PAL image data has been described, but in any case, the PAL image data is converted to the NTSC image data. Can also be converted into image data. In this case, set the setting value of the calculation coefficient register to PAL.
It is necessary to set the calculation coefficient from the system to the NTSC system and set the count value of the calculation coefficient register pointer to 0-5.

[0069]

According to the present invention, only the line buffer for two lines is required instead of the block buffer having the storage capacity for one macroblock line, which has been conventionally required, and it is possible to reduce the cost and the circuit scale. There is an effect that.

Further, in the past, line conversion could not be performed until data for one macroblock line was prepared.
According to the present invention, since conversion can be performed sequentially when two lines in one block are aligned, there is an effect that the data processing speed associated with conversion can be significantly improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a macroblock of a JPEG “Y: U: V = 2: 1: 1” block interleave system.

FIG. 3 is an explanatory diagram of procedures 1 to 3 of the present invention.

FIG. 4 is an explanatory diagram of procedures 4 to 6 of the present invention.

FIG. 5 is an explanatory diagram of procedure 7 of the present invention.

FIG. 6 is an explanatory diagram of procedure 8 of the present invention.

FIG. 7 is an explanatory diagram of a procedure 9 of the present invention.

FIG. 8 is an explanatory diagram of procedure 10 of the present invention.

FIG. 9 is an explanatory diagram of procedure 11 of the present invention.

FIG. 10 is an explanatory diagram of procedure 12 of the present invention.

FIG. 11 is an explanatory diagram of procedure 13 of the present invention.

FIG. 12 is a block diagram showing a second embodiment of the present invention.

[Fig. 13] Fig. 13 is a diagram illustrating the configuration of a macro block of a "Y: U: V = 4: 1: 1" block interleave system of JPEG.

FIG. 14 is an explanatory diagram of the procedure 34 of the present invention.

FIG. 15 is an explanatory diagram of a procedure 35 of the present invention.

FIG. 16 is an explanatory diagram of the procedure 36 of the present invention.

FIG. 17 is an explanatory diagram of procedure 37 of the present invention.

FIG. 18 is an explanatory diagram of the procedure 38 of the present invention.

FIG. 19 is an explanatory diagram of procedure 39 of the present invention.

FIG. 20 is an explanatory diagram of the procedure 40 of the present invention.

FIG. 21 is an explanatory diagram of procedure 41 of the present invention.

FIG. 22 is an explanatory diagram of the procedure 42 of the present invention.

FIG. 23 is a schematic diagram of NTSC / PAL conversion.

FIG. 24 is an explanatory diagram illustrating a calculation of linear interpolation of NTSC / PAL conversion.

FIG. 25 is an explanatory diagram illustrating an operation of conventional line conversion using a line buffer.

FIG. 26 is an explanatory diagram illustrating a conventional line conversion operation in the case of the “Y: U: V = 2: 1: 1” block interleave method.

[Explanation of symbols]

 1, 21 JPEG codec 2, 22 Changeover switch 3, 23 First line buffer 4, 24 Second line buffer 5, 25 Line buffer / address counter 6, 26 R / W clock generator 7, 27 Calculation coefficient Register control unit 8,28 Arithmetic circuit 9,29 First arithmetic coefficient register 10,30 Second arithmetic coefficient register 11,32 Memory address generating unit 12,33 Image memory 31 Pointer buffer

Claims (2)

[Claims] 1. An image processing apparatus for continuously processing image data in the horizontal direction for each component of a video signal in a pixel block unit composed of a plurality of m × n pixel data, and storing the processed image data in an image memory. First and second line buffers for temporarily and temporarily storing pixel data of each line forming the pixel block for each line; and on the image memory for the pixel data stored in the line buffer. And a calculation coefficient setting means for setting a calculation coefficient for line conversion determined according to the line address in the first and second line buffers, and at the same time the pixel data is written in one of the first and second line buffers. The pixel data at the corresponding position of the line buffer is read out and the arithmetic unit for the pixel data of each of the first and second line buffers is read. An image characterized by comprising: an arithmetic means for performing arithmetic operation using the above; and a memory address generating means for generating an address signal for storing the pixel data generated by the arithmetic means in the image memory in block units. Line conversion circuit for processing equipment. 2. An image processing apparatus for alternately processing image data in a horizontal direction and a vertical direction for each component of a video signal in a pixel block unit composed of a plurality of m × n pixel data and storing the processed image data in an image memory. The first and second line buffers for temporarily storing the pixel data of each line forming the pixel block alternately for each line, and the image for the pixel data stored in the line buffer. Arithmetic coefficient setting means for setting an arithmetic coefficient for line conversion determined according to a line address on a memory; a pointer buffer for holding the point value of the arithmetic coefficient setting means in block units; While the pixel data is written into one of the two line buffers, the pixel data of the corresponding position in the other line buffer is simultaneously written. Computing means for reading the data and computing using the computing coefficient for the pixel data of each of the first and second line buffers; and the pixel data generated by the computing means in the image memory in block units. A line conversion circuit of an image processing apparatus, comprising: a memory address generation unit that generates an address signal for storing.