JPH1040366A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor by which raster sequential image data can be converted into block sequential image data, or the block sequential image data can be converted into the raster sequential image data at low cost without sacrificing the operating speed. SOLUTION: This device is provided with an even numbered pixels memory 23 and an odd numbered pixel memory 24. The operation of writing inputted odd pixel data in the odd numbered pixel memory 24 at the time of reading odd numbered pixels from the odd numbered pixels memory 23, and the operation of writing inputted even numbered pixels data in the even numbered pixel memory 23 at the time of reading odd numbered pixels from the odd numbered pixel memory 24 are repeatedly executed under the control of a control circuit 25. Then, the control circuit 25 makes the address generation order of the even numbered pixel memory 23 and the odd numbered pixel memory 24 at the time of writing different from that at the time of reading.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for processing image data, and more particularly, to converting raster-input image data into block-sequential image data or converting block-input image data into raster-sequential data. The present invention relates to an image processing device for converting image data into image data.

[0002]

2. Description of the Related Art Conventionally, an international standard JPEG (Joint Photographic Expert) has been used as a compression technique for multivalued image data.
Group) method. In this JPEG compression technique, RGB pixel components input in raster order are converted to YU
Convert to V pixel component. The YUV pixel data obtained in this way is DCT (decrete cosine) in units of 8 × 8 blocks.
transform; discrete cosine transform) is transformed into a spatial frequency component. What is converted to this spatial frequency is DCT
It is called a coefficient. Then, the DCT coefficient is quantized in two types of 8 × 8 units of a luminance component (Y) and a chromaticity component (U, V). Note that the quantization coefficient here is based on a Huffman coded coefficient which is a variable length coding method.

In the DCT conversion, since processing is performed in units of 8 × 8 blocks, it is necessary to convert raster-input pixel data into block-sequential pixel data before the DCT conversion processing. In order to realize this conversion processing by hardware, a memory for at least eight lines is prepared, and a reading order is changed for pixel data written once.

In order to perform this conversion in a pipeline manner, it is general to prepare two 8-line memories and perform writing and reading at the same time. Specifically, when the eight lines of pixel data are being written to the first line memory, the previous eight lines of pixel data are read from the second line memory and read.
Performs raster block conversion for lines. Next, reverse
The operation of reading pixel data from the second line memory and writing it to the second line memory is repeated.

[0005]

As described above, as described above, JP
In an image processing apparatus using a compression technique based on the EG method, since raster block conversion is realized in hardware in a pipeline manner, two memories for eight lines must be prepared. However, there is a problem that the cost is increased. to solve this problem,
Image processing apparatuses that perform raster block conversion by sequentially reading / writing pixel data for the same address of the same memory have been proposed (for example, Japanese Patent Application Laid-Open Nos. Hei 6-326997 and Hei 8-18791). Gazette).

The image processing apparatus according to the prior art has the advantage that the memory cost can be halved because only one memory is required, but the writing and reading are performed continuously so that the writing and reading per pixel can be performed continuously. 2 for reading
It will take twice as long. That is, in the case where reading and writing of one pixel take a time equivalent to one clock, for example, a waiting time of one clock for reading is inserted between writing of a certain pixel and writing of the next pixel. Writing takes a total of two clocks. Similarly, reading of one pixel requires a time equivalent to two clocks. As described above, although the memory cost can be reduced by half, there is a problem that the performance of the device, that is, the operation speed is sacrificed.

The present invention has been made in view of the above problems, and has as its object to convert raster-sequential image data into block-sequential image data at low cost without sacrificing operation speed. Another object is to provide an image processing apparatus capable of converting block-sequential image data into raster-sequential image data.

[0008]

According to the image processing apparatus of the present invention, 2n (n = 0, 1, 2) from the beginning of input image data
, And the even-numbered pixel data at the position of 2n + 1 (n =
Input means for selecting and inputting odd pixel data at the position of (0, 1, 2,...), Even pixel storage means for storing even pixel data, and odd pixel storage means for storing odd pixel data; The even-numbered pixel data is written to the even-numbered pixel memory in synchronization with the reading of the odd-numbered pixel data from the odd-numbered pixel memory, and the even-numbered pixel data is written to the odd-numbered pixel memory in synchronization with the reading of the even-numbered pixel data from the even-numbered pixel memory. A configuration including control means for writing odd-numbered pixel data, and output means for selecting and outputting even-numbered pixel data read from the even-numbered pixel storage means and odd-numbered pixel data read from the odd-numbered pixel storage means It has become.

In the image processing apparatus having the above configuration, the input odd-numbered pixel data is written into the odd-numbered pixel storage means when the even-numbered pixel is read from the even-numbered pixel storage means, and the input is read when the odd-numbered pixel is read out from the odd-numbered pixel storage means. The operation of writing the even-numbered pixel data to the even-numbered pixel storage means is repeatedly executed under the control of the control means. Then, the control means makes the address generation order of the even-numbered pixel storage means and the odd-numbered pixel storage means different at the time of writing and at the time of reading. As a result, image data input in a raster sequence is converted into image data in a block sequence, or image data input in a block sequence is converted into image data in a raster sequence.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a basic configuration of an embodiment of the present invention. In FIG. 1, the image processing apparatus according to the present embodiment is configured such that even-numbered pixel data located at a position 2n (n = 0, 1, 2,...) From the head of input image data and 2n + 1 (n = 0, 1, 2,. ..) And input means 11 for selecting and inputting the odd-numbered pixel data at the position of...
2 and an odd pixel storage unit 13 for storing odd pixel data
And writes the even-numbered pixel data to the even-numbered pixel storage means 12 in synchronization with the reading of the odd-numbered pixel data from the odd-numbered pixel storage means 13, and writes the odd-numbered data in synchronization with the reading of the even-numbered pixel data from the even-numbered pixel storage means 12. Pixel storage means 13
Control means 14 for writing odd-numbered pixel data to
An output unit 15 selects and outputs even-numbered pixel data read from the even-numbered pixel storage unit 12 and odd-numbered pixel data read from the odd-numbered pixel storage unit 13.

FIG. 2 is a block diagram showing an example of a specific configuration of the image processing apparatus according to the present embodiment. In the figure, the same parts as those in FIG. In FIG. 2, the input means 11 is constituted by a register (REG) 21 and a demultiplexer (DMUX) 22, and the output means 15 is constituted by a multiplexer (MUX) 26 and a register 27, and the even pixel memory 23 is replaced by an even pixel storage means 12. , The odd-numbered pixel memory 24 corresponds to the odd-numbered pixel storage means 13, and the control circuit 25 corresponds to the control means 14.

One data output terminal of the demultiplexer 22 and one data input terminal of the multiplexer 26 are connected to the data input / output terminal of the even-numbered pixel memory 23 via the data bus 31 and the other data output terminal of the demultiplexer 22. The other data input terminal of the multiplexer 26 is connected to the data input / output terminal of the odd pixel memory 24 via the data bus 32.

The control input terminals of the demultiplexer 22 and the multiplexer 26 are connected to the control circuit 25 via signal lines 33 and 34. An address input terminal of the even pixel memory 23 is connected to a control circuit 25 via an address bus 35.
The write enable input terminal and the read enable input terminal are connected to the control circuit 25 via signal lines 36 and 37. Also, the odd pixel memory 2
The address input terminal 4 is connected to the control circuit 25 via an address bus 38, and its write enable input terminal and read enable input terminal are connected to the control circuit 25 via signal lines 39 and 40.

The control circuit 25 has a system clock CL
K, line synchronization signal LSYNC, page synchronization signal PSY
NC, the selection signal S1 of the demultiplexer 22, the selection signal S2 of the multiplexer 26, the address signal S5 of the even pixel memory 23, the address signal S6 of the odd pixel memory 24, and the even pixel memory 2 based on these signals.
3, a write enable signal S7 for the odd-numbered pixel memory 24, a read enable signal S9 for the even-numbered pixel memory 23, and a read enable signal S10 for the odd-numbered pixel memory 24.

In the image processing apparatus having the above configuration, the input-side register 21 synchronizes the input image data with the system clock CLK and supplies it to the demultiplexer 22. The register 27 on the output side synchronizes the output data of the multiplexer 26 with the system clock CLK and outputs it as output image data.

When the selection signal S1 provided from the control circuit 25 via the signal line 33 is at logic "0" (hereinafter simply referred to as "0"), the demultiplexer 22
, And outputs the data to the odd-numbered pixel memory 24 via the data bus 32 when the selection signal S1 is logic “1” (hereinafter simply referred to as “1”). The multiplexer 26 outputs the data of the even-numbered pixel memory 23 via the data bus 31 when the selection signal S2 given from the control circuit 25 via the signal line 34 is 0, and outputs the data bus when the selection signal S2 is 1 The data of the odd-numbered pixel memory 24 is output via the reference numeral 32.

In the even-numbered pixel memory 23, when the write enable signal S7 supplied from the control circuit 25 via the signal line 36 becomes 0, designation by the address signal S5 supplied from the control circuit 25 via the address bus 35 is performed. Data is written to the address, and a read enable signal S provided from the control circuit 25 through a signal line 37 is provided.
When 9 becomes 0, the data at the specified address is read. In the odd-numbered pixel memory 24, when the write enable signal S8 provided from the control circuit 25 via the signal line 39 becomes 0, the data is transferred to the address designated by the address signal S6 provided from the control circuit 25 via the address bus 38. Is written, and when the read enable signal S10 given from the control circuit 25 via the signal line 40 becomes 0, the data at the designated address is read.

FIG. 3 shows raster sequential image data, and FIG. 4 shows block sequential image data. In FIG. 3, the raster sequential image data is input in order from left to right and top to bottom starting from the upper left. In FIG. 4, the block sequential image data is input in order from left to right and top to bottom starting from the upper left in the block. That is, they are input in the order of block 1, block 2,... FIG.
In the example, the main scanning direction is two blocks, but the number of blocks is not limited.

FIG. 5 shows the correspondence between input pixel data and addresses of the even-numbered pixel memory 23 and the odd-numbered pixel memory 24. In the example of FIG. 5, addresses of 8 pixels in the sub-scanning direction are shown for 16 pixels in the main scanning line.

Hereinafter, referring to FIGS. 2, 3, and 5 to 8,
The operation of converting from raster sequential to block sequential will be described. In the timing charts of FIGS. 6, 7 and 8, signal names such as S1 to S10 correspond to the signals shown in FIG. 2, and "-" indicates "Don't Car".
e ”.

First, in FIG. 6, when the page synchronization signal PSYNC becomes 1 and the line synchronization signal LSYNC becomes 1 from time t1, the image data 100 of the first pixel of the first line is obtained.
Are input in synchronization with the rise of the system clock CLK. At time t2, since the selection signal S1 is 0,
Since the image data S3 (100), which is the output data of the register 21, is output to the data bus 31 via the demultiplexer 22, and the write enable signal S7 of the even-numbered pixel memory 23 is 0 at the same time, the image data S3 (1
00) is written to the designated address 0 of the even-numbered pixel memory 23 by the address signal S5.

At time t3, since the selection signal S1 is 1, the image data S4 (10) which is the output data of the register 21 is supplied to the data bus 32 via the demultiplexer 22.
1) is output, and at the same time, the write enable signal S8 of the odd-numbered pixel memory 24 becomes 0, so that the image data S
4 (101) is an address signal S6 of the odd pixel memory 24;
At the specified address 0. At time t4, since the selection signal S1 is 0, the image data S3 (102) which is the output data of the register 21 is output to the data bus 31 via the demultiplexer 22, and at the same time, the write enable signal S7 of the even-numbered pixel memory 23 becomes 0. Therefore, the image data S3 (102) is written to the specified address 1 of the even-numbered pixel memory 23 by the address signal S5.

During the above period, since the read enable signal S9 of the even pixel memory 23 and the read enable signal S10 of the odd pixel memory 24 are active, the initial value of the memory is output. The above operation is repeated in the same manner for eight lines.

In FIG. 7, even pixel memory 23
And the odd-numbered pixel memory 24 store raster-sequential image data for eight lines, and convert these into block-sequential image data while reading them. When the line synchronization signal LSYNC becomes 1 from time t1, the image data 900 of the first pixel on the ninth line is output from the system clock CLK.
Is input in synchronization with the rising edge of. At the same time, since the read enable signal S9 of the even-numbered pixel memory 23 becomes 0, the image data S3 (100) of the first pixel on the first line
Are read from the even-numbered pixel memory 23 from the specified address 0 by the address signal S5. Further, since the selection signal S2 is 0, the image data S3 (1
00) is output.

At time t2, since the selection signal S1 is 0, the image data S3 (90) which is the output data of the register 21 is sent to the data bus 31 via the demultiplexer 22.
0) is output, and at the same time, the write enable signal S7 of the even-numbered pixel memory 23 becomes 0, so that the image data S
3 (900) is the address signal S5 of the even pixel memory 23.
At the specified address 0. At this time, since the read enable signal S10 of the odd-numbered pixel memory 24 becomes 0, the image data S4 (10
1) is read from the specified address 0 of the odd-numbered pixel memory 24 by the address signal S6. Further, the selection signal S
Since 2 is 1, the image data S4
(101) is output. The time t is stored in the register 27.
One image data S3 (100) is stored and output as output image data.

At time t3, since the selection signal S1 is 1, the image data S4 (90) which is the output data of the register 21 is sent to the data bus 32 via the demultiplexer 22.
1) is output, and at the same time, the write enable signal S8 of the odd-numbered pixel memory 24 becomes 0, so that the image data S
4 (901) is an address signal S6 of the odd pixel memory 24.
At the specified address 0. At this time, since the read enable signal S9 of the even-numbered pixel memory 23 becomes 0, the image data S3 (10
2) is read from the designated address 1 of the even pixel memory 23 by the address signal S5. Further, the selection signal S
Since 2 is 0, the multiplexer 26 outputs the image data S3
(102) is output. The time t is stored in the register 27.
The second image data S4 (101) is stored and output as output image data.

The above operation is repeated in the same manner. Time t
In FIG. 9, since the selection signal S1 is 1, the image data S4 (907), which is the output data of the register 21, is output to the data bus 32 via the demultiplexer 22, and at the same time, the write enable signal S8 of the odd-numbered pixel memory 24 becomes 0.
Therefore, the image data S4 (907) is designated by the address signal S6 of the odd pixel memory 24 at the designated address 3
Is written to. At this time, since the read enable signal S9 of the even-numbered pixel memory 23 becomes 0, 1 in the second line
The image data S3 (200) of the pixel is read from the specified address 8 by the address signal S5 of the even-numbered pixel memory 23. Further, since the selection signal S2 is 0, the image data S3 (200) is output from the multiplexer 26. The register 27 stores the image data S4 at time t8.
(107) is stored and output as output image data.

At time t10, since the selection signal S1 is 0, the image data S3 (90) which is the output data of the register 21 is sent to the data bus 31 via the demultiplexer 22.
8) is output, and at the same time, the write enable signal S7 of the even-numbered pixel memory 23 is 0, so that the image data S
3 (908) is the address signal S5 of the even pixel memory 23.
Is written to the specified address 8. At this time, since the read enable signal S10 of the odd-numbered pixel memory 24 becomes 0, the image data S4 (20
1) is read from the specified address 8 of the odd-numbered pixel memory 24 by the address signal S6. Further, the selection signal S
Since 2 is 1, the image data S4
(201) is output. The time t is stored in the register 27.
Nine image data S3 (200) are stored and output as output image data.

The above operation is repeated in the same manner. FIG. 8 shows an image output operation timing for an image input on the tenth line.

Next, FIG. 2, FIG. 4, FIG. 5, and FIG.
The operation of converting from block sequential to raster sequential will be described using FIG. 9 and 10 and FIG.
In the timing chart of FIG. 1, signal names such as S1 to S10 correspond to the respective signals shown in FIG. 2, and "-" means "Don't Care".

First, in FIG. 9, when the page synchronization signal PSYNC becomes 1 and the line synchronization signal LSYNC becomes 1 from time t1, the image data 100 of the first pixel on the line 1 of the block 1 is synchronized with the rise of the system clock CLK. Is entered. At time t2, since the selection signal S1 is 0, the data bus 3
1 is image data S3 which is output data of the register 21
(100) is output, and at the same time, the write enable signal S7 of the even-numbered pixel memory 23 is 0, so that the image data S3 (100) is written to the designated address 0 by the address signal S5 of the even-numbered pixel memory 23.

At time t3, since the selection signal S1 is 1, the image data S4 (10) which is the output data of the register 21 is supplied to the data bus 32 via the demultiplexer 22.
1) is output, and at the same time, the write enable signal S8 of the odd-numbered pixel memory 24 becomes 0, so that the image data S
4 (101) is an address signal S6 of the odd pixel memory 24;
At the specified address 0. At time t4, since the selection signal S1 is 0, the image data S3 (102) which is the output data of the register 21 is output to the data bus 31 via the demultiplexer 22, and at the same time, the write enable signal S7 of the even-numbered pixel memory 23 becomes 0. Therefore, the image data S3 (102) is written to the specified address 1 of the even-numbered pixel memory 23 by the address signal S5.

During the above period, since the read enable signal S9 of the even-numbered pixel memory 23 and the read enable signal S10 of the odd-numbered pixel memory 24 are active, the initial value of the memory is output. From time t9, since the image data is block-sequential image data, image data 200 of the first pixel on line 2 of block 1 is input. The above operation is repeated in the same manner for eight lines.

In FIG. 10, even-numbered pixel memory 2
3 and the odd pixel memory 24 have the block 1 and the block 2
Are stored in a block-sequential image data for a total of 8 lines, and are read and converted into raster-sequential image data. From time t1, the line synchronization signal LSYN
When C becomes 1, the image data 900 of the first pixel on line 1 of the block 3 is input in synchronization with the rise of the system clock CLK. At the same time, the even pixel memory 23
Becomes zero, the image data S3 (100) of the first pixel on line 1 of block 1
Are read from the even-numbered pixel memory 23 from the specified address 0 by the address signal S5. Further, since the selection signal S2 is 0, the image data S3 (1
00) is output.

At time t2, since the selection signal S1 is 0, the image data S3 (90) which is the output data of the register 21 is sent to the data bus 31 via the demultiplexer 22.
0) is output, and at the same time, the write enable signal S7 of the even-numbered pixel memory 23 becomes 0, so that the image data S
3 (900) is the address signal S5 of the even pixel memory 23.
At the specified address 0. At this time, since the read enable signal S10 of the odd pixel memory 24 becomes 0, the image data S4 (10
1) is read from the specified address 0 of the odd-numbered pixel memory 24 by the address signal S6. Further, the selection signal S
Since 2 is 1, the image data S4
(101) is output. The time t is stored in the register 27.
One image data S3 (100) is stored and output as output image data.

At time t3, since the selection signal S1 is 1, the image data S4 (90) which is the output data of the register 21 is sent to the data bus 32 via the demultiplexer 23.
1) is output, and at the same time, the write enable signal S8 of the odd-numbered pixel memory 24 becomes 0, so that the image data S
4 (901) is an address signal S6 of the odd pixel memory 24.
At the specified address 0. At this time, since the read enable signal S9 of the even-numbered pixel memory 23 becomes 0, the image data S3 (102) of the third pixel of the line 1
Are read from the specified address 1 of the even-numbered pixel memory 23 by the address signal S5. Further, since the selection signal S2 is 0, the image data S3 (1
02) is output. Further, the image data S4 (101) at time t2 is stored in the register 27 and output as output image data.

The above operation is repeated in the same manner. Time t
In FIG. 9, since the selection signal S1 is 1, the image data S4 (907), which is the output data of the register 21, is output to the data bus 32 via the demultiplexer 22, and at the same time, the write enable signal S8 of the odd-numbered pixel memory 24 becomes 0.
Therefore, the image data S4 (907) is designated by the address signal S6 of the odd pixel memory 24 at the designated address 3
Is written to. At this time, since the read enable signal S9 of the even pixel memory 23 becomes 0, the image data S3 (108) of the ninth pixel on the line 1 is stored in the even pixel memory 2
3 is read from the designated address 4 by the address signal S5. Further, since the selection signal S2 is 0, the multiplexer 26 outputs the image data S3 (108).
The register 27 stores the image data S4 (10
7) is stored and output as output image data.

At time t10, since the selection signal S1 is 0, the image data S3 (10) which is the output data of the register 21 is sent to the data bus 31 via the demultiplexer 22.
00) is simultaneously output and the write enable signal S7 of the even-numbered pixel memory 23 is 0, so that the image data S3 (1000) is written to the designated address 4 by the address signal S5 of the even-numbered pixel memory 23. At this time,
The read enable signal S10 of the odd pixel memory 24 is 0
Therefore, the image data S4 (1
09) is read from the specified address 4 of the odd-numbered pixel memory 24 by the address signal S6. Further, since the selection signal S2 is 1, the image data S
4 (109) is output. The image data S3 (108) at time t9 is stored in the register 27 and output as output image data.

The above operation is repeated in the same manner. FIG.
5 shows the image output operation timing for the image input of the line 3 of the block 3.

As described above, the even-numbered pixel memory 23 and the odd-numbered pixel memory 24 are provided, and when the even-numbered pixels are read from the even-numbered pixel memory 23, the input odd-numbered pixel data is written into the odd-numbered pixel memory 24. When reading odd-numbered pixels from the memory, the operation of writing the inputted even-numbered pixel data to the even-numbered pixel memory 23 is repeatedly executed, and the even-numbered pixel memory 23 and the odd-numbered pixel memory 24
The order in which the addresses are generated is made different at the time of writing and at the time of reading, so that image data input in raster sequence can be converted into image data in block sequence or image data in block sequence can be converted into image data in raster sequence. .

Focusing on a memory for storing image data, when converting from raster order to block order or from block order to raster order in 8 × 8 size, conventionally, image data for 8 lines is stored. While two possible memories are required, the image processing apparatus according to the present embodiment requires two memories each having a capacity of four lines capable of storing even-numbered pixels and odd-numbered pixels. Because it is good, the memory cost can be reduced by half. In the case of one memory, the operation speed is sacrificed. However, according to the image processing apparatus according to the present embodiment, the operation speed can be reduced at the same cost as in the case of one memory. Instead, it is possible to convert from raster sequential to block sequential or from block sequential to raster sequential.

[0042]

As described above, according to the present invention,
An even-numbered pixel storage unit and an odd-numbered pixel storage unit are provided, and when inputting even-numbered pixels from the even-numbered pixel storage unit, input odd-numbered pixel data is written to the odd-numbered pixel storage unit. The operation of writing the obtained even-numbered pixel data to the even-numbered pixel storage means is repeated, and the order of address generation of the even-numbered pixel storage means and the odd-numbered pixel storage means is made different at the time of writing and at the time of reading. It is possible to convert raster-sequential image data into block-sequential image data or block-sequential image data into raster-sequential image data without sacrificing the image data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a specific configuration of an image processing apparatus according to an embodiment.

FIG. 3 is a diagram showing raster-sequential image data.

FIG. 4 is a diagram showing block-sequential image data.

FIG. 5 is a diagram showing addresses of an even-numbered pixel memory and an odd-numbered pixel memory for 16 × 8 pixels.

FIG. 6 is a timing chart (part 1) illustrating an operation of converting from raster sequential to block sequential.

FIG. 7 is a timing chart (part 2) illustrating an operation of converting from raster sequential to block sequential.

FIG. 8 is a timing chart (part 3) illustrating an operation of converting from raster sequential to block sequential.

FIG. 9 is a timing chart (part 1) illustrating an operation of converting from block sequential to raster sequential.

FIG. 10 is a timing chart (part 2) illustrating an operation of converting from block sequential to raster sequential.

FIG. 11 is a timing chart (part 3) illustrating an operation of converting from block sequential to raster sequential.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Input means 12 Even pixel storage means 13 Odd pixel storage means 14 Control means 15 Output means 21, 27 Register 22 Demultiplexer 23 Even pixel memory 24 Odd pixel memory 25 Control circuit 26 Multiplexer

Claims (1)

[Claims] 1. 2n (n = n) from the beginning of input image data
0, 1, 2,...) And 2n +
Input means for selecting and inputting odd-numbered pixel data at the position of 1 (n = 0, 1, 2,...); Even-numbered pixel storage means for storing the even-numbered pixel data; and storing the odd-numbered pixel data. Odd-numbered pixel storage means, writes even-numbered pixel data to the even-numbered pixel storage means in synchronization with reading of odd-numbered pixel data from the odd-numbered pixel storage means, and reads out even-numbered pixel data from the even-numbered pixel storage means. Control means for synchronously writing odd pixel data to the odd pixel storage means; and even pixel data read from the even pixel storage means and odd pixel data read from the odd pixel storage means. An image processing apparatus, comprising: output means for selecting and outputting.