JPH01295568A - Picture element synthesis processing unit - Google Patents

Abstract

PURPOSE:To quicken the picture synthesis processing by extracting a picture element reference line and a picture element processing line corresponding to the said picture element reference line simultaneously and using the picture element reference line and the picture element processing line simultaneously so as to apply picture element synthesis processing. CONSTITUTION:A picture processing line 11 outputted from a picture input section 2 is stored in a line memory 5 by one line and a picture element reference line 12 is inputted to a picture element synthesis circuit 4 by one word next. Then 4-point logic synthesis by one word is applied. Since the picture element synthesis processing unit 1 applies synthetic processing to the picture element processing line 11 by one word and the picture element reference line 12 simultaneously at the reduction processing of a picture in this way, the picture element synthesis is processed very fast.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a pixel synthesis processor used in an image editing device or an electronic filing device that handles image information as an electrical signal quantized into binary levels of O and 1. Regarding.

[Conventional technology]

Conventionally, this type of pixel synthesis processor performs synthesis processing by sequentially extracting reference pixels in series with respect to pixels to be synthesized using software or hardware. That is, conventionally, when performing image reduction processing, pixel synthesis processing has been performed by extracting reference pixels for pixel positions after reduction processing.

[Problem to be solved by the invention]

The conventional pixel synthesis processor described above performs pixel synthesis processing by extracting reference pixels from the pixel position after reduction processing when performing image reduction processing. There is a problem that the processing time becomes long.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, it is an object of the present invention to provide a pixel synthesis processor that can speed up pixel synthesis processing by simultaneously using a pixel reference line and a pixel processing line. There is a particular thing.

[Means to solve the problem]

The pixel synthesis processor of the present invention includes a line memory for storing one line of pixel processing lines inputted by an image input section, and a pixel reference line that is taken in every predetermined word from the image input section, and a pixel reference line and a pixel reference line. a pixel synthesis circuit that takes in pixel processing lines of a corresponding number of words from the line memory, performs pixel synthesis processing using these pixel processing lines and pixel reference lines simultaneously, and then outputs the result to an image output section; A control unit that controls input/output of the pixel processing line to the line memory, specifies an operation mode of the pixel synthesis process for the pixel synthesis circuit, and controls output timing of the image output unit after the pixel synthesis process. It is characterized by

[Effect]

The pixel synthesis processor having the above configuration temporarily stores the pixel processing line input by the image input unit in the line memory, and when the pixel reference line is input to the pixel synthesis circuit, the pixel processing line corresponding to the pixel reference line is It is possible to take out the processing line from the line memory and input it to the pixel synthesis circuit, and perform pixel synthesis processing using these pixel processing lines and pixel reference lines simultaneously. Therefore, the time required for pixel synthesis processing is extremely short.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a pixel synthesis processor according to an embodiment of the present invention.

The pixel synthesis processor 1 includes an image input section 2 as shown in FIG.
and a pixel synthesis circuit 4 connected between the image output unit 3 and the image output unit 3;
The pixel synthesis circuit 4 includes a line memory 5 connected between the pixel synthesis circuit 4 and the image input section 2, and a control section 6 that controls the pixel synthesis circuit 4 and the line memory 5.

The pixel synthesis circuit 4 employs a four-point logic synthesis method as a pixel synthesis processing method. This four-point logic synthesis method is used to determine the white or black color of pixel N, that is, the zero or one of pixel N, by reduction processing, as shown in Figure 2.
This refers to the method of referring to the four points a6+ aInb, , b surrounding the . In order to perform this four-point logic synthesis method, the pixel synthesis circuit 4 includes a nearest neighbor synthesis section 4a, an AND synthesis section 4b, an OR synthesis section 4c, a majority I synthesis section 4d, and a majority decision I synthesis section 4d, as shown in FIG. (2) A synthesis section 4e is provided.

The nearest neighbor point synthesis unit 4a has a function of calculating N=a0...■. Note that the nearest neighbor point of pixel N is pixel N. However, it is actually quite difficult to determine the pixel value, so
In this embodiment, 30 is approximately used as the nearest neighbor point. Furthermore, the AND synthesis section 4b performs N"aa'al"
1) It has a function to perform the operation of o'l)+""■, and the OR synthesis section has N=a.

+al+b6+bl . . . has the function of performing the calculation of ■. Furthermore, the majority decision I combining unit 4d calculates that N=a, ・a
tHbo+a, ・bo・b, +b, ・b, ・a0+
b.

・ao・al...Has the function of performing the calculation of ■.

This formula ■ is expressed as N= if two or more of the pixels in all+ aIn bOr bI are white, that is, 0.
0, giving priority to white color. In addition, the majority decision combining section 4e performs Nz (a0+a, +b,) ・ (a, +
b0+b;) ・ (b, +b, +aJ ・ (b
I"ao+a+)... has the function of performing the calculation of ■.

This formula ■ is a 6+ a In 1) 6+ b I
If two or more pixels among the pixels are black, that is, 1, N=1, and this is a formula that gives priority to black.

The line memory 5 has a function of storing at least one pixel processing line 11 input from the image input section 2.

The control section 6 has a function of controlling the pixel synthesis circuit 4, line memory 5, and image output section 3 based on the signal from the image input section 2. For the line memory 5, the control unit 6 processes a pixel having the same bit width as the pixel reference line 12 from the inner memory 5 every time one word of the pixel reference line 12 is input from the pixel input unit 2 to the pixel synthesis circuit 4. Input/output control is performed so that one word is read out from the line 11 and inputted to the pixel synthesis circuit 4. The control unit 6 specifies an operation mode for the pixel synthesis circuit 4. That is, when it is desired to determine the pixel N by the calculation of the above equation 0, the pixel processing line 11 and the pixel reference line 12 are introduced into the AND synthesis section 4b to activate the calculation function of the AND synthesis section 4b. Further, the control unit 6 controls the output timing of the image after the pixel composition processing for the image output unit 3.

The image input section 2 is formed of a host CPU or a DMAC, and has a function of inputting and transmitting the pixel processing line 11 to the pixel composition processor 1 and then inputting and transmitting the pixel reference line 12. Further, the image output section 3 is formed of an image reducer or the like.

Next, the operation of the pixel synthesis processor 1 according to this embodiment will be explained.

When the nearest neighbor point, that is, the logic expressed by the above formula 0, is selected as the four-point synthesis logic, the control unit 6 specifies the operation of the nearest neighbor point synthesis unit 4a, and releases the other synthesis units 4b to 4e. do. As a result, the pixel processing line 11 outputted from the image input section 2 is outputted as it is to the image output section 3 via the nearest neighbor point synthesis section 4a.

When one of the above logical formulas ○ to ■ is selected as the four-point synthesis logic, first, one line of the image processing line 11 output from the image input section 2 is stored in the line memory 5, and then the next One word of the pixel reference line 12 is input to the pixel synthesis circuit 4.

At this time, for example, when formula 0 is selected as the four-point synthesis logic, the pixel reference line 12 is manually input to the AND synthesis section 4b. At the same time, by the action of the control section 6, the pixel processing line 11 corresponding to one word having the same bit width as the pixel reference line 12 is transferred from the line memory 5 to the AND synthesis section 4.
b. Therefore, four-point logic synthesis using the 0 formula for one word is performed in the AND synthesis section 4b. That is, in FIG. 2, pixel N is formed by four points ao bo b and aH.
In addition to determining (a-z, b-2+ b
-1n a-+).

(a-+, 1)-+, b(,,ao), H+ +,
Four-point logic synthesis is also performed for (a3.b3°b4.a4) at the same time. As a result, the lattice before the reduction process indicated by the solid line 8 is reduced to the lattice indicated by the broken line 10. Note that Q mark 7 indicates a pixel before reduction processing, and △ mark 9 indicates a theoretical selected pixel position during reduction processing. The output data at this time is output to the image output unit 3, and the output data corresponds to the composite pixel indicated by the cross mark 13 in FIG.

As explained above, the pixel synthesis processor 1 of this embodiment is
Pixel processing lines 11 of one word each during image reduction processing
Since the pixel reference line 12 and the pixel reference line 12 are simultaneously synthesized, the pixel synthesis process is performed extremely quickly.

In this embodiment, the four-point logical synthesis method is adopted as the pixel synthesis processing method, but it is not limited to this, and it is clear that any method that can process pixel synthesis processing in units of predetermined words may be used. be.

Therefore, in such a case, the number of line memories 5 is not limited to one, but may need to be provided in multiple stages.

〔Effect of the invention〕

As explained above, the pixel synthesis processor according to the present invention is
The pixel synthesis circuit is configured to simultaneously incorporate a pixel reference line and a pixel processing line corresponding to this pixel reference line, and perform pixel synthesis processing using these pixel reference lines and pixel processing lines at the same time. This has the effect of increasing speed.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing a pixel synthesis processor according to an embodiment of the present invention, and FIG. 2 is a diagram showing a four-point logic synthesis method performed by the pixel synthesis processor of FIG. 1. 1... Pixel synthesis processor 2... Image input unit 3... Image output unit 4... Pixel synthesis circuit 5... Line memory 6...・Control unit 11...Pixel processing line 12...Pixel reference line agent Patent attorney Yoshiyoshi Iwasa

Claims (1)

[Claims] (1) A line memory that stores one line of pixel processing lines input by the image input section, and a pixel reference line that is taken in every predetermined word from the image input section, and the number of pixels corresponding to this pixel reference line. a pixel synthesis circuit that takes in processing lines from the line memory, performs pixel synthesis processing using these pixel processing lines and pixel reference lines simultaneously, and then outputs the result to an image output section; It is characterized by comprising a control unit that controls input/output of a processing line, specifies an operation mode of the pixel synthesis process for the pixel synthesis circuit, and controls output timing of the image output unit after the pixel synthesis process. pixel synthesis processor.