JPS61282932A - Address counter control system - Google Patents

Abstract

PURPOSE:To reduce a program area and to raise the processing speed by discriminating designation of a program with the word length in accordance with the fact that all programs are generated and stored with determined word lengths. CONSTITUTION:The program stored in a memory (ROM) 1 of 1k steps X 32 bits is accessed in 32-bit units by an upper address decoder 42 and is sent to a selector part 2 and is stored. A decoder 3 discriminates the number of bits of an instruction to be executed by the stored program code and sends a prescribed signal to a PC control part 44. The PC control part 44 changes the counted value of lower two bits of a PC 411 by the prescribed signal and selects the prescribed instruction sent to the selector part 2 by this value, and the read of the program having plural kinds of word length (bit number) can be controlled thereby; and thus, the memory (ROM) 1 is used efficiently and the instruction processing is performed quickly.

Description

[Detailed Description of the Invention] [Summary] An address counter control method for a predetermined processor, comprising:
Corresponding to the fact that all stored programs are created and stored with a fixed word length (number of bits), each program is created and stored with the required word length (number of bits) and its designation is This makes it possible to reduce the program area and increase processing speed.

[Industrial application field]

The present invention relates to a device that uses a program counter to select a program from a program memory storing programs of various word lengths (bit numbers), and particularly to This invention relates to an address counter control method specified by multiple lower bits of a program counter.

When processing general-purpose digital signals with a processor that performs program control, there are two types of programs: a "compound instruction" program that executes multiple processes simultaneously, and a "compound instruction" program that executes a single process.
It is processing a mixture of "single instruction" programs.

These programs are stored in the program memory within the processor and retrieved and used whenever necessary. When a predetermined program is retrieved from such a program memory, an address counter is used to designate an address.

On the other hand, the word length (number of bits) of programs stored in the program memory varies depending on the content to be processed, but in general, various programs are stored with a predetermined word length (number of bits). There is.

It is expected that such a program will be stored in the minimum required word length (number of bits) and that the program will be used to speed up the execution of the processor.

[Prior art and problems to be solved by the invention] A general-purpose digital signal processing processor will be explained as an example of the prior art.

FIG. 4 is a block diagram illustrating a conventional example of a general-purpose digital processor, and FIG. 5 is a storage status diagram of processor processing programs.

General-purpose digital processor 6 (hereinafter referred to as DSP 6)
is implemented as an LSI, and FIG. 4 shows a block diagram of a part of it. Further, FIG. 4 shows a program memory (ROM) 1 storing a program for controlling the instruction execution procedure of the DSP 6, and a predetermined program outputted from the program memory (ROM) 1 which is selected and sent to the internal bus a. a decoder 3 that interprets instruction execution contents from a predetermined program output from the program memory (ROM) 1; and an address pointer that indicates an address for reading data stored in the program memory (ROM) 1. If the program command output from the program memory (ROM) 1 is a predetermined arithmetic instruction, a multiplier and a logical arithmetic unit execute the predetermined arithmetic instruction. It is composed of an arithmetic unit 5 and the like.

The above-mentioned DSP6 is high-speed and has a small program memory (R
One way to efficiently use OM) 1 is to combine instructions (compound instructions).

For example, the capacity of program memory (ROM) 1 is I
In the case of K steps x 32 bits, the 32 bits are divided into, for example, 16 bits as shown in FIG.
The other side stores "operation instructions" for the operation section 5.

Program memory (ROM) 1 stores various instructions such as compound instructions and single instructions, and the contents of these various instructions are stored in program memory (ROM) 1.
As a method of interpretation from the program read from the address counter 4, the least significant bit of the address counter 4 is incremented sequentially
The command read from the memory (ROM) 1 according to the address is interpreted by the decoder 3 and executed.

A DSP with an architecture that adopts such complex instructions
In the case of 6, the word length (number of bits) of one instruction generally tends to be large. On the other hand, among various types of processing, there are cases in which single instructions are consecutive without requiring compound instructions.

However, in a DSP6 that employs compound instructions even for a single instruction as described above, the program word length (number of bits) is the same as that of the compound instruction, and unnecessary areas are moved to non-operational areas as shown in Figure 5 (B). In addition, there is a problem in that the program memory (ROM) 1 is inefficiently used.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention.

Figure 1 shows the program memory (ROM) explained in Figure 4.
) 1, selector section 2. Dekoda 3. The address counter 4 increments the lower two bits based on the output from the decoder 3, outputs the result as a count value to control the selector section 2, and also stores the result in the program memory (ROM).
A program counter 41 (hereinafter referred to as PC
41), an upper address decoder 42 which outputs the upper 10 bit count value of the PC 41 as an address for accessing memory (ROM) 1, and an 8-bit controller 42 which stores the lower 2 bit count value of the PC 41 in the selector unit 2. It receives the output from the lower address decoder 43 and decoder 3, which outputs it as an address for selecting predetermined data from a plurality of data units, and controls whether the least significant bit is incremented or the second bit from the least significant bit is incremented. It consists of a PC control section 44.

(Operation) The program stored in step 1 x 32-bit memory (ROM) 1 is accessed in units of 32 bits by the upper address decoder 42 and sent to and stored in the selector section 2. The decoder 3 reads the stored program code. The number of bits of the instruction to be executed is determined based on the number of bits of the instruction to be executed, and a predetermined signal is sent to the PC control unit 44.

The PC control unit 44 displaces the lower two bits of the PC 41 using a predetermined signal, and uses this value to change the selector unit 2.
By selecting the predetermined command sent to
It becomes possible to control reading of programs having a plurality of word lengths (number of bits), thereby increasing the efficiency of the memory (ROM) 1 and speeding up instruction processing.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram for explaining this embodiment, and FIG. 3 is a diagram for explaining the operation of the program counter of this embodiment. Note that the same reference numerals indicate the same objects throughout the figures.

The selector unit 2 shown in FIG. 2 has a register 21 that sequentially stores 32-bit data (program) output from a memory (ROM) 1, and a register 21 that stores 8-bit data (program) out of the 32 bits. An 8-bit selector 22 selects from the register 21, and a 16-bit selector 23 selects 16 bits of data (program) out of 32 bits from the register 21.
and a 32-bit selector 24 that selects 32-bit data (program) from the register 21.

Next, the operation of this embodiment will be explained. It is assumed that when the selector section 2 is reset, it is set to select, for example, 8-bit data.

Also, the first few bits of the data (program) stored in memory (ROM) 1 are the data (program).
It has an instruction code area that displays the word length (number of bits).

8 sent from the selector unit 2 after this DSP 6 is reset
The decoder 3 sends a predetermined signal to the PC control section 44 based on the bit length code. Based on this signal, the PC control unit 44 increments the least significant bit (ie, the "A" portion) of the PC 41 as shown in FIG. 3(A).

Note that the PC control unit 44 inputs “A” in the lower two bits of the PC 41.
If part is incremented, 8-bit instruction, “B”
If the part is incremented, a 16-bit instruction will be selected, and if the "C" part, which is the least significant bit part of the 10-bit father value, is incremented, a 32-bit instruction will be selected.

Also, when each bit is incremented, the bits below it are controlled to maintain their previous state. On the other hand, the increment of the upper 10 bits is controlled and incremented sequentially by the PC control unit 44 so that the address one address before the lower 2 bits can be specified.

The count value of the upper lO bit is converted from memory (ROM) 1 by the address decoder 42 to the address to access the next data (program) location and sent, and the selection of the data (program) stored in the register 21 is completed. Immediately, the next data (program), i.e. the third
In this embodiment shown in Figure (B), 16-bit data (program) is sent.

Incidentally, when a 32-bit instruction is selected, incrementing of the lower two bits is stopped.

Next, the word length (number of bits) of the next data (program) is determined by 16 from the data (program) stored in the register 21.
When the bit is interpreted by the decoder 3, the PC control unit 44 increments the "B" portion of the PC 41, and the count value of the lower 2 bits of the PC 41 at this time is sent to the address decoder 43.

Address decoder 43 thereby accesses 16-bit selector 23 and sends a 16-bit instruction to internal bus a. Incidentally, the incrementing status of the I'C 41 and the status of the data (program) stored in the memory (ROM) 1 as described above are shown in FIG. 3(B).

That is, the first instruction in memory (ROM) 1 is an 8-bit instruction, which is converted into 8-bit data (program).
The decoder 3 interprets the first code and outputs "A" on the PC 41.
(the Q mark in FIG. 3(B) indicates the opening for incrementing), and the selector unit 2 selects 8-bit data (program) based on this count value.

In this way, the PC 41, which is displayed in 12 bits, is divided into the lower 2 bits and the upper 10 bits, and the meaning of each count value is waited for before accessing the memory (ROM) 1 and the selector section 2, thereby speeding up the processing of instructions. This makes it possible to use memory (ROM) 1 efficiently.

〔Effect of the invention〕

According to the present invention as described above, a plurality of word lengths (number of bits)
The instruction having the word length (number of bits) allows the instruction to be processed quickly and has the effect of increasing the efficiency of the memory that stores the instruction.

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the present invention, Figure 2 is a block diagram explaining this embodiment, Figure 3 is a diagram explaining the operation of the program counter of this embodiment, and Figure 4 is a conventional general-purpose digital processor. A block diagram explaining an example. Figure 5 is a storage situation diagram of a processor processing program. 1 is a program memory (ROM), 2 is a selector section, 21 is a register, 22 is a selector for 8 bits, and 23 is a selector for 16 bits. , 24 is a 32-bit selector, 3 is a decoder, 4 is an address counter, 41 is a PCL, 42 is a 1-hi address decoder, 43 is a lower address decoder, 44 is a PC control section, 5 is a calculation section, 6 is a DS
P. 7 principles of small firing

Claims (1)

[Claims] A program memory (1) storing a plurality of programs having various word lengths (number of bits); (number of bits); and a decoder (3) that determines how many bits the instruction is based on the word length (number of bits) of the program selected by the selector unit (2). In the processor device, an address counter (4) that controls the instruction type of a predetermined program output from the memory (1) using a plurality of lower bits of the word length (number of bits) constituting the instruction; a program counter (41) consisting of (N+M) bits, that is, upper N bits and lower M bits, and which changes counter values of the upper N bits and lower M bits according to information from the decoder (3); and the counter (41) an upper address decoder (42) that inputs the counter value of the upper N bits of the counter and converts it into an address for accessing the memory (1);
a lower address decoder (43) that inputs the counter value of the lower M bits of 41) and converts it into an address to access the selector section (2); An address counter control system comprising: a program counter control section (44) for controlling the displacement of a value, and selecting a corresponding program according to a change state of a lower bit of a counter value of the program counter (41).