JPS58150186A - System for controlling buffer memory - Google Patents

Abstract

PURPOSE:To shorten the time required for accessing a buffer, by converting physical addresses sent for the coincidence processing as store request addresses into assignment information, knowing the location of block to be subjected to the coindience processing in a buffer memory, and all block on the buffer memory corresponding to the given physical addresses allow to coincidence processing operation. CONSTITUTION:Addresses are received by address registers 111-113 through a bus 100-1, nd the stored content of a conversion table 300 is set in a register 310 in response to the addresses designatod by a part of D of a part and E of the address registers 111-113. An address converting means 200, when it is ascertained by a comparator 320 that no physical addresses corresponding to the logical addresses set in the address registers 111-113 exits, performs address converting operations in accordance with the indication from a buffer controlling means 700 and operates so as to give the address-converted physical addresses to the conversion table 300 through a bus 200-1.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a buffer memory control system that enables high-speed access through simple control to a large-capacity buffer memory in an information processing system.

A conventional computer system has a central processing unit and a main memory, and programs and data necessary for processing are stored in the main memory. As the number of these programs increases, the capacity of the main memory increases, and the access time increases accordingly. For this reason, a system is known in which highly used information is stored in a buffer memory with a smaller capacity as a copy of the main storage contents, thereby improving processing speed by reducing access time. There is. In such a system, the central processing unit first accesses the buffer memory IJ =i and accesses the main memory when the desired information is not stored in the buffer memory.

When this main memory is accessed, the accessed information is stored in the buffer memory. Here, the process of dividing a program into several parts and transferring the program between the main memory and a directly accessible buffer memory is called paging. Since the main memory is shared by many users, programs are replaced as needed. There is no need to consider whether your program will be divided like this. therefore,
Since the entire program does not need to be stored in main memory, the physical size of the device becomes irrelevant to the program user. When the programmer specifies a virtual address (1[17 addresses), the address is expanded from this virtual address through various tables to generate a physical (real) address.

Based on the concept of virtual addresses, the
The conventional storage ffi system proposed in Japanese Patent No. 36178 includes a buffer memory (not shown) and a buffer memory (not shown).
It includes a buffer directory 56 for storing address information for memory management, and an address conversion unit 46 for converting a virtual address, which is a logical address given from the outside, into a real address, which is a physical address.

The lower bit group of this sys address, that is, the intra-page address, is used as is as the lower bit group of the real address. Therefore, even if we try to increase the capacity of the buffer memory, there is a limit to the direction in which the addresses within the page can be increased.Therefore, we have no choice but to adopt a method of arranging so-called sets horizontally and increasing the number of cents. The disadvantage is that an increase in quantity occurs.

In order to solve these drawbacks, a memory system having a plurality of banka memories and a plurality of processors respectively corresponding to them is described in Japanese Patent Publication No. 53-25457. This system uses a management table, and if the existence of the information required for the buffer memory internal pressure is not recognized, it investigates the auxiliary directory and checks whether the information exists in all buffer memories including the buffer memory. It has a configuration that Therefore, even if the desired information exists in one of all buffer memories, the presence or absence of the information cannot be determined by just one direct access to the management table, and as a result, the time required to access the buffer increases. This has the disadvantage that this causes a decrease in performance. Furthermore, after checking the management table, it may or may not be necessary to check the auxiliary directory, and the control for this is also complicated.

OBJECTS OF THE INVENTION It is an object of the invention to provide an address buffer memory system which eliminates the above-mentioned drawbacks.

Another object of the present invention is to provide an address buffer memory system that realizes a buffer memory matching processing method that completely preserves the contents of a buffer memory where the same information may exist in a plurality of buffer memories. It is in.

DESCRIPTION OF THE INVENTION The system of the present invention includes a first field, a second field, and a third field, which are represented as either a logical address or a physical address in response to each instruction for accessing main memory. address information generating means for generating address information having a field; address converting means for converting a logical address from the address information generating means into a physical address; a conversion table means for storing a part of the storage contents of the main memory at the addresses specified by the first and second fields; buffer memory means for storing at an address estimated based on the second and third fields of information;

management table means for storing the same physical address corresponding to the storage content of the buffer memory means at an address specified based on the second and third fields of the address information in correspondence with the instruction;

Comparing means for comparing the physical address from either the address generating means or the translation table means with the physical address from the management table means.

means for determining whether or not the contents read from the buffer memory means are valid in response to the comparison result Kffi of the comparison means; and address generation means in response to a discrepancy between the comparison results of the comparison means The address information is stored block by block in correspondence with the instruction, with the same storage content as a part of the storage content of the main memory specified by the physical address from either one of the conversion table means and the content of the same block address. storage at the address of the banoffer memory means specified based on the second and third fields, and the same physical address corresponding to these storage contents based on the second and third fields of the address information corresponding to the second and third fields. and means for storing the data at the specified address.

In the present invention, when part of the address used as the address to the management table is different, even if the corresponding physical address is the same, the allocated storage location in the buffer memory is different. Part of the address is the same
In this case, if the corresponding physical address is also the same, the final buffer memory is managed only using the physical address, so that even if the other parts of the address are different addresses, they are considered to be exactly the same address. Configure it like this,
Enables the existence of multiple pieces of the same information in the buffer memory, making large-capacity buffer memories faster with simple control when using software that refers to the same physical address data at different logical addresses even though it is used infrequently. Accessible and working.

Furthermore, the 脣黴Fi of the present invention converts the physical address as a store request address sent for matching processing into specified information using an inverse conversion table, and determines and provides the position of the block in the buffer memory where matching processing must be performed. The object of the present invention is to operate to guarantee the normality of stored information to a temporary address buffer memory by performing a matching operation on all blocks in the buffer memory corresponding to a physical address.

Examples of the invention Next, the present invention will be explained in detail with reference to the drawings.

Referring to Figure #I1, the system to which the present invention is applied has main memories 11, 12, 13 . and 14. These main memories 11, 12 . Memory controllers 21 and 22 .IJ and 14 are connected by Km, respectively. It is composed of data transfer devices 41 and 42 and processing devices 31 and 321 connected to the memory control device 21, and data transfer devices 43 and 44 and processing devices 33 and 34 connected to the memory control device 21. Each of the line processing devices 31-34 includes a sofa memory control block 51-54.

Referring to FIG. 2, a first embodiment of the present invention includes an addressing device 100 . An address conversion means 200 for converting a logical address into a physical address, a conversion table 300, a buffer memory 400 for storing a copy of a part of the contents of the main memory, and a management unit for storing addresses for managing this buffer memory 400. table 500
, comparators 320.610, 620.630. and 64
0, buffer control means 7001 selection circuit 530, 650
and 710, memory controller 21. and register I
'll, 112, 113, 310, 510 and 520
It consists of

The addressing device 100. The conversion table 300, the buffer memory 400, and the management table 500 are stored in the processing device 1011 No. 3 described in FIG. 2 of Japanese Patent Publication No. 53-25457.
Conversion manual as shown) IJ 220, Cache 2
00. and fetch directory 210, respectively.

Next, the address format applied to the invention and its address generation will be explained in detail with reference to FIGS. 3 to 5.

FIG. 5 shows the processing units 31-34 of FIG.
5 is a diagram showing an address format used in this embodiment when requesting access to memories 11 to 14. FIG. Address generation using this address format is performed as follows.

Referring to FIGS. 3 and 5, at the first logical address LAD1, the J table is indexed from the system space to specify the software process.
The hp child table is indexed according to the contents of the table. Of the indexed P tables, 11Kjl)7' Process Control Blocks are retrieved. The starting address of the segment table word array is indexed by the word ASW specifying the address space in the indexed block. The segment type as an in-process address is then added to the negative address as a difference, and the contents of the table indexed by the addition result indicate the starting address of the segment table. The segment number for each type is added to this starting address, and the starting address of the page table is designated by the contents of the table indexed by this addition result. The intra-segment page number is added as a difference to this starting address, and the addition result indicates the starting address of the page. In the physical address, the page address, which is the first address, is formed as a group of upper bits, the block address within the page is formed as a group of middle bits, and the address within the block is formed as a group of lower bits.

Next, referring to FIGS. 4 and 5, at the second logical address LAD2, the first address of the G table is designated by the system pace. The system segment number is added to this starting address as a difference, and the result of this addition specifies the destination 1 [1] of the page table. A page number as an intra-segment address is added to this starting address as a difference. The content indexed by the addition result indicates the top address of the page. In the physical address, the page address, which is the first address, is formed as a group of upper bits, the block address within the page is formed as a group of middle bits, and the address within the block is formed as a group of lower bits.

Referring to FIG. 5, the logical address LAD1 of rattan 1 is:
Information (J) indicating a difference in the J table in a group of upper bits and a difference in the P table in a group in lower bits to specify a software process.

Segment type (S: beep) as in-process address 4-7) Segment for each type) number (T2 bits 8-
15), segment page number (P: bit 16-1
9), block i within the page (R: bits 20-26)
, and is used when making intra-block Pam-specific access, system segment number (G), page number' (P: bits 16-19') as intra-segment address.
), block number within the page (R: beep) 20-26),
and in-block byte address (bits 27-31)
It consists of The physical address PAD includes the page position (Q; bits 4-19) and the block number within the page (R:
bits 20-26), and intra-block byte addresses (bits 27-31). In addition, the temporary address given as the access request address includes these three types of address formats, and the address format type (
To), temporary addresses A, B, C, D, and E, an intra-page block number (R: bits 20-26), and an intra-block byte address (bits 27-31). In all address formats, the intra-page block number (R: bits 20-26) and intra-block byte address (bits 27-31) are in a common format, and when indicating the same information, always use the same value. have

Regarding the address format in this embodiment, the logical number of address types, bit separation positions, address information size and number of bits, etc. can be arbitrarily determined. Referring to Figure 'm6, the buffer control means 700 of Figure 2 is comprised of AND gates 7G1, 702 and 704, and an OR gate 703 which outputs a true signal and a complementary signal. The buffer control means 700 responds to a comparison result match signal sent from the comparison circuit 320 via the line 320-1 shown in FIG. The selection signal of selection circuit 710 is sent to 411700-2. This selection signal is determined depending on whether comparison circuits 610 and 620 detect a match or comparison circuits 630 and 640 detect a match. The control means 700 sends the selection signal to the mat 700-2 and! A data valid signal is sent to the processing unit 100 via 1700-3.

If the output of the selection circuit 650 is
40 does not indicate a match, it sends a memory request via edge 2131-3 to memory controller 21 instructing it to read the desired information from main memories 11, 12, 13 and 14.

Next, the operation of this embodiment will be explained in detail with reference to FIGS. 1 to 7. The address device 100 shown in FIG. 2 is composed of an instruction prefetch control section or an arithmetic control section (none of which is shown) in the processing units 31, 32, 33, and 34 shown in FIG. 11g1, and has an address format shown in FIG. An address specifying the type (To) is supplied. This address is supplied in response to each instruction from the registers in said processing units 31, 32, 33 and 34 of FIG. This is done in response to the instruction given from the above-mentioned register in order to read out instructions for performing operations from the main memory in addition to the instructions given from the register (87).
(See 100 in the figure).

The address is sent to address registers 111, 112 . . . via path 100-1k in FIG. and 113 (see 111, 112° and 113 in FIG. 7).

The conversion table 300 in FIG.
1,112. and a part of 113 and E (Pino)
12-19), a memorized answer is set in the register 310 (see 300 and 310 in FIG. Check information (To,
A.

B, C, D (Dk' 8 11) are provided to comparator 320, and physical address Q is provided to comparators 610 and 630. Note that the register 31o does not need to exist as a register.

In the conversion table 300, part of the information To, A, B, C, D, E, and E that is greater than or equal to the page number of the address is stored as an address, and the rest is stored as check information.

The comparator 320 uses the check information given from the conversion table 300 and the address registers 111, 112, and
and 1130 information (T, A, B, C.

bits 8-11 of D), and if they match, it is notified to the buffer side control means 700 via the path 320-1 that the physical address Q read from the Kh conversion f-pull 300 is valid. (See Figure 7, 320, 610, 630 and 640).

The address translation means 200 in FIG.
0, address registers 111, 112 and 113
If it is determined by a voice that detects a mismatch that corresponds to the logical address set in 300.

A management table 500 in FIG. 2 is a management table for the buffer memory 400, and address registers 111, 112.
．． and 113, E (Pino) 16-19) and R (bits 2O-26) are accessed as addresses, and the physical address Q is read corresponding to the two sets in the table, registers 510 and 520 respectively. (see 500, 510 and 520 in FIG. 7).

Here, as a feature of the present invention, the management table 50
R of the address information used as the address of 0
It can be shown that the other part, that is, the information in the physical address Q corresponding to the bit position corresponding to E in this embodiment, is also included in the physical address information stored in the management table 500. This is the bit position (4) above R that has the same information in each address format in the present invention.
To.

A, B, C, D, E, ...E) in this embodiment are used as addresses for the management table 500, and are also used as physical address information to be stored. Management table 5 by address
buffer memory 400 by making 00 accessible
capacity can be increased. Along with this, the physical address information that ultimately determines whether the information exists in the buffer memory 400 or not.

By including all information above the common R in each format, it is possible to ensure the determination of the presence or absence of information.

Comparators 610, 620, 630 in FIG. and 640
and a selection circuit 650.
0,630,640. and 650 is the management table 5
Comparators 610 and 630 compare the physical addresses Q corresponding to the two sets successively derived from 00 and the physical address Q read from the conversion table 300 (6 in FIG.
10 and 630). At the same time, the comparison means includes address registers 111, 112 . Oage 113
Comparators 620 and 640 compare the Q information (bits 4 to 19) of the physical address of , and the Q information of the two physical addresses read from the management table 500 (see 620 and 640 in Figure @7). Also, address register 1
Comparators 610, 620, 630 . and 6
40 is selected by selection circuit 650 and applied to buffer Ill8 means 700 (see 650 in FIG. 7). That is, when address type information To indicates a physical address format, the outputs of comparators 620 and 640 are selected; otherwise, outputs of comparators 610 and 630 are selected.

Referring to FIGS. 2 and 3, the buffer memory 40
0 consists of two cents, and the address register 111
, 112. and E (biy) 16 19 of 113
) and R (bits 20-26) as addresses. That is, the memory 400 has a storage capacity of 64 bytes 2 sets = 128 bytes (Kyo 1024). However, the capacity and number of sets of the buffer memory 400 may be arbitrary. A feature of the present invention is that the address to the buffer memory 400 is block specific information other than R (peer) 20 26), which is common to each address format.E (To, A; B, C.

D) (see 400 in FIG. 7).

Referring to FIGS. 2 and 6, the buffer control means 7
00 instructs the address conversion means 200 to convert the address if the address IUIJ information T0 of the register 111 indicates a logical address and the comparison result of the comparator 320 indicates a mismatch. In other cases, the physical address of the access request given by the address is the address register 111, 1.
12. In the top 113 or in the conversion table 300
Assuming that the information has been determined through the 1 selection circuit 650, it is determined whether the information successively output from the buffer memory 400 is correct or not based on the output of the 1 selection circuit 650. That is, if the comparison results of the comparators 610 and 630 indicate -at-, the selection circuit 710t is operated as the one desired by the pro-run selected from the seven nodes on the left.

If the output selection results of the comparators 620 and 640 indicate a match, the selection circuit 710 is operated assuming that the block δ read from the right set is desired (see 710 in FIG. 7). Furthermore, if both output selection results indicate a mismatch, it is assumed that the desired information does not exist in the buffer memory IJ 400, and the block continuous output operation is performed in the memory W.
ill 14] request the device 21. Of course, even if both output selection results indicate no-t, the buffer memory 4
There is a possibility that the desired block exists in another word in 00 (address J!4), but for the sake of simplifying control, the desired information is not examined in other words t in the management table 500. operate in such a way that it is assumed that there is no such thing. What makes this possible is that although it is logically possible to easily access the same physical address with different logical addresses, due to the nature of the software configuration, when viewed at the hardware level, This is due to the fact that such accesses are performed very infrequently. That is, even if the above configuration is adopted in which information of the same physical address corresponding to each instruction can exist at each corresponding address position in the plurality of buffer memories 400,
Substantially, there are few cases of duplicate installation of the same information, and the rate at which the capacity of the buffer memory 400 is substantially reduced is very small.

The present invention is provided with a buffer memory 400 and a management table 500t that are accessed using a temporary address, and the presence or absence of information in the buffer memory 400 is confirmed f! Configuring the system to use physical addresses has the advantage that the large-capacity buffer memory 400 can be accessed at high speed with simple control.

In the first embodiment described above, even if the configuration is such that information at the same physical address can exist in each position in a plurality of buffer memories corresponding to each instruction, it is actually a case of duplicate installation of the same information. There are few. However, when there are duplicate installations of the same information, if one piece of information is rewritten, it will no longer match the other pieces of identical information, and when the same location is specified from the processor, the information read out will be different, resulting in a bug. There is. A system that overcomes this drawback and enables more reliable operation is the second embodiment described below.

Referring to FIG. 8, the second embodiment of the present invention comprising the backup memory control block 51, 52, 53 or 54 of FIG.
In this embodiment, the buffer memory 400 and the selection circuit 71O1
Management table 500, store address device 1000° consisting of registers and selection circuits, reverse conversion table 800, comparators 610, 630° 910, 920, 930 and 94
0, match processing control unit 9001 selection circuit 8501 temporary address register 110. Conversion table 300. and a buffer control means 700.

300, buffer memory 400% and management table 5
00 is the processing device 101 shown in FIG. 2 of Japanese Patent Publication No. 53-25457, the conversion directory 220 shown in FIG. 3, and the cache 200. and fetch directory 210, respectively.

Referring to FIG. 9, the addresses used in this embodiment are the in-page block designation address (R: bits 20-26) and the in-block byte address (X: bits 27-31) that are common to each format. In addition, information specifying the page includes the page number (P: beep 4-19) for logical addresses, and the physical page designation (Q:
bits 4-19), and in the temporary address, the following information is address type information (To: bit 0) indicating whether it is a logical address format or physical address format, and a page specified address (A:
4-19).

Temporary address page designation information, +1 address building information T
The value is the same answer as the page number pt or the physical page designation Q, and both the logical address and the physical address are integrated and expressed as a circle.

The physical address is used as an address when accessing main memory. However, as is known in the prior art, the address to the main memory does not always have to be a physical address, but may be a physical address converted by a floating address register or the like, or may be converted by prefix conversion. Logical address is page number P
The page table provided by the software is accessed by , and the physical page designation Qt from this table is converted into a physical address by reading h.
7 Referring to FIG. 10, the buffer control means 70 of FIG.
0 is ANDKATE 701, 702 and 7051 or game) 70 (, 706 and 711, F/F 707, 7
08 and 709% selection circuit 712.716 and 71
7. It consists of registers 713 and 715, a decoder 714, and a replacement control circuit 718. When the address conversion in the conversion table 300 of FIG. 8 is valid, the selection instruction operation to the selection circuit 710 is the same as the above-described control operation of the buffer control means 700 shown in FIG.

However, 9610-1 and 630-1 find that the desired information is not stored in the buffer memory 400 in FIG.
When a comparison result mismatch signal given via the comparison result is successful, the F/Fs 707-709 are operated to send a set instruction signal and set data f to the register 1010 in FIG.
Send it to @700-4. Along with this, the write instruction signal and write data to each set of the inverse conversion table 800 are
Sent via 00-5. Let me explain this in detail.

In response to the output of F/F 707, inverse conversion table 800
The write operation to is as follows. Each set of addresses in the cough table 800 is determined by a replacement control circuit 71 that implements the data replacement algorithm of the buffer memory 400 using a logic circuit.
In response to the selection instruction signal from 8, the selection circuit 712 selects the address of the buffer memory 400 given from the management table 500 via @1501-1 and 502-1'i.
is selected and determined. Further, which of the four groups in the corpse table 800 is selected is determined by the output of the de:noder 714. The table 8 determined in this way
000 random access instruction memory is provided with the contents of register 715 via 1i1700-5. Note that before a write operation is performed in response to the output of the F/F 707, the output of the AND gate 705 is sent to the address register 1010 of the table 800 as an address point instruction No. m via the OAG) 706t. Said F/F 7
F/F 708 is set in response to the output of 07.

The output of this F/F 708 is sent to the 1ii 700-4 via the address register 1010 as an address cent instruction signal. Along with this sending, the selection circuit 716 selects 1m! from the register 110! 110-2
and 110-3t- the page and intra-page block specification address information Q and R given through 1117
It is set in register 1010 via 00-4. The output of F/F 708 sets F/F 709.

The output of the F/F 709 is provided to a decoder 714 via an audio signal 711. The decoder 714 receives an address signal i, @ which selects one of the four tables 80004.
700-5. At this time, the write data given to the table 800 via ll11700-5 is as follows.

It includes the v bit changed from %QI to 111, the real address Q1 converted by the conversion table 300, and the estimated information obtained from the temporary address register 110 and replacement control circuit 718+11).

Referring to FIG. 11, the inverse conversion table 8 of FIG.
One column in 00 is 4 random access memories 80
1-804. Each of these random access memories 801-804 is connected to the register 715 of the buffer memory control means 700 in Figure #110.
A write data terminal WD receives write data applied via the edge TOO-5 from the control means 700 of FIG.
A write enable terminal WE receives the signal tube write enable signal from the decoder 714 of the register 1010 to 1101.
0-2t- address terminal A receiving an address signal applied via
-1, 803-1 and 80-4. Random access in Figure 11
The memory normally outputs read data from the terminal RD. When writing, 4 is located in the row specified by the address signal.
A write enable signal is applied to one of the two random access number memories 801-804. Write data is provided to the random access memory seen at four of this signal. At this time, the continuous output operation is stopped.

Referring to FIG. 12, the matching processing control unit 900 of FIG.
is AND gate 901-908, F/F912-91
5. It is composed of Nant gates 909, 910° 916-926 and a gate 927 for generating a true signal and a complementary signal.

Comparison circuits 910, 920, 930, 940 to 1M91
0-1.920-1.930-1 and 940-1t-
The outputs provided through the flip-flops 912, 913, and 9 respectively manage the completion of the corresponding set of treatments.
Under the condition that 14,915 is 101, K is determined, and the invalidation processing or iu, the matching block data writing processing 11 instructs the selection circuit 850 to select each set that requires it, and writes to the necessary set. An instruction is sent to the management table 500 or buffer memory 400.

Referring to FIG. 13, store address device 1 of FIG.
000 are gates 1001 and 1002 that output a true signal and a complementary signal, and (and goo) 1003 and 1006,
F/F1004 and 1005゜nandogoo) 1007
, selection circuits 1008 and 1013 and register 10
09.1011.1012 and 1014.

The store address device 1000 receives the memory control device 21 and the store control unit 50 from the edges 2131-4 and 50-.
1, receives the matching processing request, matching processing address, and store data given through 1010, accepts the matching processing request according to the priority order, and stores the corresponding matching processing address and set instruction in the register 1010 (41111000).
-It-, and also sends the corresponding store data through string 1
It is sent as write data to the buffer memory 400 via 000-2.

Next, the operation of the second embodiment will be described in detail with reference to FIG.

First of all, IIS! Legs.

When attempting to access information in buffer memory 40θ, buffer memory 1J400. The location of the management table 500 is specified. Next, converter R300
and the physical address from the management table 500 are compared by the comparators 610 and 630, and in response to the comparison result, the buffer memory IIIJIM1 means 700 determines whether the information read from the buffer memory 400 is the one desired. The selection circuit 710t is activated to send information to the processing unit 100 via the selection circuit 710t via @700-2.
Comparison result from 0 - 1kK response and buffer memory 40
The output of the left side portion 401 of 0 is selected and sent to the processing unit 100. In response to a match in the comparison result from the comparator 630, the output of the right portion 402 of the buffer memory 400 is selected and sent to the processor ff1l$100.

Buffer control means 700 includes comparators 610 and 630
If the desired information does not exist in the buffer memory 400 based on the comparison result of It operates to read data from main memories 11, 12, 13 and 14 in the figure and provide it to buffer memory 400. The location within buffer memory 400 where the information newly stored in buffer memory 400 is to be stored is determined using a replacement algorithm known in the art. However, the position determined by the replacement algorithm is determined by which set 401 .
402, seven) 401.402 word position, buffer memory 400. It is determined by a temporary address (bits 19-26) which is an access request address given to the management table 500 as an address. Here, bit 19 of the temporary address may have different values even when the logical address and the physical address indicate the same information tm.

Therefore, there is a possibility that the same information is stored in the count position in the backup memory 400.

The buffer control means 700 newly controls the buffer memory 40.
When it becomes necessary to store information in 0, the physical address of the information to be stored is set in register 1010, and bit 1 is set.
9-26t-address is given to the inverse conversion daple 800, and Q (bits 4-19) of the physical address of the information to be stored and the position in the buffer memory 400 where it has been determined that the new information is to be stored. [t-Specification information S to be visited is given as a set as write data, so that the position in the inverse conversion table 800 that has been empty until now is written. Next, the physical address of the friend information that previously existed at the location in the buffer memory where it has been determined that it will be newly stored is extracted from the management table 500 and set in the register 1010. This register 1
The contents of 01O are given to the inverse translation table 800 as an address, and the real address Q and designated information in the inverse translation table 800 corresponding to the information that existed before, that is, the information that is about to be erased from the buffer memory 400. It is instructed to invalidate the pair with S, that is, to make it empty. The above control ensures that the inverse conversion table 800 stores data including a set of real address Q and designated information S regarding all information existing in the buffer memory 400.

Here, the new real address Q to the inverse translation table 800 is
In order to guarantee that writing of the combination of and specification information S can always be performed, the number of entries in the inverse conversion table 800 needs to be n times or more the number of entries in the management table 500. The value of n indicates that part of the temporary address used as the address of the buffer memory 400 is A (bits 4-19).
) is determined by how many bits it contains.

In this embodiment, since there is only one bit, bit 19, the number is n-2. Therefore, in the small embodiment, for c/)K where the number of sectors of the buffer memory 400 is 2, f
The number of sets in the fi conversion table 800 is doubled to four.

However, the management table 500 is always included in the inverse conversion table 800.
It is not necessary to prepare n times the number of entries, and it is also possible to install a small-capacity inverse conversion table 5oon in view of the performance deterioration due to the probability of overflow and the relationship with the hardware cover.

Buffer memory 400 in the fc1 season embodiment, [
Conversion table 800) The capacity, number of sets, data width of information handled in accessing the buffer memo 1J40G, etc. do not constitute the essence of the present invention, and various configurations can be considered.

Next, Figures 1 and 8 show the write operation to the main memory.
This will be explained with reference to the figures.

Writing to the main memory 11-14 is executed in response to a write instruction to the main memory 11-14. Main memo! If part of the contents of J11-14 is rewritten by the write operation, the contents of the buffer memory 400 in FIG. 8 and the main memo! Jl
This causes a discrepancy with the contents of 1-14. A general information processing system operates on the assumption that the contents of the buffer memory 400 are a copy of a portion of the contents of the main memo IJII-14. It becomes necessary to perform matching processing with the contents of the memories 11-14.

Next, the matching processing side, which is a feature of the present invention, will be explained with reference to FIG. 1, #I8, and @14.

The store address device 1000tt in FIG. 8 receives the physical address for matching processing sent via the memory control device 21 or the store control unit 5o-2131-4 and 5O-1t-, It is set in the register 1010, and if store data is sent, it is sent to the buffer memory 400 via the i-edge 1000-2 (21.50. in FIG. 14).
1000 and 1010). Note that the store control section is composed of an instruction prefetch section or an arithmetic processing section of the processing device.

The contents of the register 1010 in FIG.
is given as an address to the inverse translation table 800, and bits 4-18 are applied to comparators 910, 920, 930 and 9.
40 (1010.800,91 in Figure 14)
0,920,930 and 940 references N).

Each number in the inverse conversion table 800 in FIG. 8) 801°80
2.803 and 804 registers 810,
A set of physical address Q and specification information S is read and given to 820, 830 and 840 (810 and 8 in Figure @14).
20, 830 and 840).

Comparators 910, 920, 930 and 940t in FIG.
i, each set of physical addresses read from the inverse translation table 800 and the physical address of the register 1010 (bits 4-
18) and if they match, the buffer memory 40 stores the information indicated by the store address.
Notify the match processing control 5900 that it contains valid specification information S specifying a position within 0 (91O in FIG. 14).
2920, 930 and 940).

Matching process 111J 11 part 900 and selection circuit 8 in FIG.
The matching processing control means consisting of a comparator 910°9
20. When a match is indicated from 930 and 940, matching processing is performed on the corresponding blocks in the buffer memory 400 for all nine sets.

That is, the match processing system @l@900 sequentially performs the following filim' for all pairs that are shown to be matched. First, specifying information St-registers 810, 820° 83 for matched pairs.
The selection circuit 850 selects from 0 and 840.

Further, the selection circuit 53 (lf!
．． 850 and 530). Next, if the store data is given to the buffer memory 400 from the store address device 1000, the store data is written to the position in the buffer memory 400 specified by the specification information S, and if the store data is not given, The matching process is performed by writing the invalidity information of the corresponding block in the buffer memory 400 to the entry at the position in the management table 500 specified by the specification information S (40 in FIG. 14).
0 and 500). In this way, the information in the buffer memory 400 is completely guaranteed. Note that when a block of the buffer memory 400 is invalidated,
Although it is necessary to invalidate the corresponding set in the inverse conversion table 800, that is, to make it empty, this method is performed in the same middle stage as the invalidation of the previous information that occurred when new registration to the buffer memory 400 was described above. .

In this embodiment, the designation information S is Pino) 19-26 as a temporary address and Nan) 50 of the management table 500.
1.502, and bits 19-26 of the temporary address are stored in the management table 50.
0 and as an address to the buffer memory 400, and the specification information is used as a set specification when the matching processing control unit 900 issues a write instruction to the management table 509 or the buffer memory 400. However, the format of the specification information S may be in a form other than that in this example.

For example, it may be given as a temporary address, as long as the corresponding entry in the management table 500 can be specified.

Effects of the Invention In the present invention, the buffer memory 400 of information corresponding to the physical address for matching processing is stored using the inverse conversion table 800.
By knowing the internal storage locations and performing matching processing on all of them, there is an effect that the validity of the information stored in the temporary address backup memory, which can store a plurality of pieces of the same information, can be guaranteed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a system configuration to which the present invention can be applied. FIG. 2 is a diagram showing a first embodiment of the present invention, and FIGS. 3 and 4 are diagrams for explaining address generation applied to the present invention. FIG. 5 is a diagram showing the address format adopted in the first embodiment of the present invention, FIG. 6 is a diagram showing a part of the first embodiment in detail, and FIG. 7 is a diagram showing the details of the first embodiment. FIG. 8 is a diagram showing a second embodiment of the present invention. Fig. 9 is a diagram showing the address format used in the second embodiment, Figs. 1O to 13 are diagrams showing some details of the W42 embodiment, and Fig. This is a diagram for explaining the operation. 11, 12, 13.14...Main memory, 21.22...Memory control device, 31゜3
2.33.34...processing device, 41.42,4
3゜44...data transfer device, 51', 52,
53.54...Buffer memory 1tllJIi
Block, 30... Processing section, 50...
Store'WIJ@@1100...Address device, 110...Temporary address register, 101゜1
02...Pants Amemory set, 200...
... Address conversion means, 300 ... Conversion table, 400 ... Buffer memory % 500
...Management table, 700...Buffer controller L718...Replacement control circuit, 800...
...Inverse conversion table, 900 ... Matching processing control unit, 1000 ... Store address device,
111,112,113,310,510,520゜7
13.715,810,820,830,840,10
09°1010.1011,1012,1014...
...Register, 801.802,803,804...
...Random access memory, 320, 610, 6
20,630,640,910゜920.930.94
0... Comparator, 530,650°710.71
2,716,717,850,1008°1013...
...Selection circuit, 707,708,709,912゜913.914,915,1004.1005...
...F/F. 714...decoder, 927,1001.10
02...Gate, 701. 702.704
．． 705.901゜902.903.904.905
．． 906.907゜908.1003,1006...
...And Gate, 909.910,916,917
,918°919.921,922,923,924,
925°926, 1007----Nandoke, 703°706.711....Orgate. η 2 Figure ′ 'jA 4 Figure η S l S 61 η 7 Figure y q Figure] 6 Turn lθ V:, /θ Firm 72 Ifl η /J Figure

Claims (2)

[Claims] (1) Generate address information represented by either a logical address or a physical address and having a first field, a second field, and a third field in response to each instruction for accessing main memory. (17) Address conversion means that converts the logical address from the 7 address information generation means into a physical address. conversion table means for storing the physical address converted by the address conversion means in addresses specified by the first and II2 fields of the address information; Buffer memory means for storing contents of the same block address in units of blocks corresponding to the instructions at addresses estimated based on the second and third fields of the address information. management table means for storing the same physical address corresponding to the storage content of the buffer memory means at an address designated based on the second and third fields of the address information in correspondence with the instruction; and the address generation means; comparison means for comparing the physical address from either one of the translation table means and the physical address from the management table means; means for determining whether or not the content read from the buffer memory means is valid in response to the comparison result of the comparison means; The storage contents are the same as a part of the storage contents of the main memory specified by the physical address from either the address generation means or the conversion table means in response to a discrepancy in the comparison result of the comparison means; storing the contents of the same block address in units of blocks corresponding to the instructions in the addresses of the bathophore memory means designated based on the second and third fields of the address information; A buffer memory control system comprising: means for storing the same corresponding physical address in an address specified based on the second and third fields of the address information corresponding to the instruction. (2) A main memory that stores information block by block at a storage location specified by a physical address given from the outside, and either a logical address or a physical address in response to each instruction to access the main memory. On the other hand, the same contents as a part of the storage contents of a plurality of blocks stored in block units in the main memory are stored in the storage location specified by the address information expressed on the one hand, in block units corresponding to the block units, and the above-mentioned buffer memory means for storing in correspondence with an instruction; and a management tape for storing a physical address indicating a block of the conobuffer memory means in a storage location specified by the address information in correspondence with the instruction; a write address generating means that generates a write address in the form of a write address generating means; a part of a physical address indicating a block stored in the buffer memory means; and a specification specifying a storage location of the management table means in which the physical address of the block is stored. inverse translation table means for storing a plurality of pairs of information in storage locations specified by the write address from the write address generation means; and part of the physical address from the write address generation means and from the inverse translation table means. a comparison means for comparing the part of the physical address of the wrinkled physical address read from the inverse translation table in response to a match between the comparison results of the comparison means; and means for applying information to at least one of the management table means and the buffer memory means to invalidate information in the corresponding block or write information to be written into the main memory into the corresponding block of the buffer memory means. A buffer memory control system characterized by: