JP2595753B2 - Invalidation method of cache memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory device, and more particularly, to processing of a valid bit of an address array.

[Conventional technology]

Generally, a cache memory is managed in units of blocks. For example, if one block is 64 bytes in size, a cache memory with a cache capacity of 64 kbytes has a capacity of 1 block.
An address array is needed to hold k addresses. When a plurality of processing units share the main memory, there is a valid bit array indicating the validity of the cache memory having the block address specified by the address array.

The configuration of this type of conventional valid bit array is the third.
This is shown in the block diagram of FIG. When an arithmetic processing unit accesses a cache memory, a valid bit is used to check whether a memory block to be accessed is valid.
Reading out the stored contents of the array 21 is performed. FIG. 7A illustrates a read operation, in which the storage contents of each storage element of the valid bit array 21 are respectively m0 and m.
Shown by 1, ..., mn. At this time, since the write enable terminal 23 is "0", the column address port
Storage element 21a of the block address specified by 25
Is output to the read data port 24. Next, when another arithmetic processing unit rewrites the main storage device, if the rewritten contents of the main storage device are cached, it is necessary to reset the valid bit of the corresponding block address. FIG. 8B illustrates the write operation. Since the write enable terminal 23 is “1”, the content m1 of the storage element 21b at the block address specified by the column address port 25 is “0”.
Is rewritten as As described above, whether to read a valid bit or write "0" is determined by setting the write enable terminal 23 to "0" or "1".

[Problems to be solved by the invention]

However, in the above-described conventional invalidation method of the cache memory, reading and writing of the valid bit are switched by switching the signal of the write enable terminal, and therefore, these cannot be executed simultaneously.
That is, when there is a request to write “0” for invalidation of a valid bit from another arithmetic processing device at almost the same timing as one arithmetic processing device reads a valid bit to access the main storage device, These two operations could not be executed in the same machine cycle. Therefore, one of the operations is executed with a delay of one machine cycle, and the processing time is wasted.

The present invention solves such a conventional problem, and provides a cache memory invalidation method capable of reducing the processing time by enabling the two operations to be executed in the same machine cycle. The purpose is to do so.

[Means for solving the problem]

In order to achieve the above object, according to the present invention, in a computer system having a main storage device shared by a plurality of arithmetic processing units and a cache memory, a write column address port and a read column address port are provided. In addition, an address array indexing operation for accessing a cache memory from a certain arithmetic processing unit, and "0" to the address array by a cache matching process from another arithmetic processing unit other than the arithmetic processing unit are provided. The write operation is executed in the same machine cycle.

(Operation)

Since the present invention is configured as described above, the valid bit read of the block address from the arithmetic processing device input from the read column address port and the read from the other arithmetic processing device input from the write column address port are performed. And writing of the block address to the valid bit can be executed in the same machine cycle.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration in one embodiment of the system of the present invention. In FIG. 1, A is an arithmetic processing unit that has requested access to the main storage device, B is another arithmetic processing device that has rewritten the main storage device, and C is the same block as the memory block that has been rewritten by the other processing device B. In the flash array unit for checking whether or not it exists in the cache memory, D
Reference numeral denotes an address array unit for indexing a memory block requested to be accessed by the arithmetic processing unit A. D is a register D1 for holding an address of a memory block requested to be accessed by the arithmetic processing unit A, and a 128-column address of the memory block held in the data array unit E
An address array D2 held at four levels, 128 columns indicating the valid state of the memory block, a four-level valid bit array D6, and a memory block requested to be accessed by the processing unit A are present in the data array unit E. A comparator D3 for determining whether or not to perform the operation, an AND gate D5 for calculating the logical product of the output of the comparator D3 and the output of the valid bit array D6, and a register D4 for holding the output of the AND gate D5. You. The flash array section C includes a register C1 for holding the address of a memory block rewritten by another processing unit, a flash array C2 having the same configuration and the same contents as the address array D2, and an invalid memory block. A comparator C3 for examining the level to be performed,
It comprises a register C4 for holding this level and a register D7 for holding the column address of the invalid memory block.

Next, the operation of the above embodiment will be described. The address of the memory block requested to be accessed by the arithmetic processing unit A is held in the register D1, and the register is registered in the next machine cycle.
The address array D2 is indexed to see if the block address held in D1 exists in the data array section E.
At the same time, the valid bit array D6 is read to check whether the memory block of the block address requested for access has been invalidated by the cache matching process, and the read memory contents and the data stored in the register D1 are stored. The logical product with the block address is taken by the AND gate D5 and stored in the register D4. When another arithmetic processing unit B rewrites the contents of the main storage device, the address of the rewritten memory block is changed to the flash array unit C.
To the register C1. In the flash array section C, the flash array C2 is indexed to check whether the memory block held in the register C1 exists in the data array section E, and if it exists, the register holding the level of the invalid memory block The write enable terminal D63 of the valid bit array D6 of the address array unit D is set to "1" via C4. Further, the valid bit of the block address corresponding to the column address specified by the register D7 holding the column address of the invalid memory block is rewritten to “0”. If the timing at this time coincides with the timing of reading the valid bit array D6, it can be executed in the same machine cycle.

Next, with reference to the detailed configuration of the valid bit array D6 shown in FIG. 2, it will be described that it can be executed in the same machine cycle. Write enable pin of valid bit array D6 at the corresponding level with the output from register C4
D63 becomes “1”. At this time, designation of a column address for reading based on an access request from the arithmetic processing unit A at the reading column address port D66,
Even if the column address specification for invalidation processing from another arithmetic processing unit B at the write column address port D65 is simultaneously occurring, the storage element D specified by the read column address port D66
The operation of outputting 61b to the read data port D64 and the operation of writing “0” to the storage element D61a specified by the write column address port D65 are executed in the same machine cycle.

Therefore, according to the above-described method, since the read column address port D66 and the write column address port D65 are independently provided, the reset of the valid bit can be performed without interrupting the memory block access request. Operations can be performed simultaneously.

〔The invention's effect〕

According to the present invention, as is apparent from the above embodiment, the reading and writing of the valid bit of the address array can be executed within the same machine cycle, so that the access operation of the cache memory of the arithmetic processing unit is interrupted. There is an effect that the cache matching process can be executed without performing.

[Brief description of the drawings]

1 and 2 are block diagrams showing the configuration of an embodiment of the system of the present invention, and FIG. 3 is a block diagram of a conventional system. A: arithmetic processing unit, B: other arithmetic processing unit, C:
Flash array section, C1, C4 ... register, C2 ... flash array, C3 ... comparator, D ... address array section, D1, D4, D7 ... register, D2 ... address array, D3 ...... Comparator, D5 ... And gate, D6 ... Valid bit array, D61 ... Storage element, D62 ... Write data port, D63 ... Write enable terminal, D64
…… Read data port, D65 …… Write column
Address port, D66: Read column address port, E: Data array section.

Claims (1)

(57) [Claims] An arithmetic processing device comprising a main storage device shared by a plurality of arithmetic processing devices and a flash array for cache matching processing from another arithmetic processing device, comprising: a write column / address port;・
A valid bit array comprising an address port and a register capable of writing and reading in the same machine cycle; an address array provided in an address array unit; and an address array for invalidating the valid bit array. A flash array that is provided in the flash array unit independently of the address array and stores the same contents as the address array; and a write enable of the valid bit array based on a search result of an invalid address of a cache memory stored in the flash array. Means for connecting the terminals,
An address array indexing operation for accessing a cache memory from a certain arithmetic processing unit, and a valid bid of the address array by a cache matching process from another arithmetic processing unit other than the arithmetic processing unit. A write operation of invalid information to a section in a same machine cycle.