JPH0194459A - Buffer memory controller - Google Patents

Abstract

PURPOSE:To reduce a propagation delay and to reduce the input/output pins of a package by dividing a TLBRA and a BAA into plural parts by means of index logical addresses of respective columns and storing the parts mutually probable to be simultaneously indexed into areas in which information can be transmitted and received in a high speed. CONSTITUTION:An address converting mechanism TLB and buffer address array BAAs 62 and 72 are divided into plural pairs by the index logical addresses of respective columns, and at least actual address storing part TLBRAs 61 and 71 of the address converting mechanism TLB probable to be simultaneously indexed for respective pairs, the buffer address array BAAs 62 and 72 and actual address comparing circuits 63 and 73 are stored into areas, for example, LSIs 60 and 70 in which the information can be transmitted and received in the high speed. Thus, the propagation delay can be reduced, and the number of the pins can be reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a buffer memory control device.

[Conventional technology]

Recent large-sized and medium-sized computers use both virtual storage and buffer storage. The virtual memory system is a system that allows programmers to code without being aware of the size of real memory, and the programmer is given logical addresses on virtual memory rather than real addresses on real memory.

On the other hand, in the puffer memory method, a high-speed, small-capacity buffer memory is arranged between the central processing unit and the main memory to form a memory hierarchy in order to compensate for the gap between the main memory, which has a large capacity but is slow compared to the calculation speed. It is a method.

In the virtual memory method, it is necessary to convert a logical address into a real address before referencing the main memory.

Conversion of a logical address into a real address is performed by referring to an address conversion table on the main memory prepared by the program, but if the slow main memory is referred to each time, the overhead of address conversion is large. Therefore, an address translation buffer (hereinafter referred to as TLB: Transl.
tion Lookaside Buffet), and when the main memory is referenced, the corresponding logical address is ThI4.
It checks whether the address exists in the address, and when it does exist (the probability of this is very high due to the locality of the program), the real address can be obtained quickly.

In the buffer storage method, since the buffer storage is a copy of a part of the main memory, K is a buffer address array (hereinafter referred to as BAA: Buf) to store the correspondence relationship.
fer Address Array) is arranged. When the central processing unit starts a main memory reference with a logical address, the real address translated by the TLB is
It is checked whether the data exists in the AA, and if it exists (the probability of this is very high due to the locality of the program), the corresponding data is read out from the buffer storage at high speed and sent to the central processing unit.

In the above explanation, the TLB and BAA are referenced serially, but in order to speed up processing, it is necessary to reference them in parallel. In this case, the BAA is referenced by the logical address. Depending on the system, some systems perform BAA column indexing using the real address part (in-page address) within the logical address, while others perform the BAA column indexing using the logical address (including the in-page address). In the latter method, there is overlap in the column index address pits of the TLB and BAA.

FIG. 2 is a block diagram showing an example of a buffer storage device that references the TLB and BAA in parallel.

A memory request request generated by the central processing unit stores a logical address in register 91.

TLB at the lower pit of the page address of the logical address
92 relevant entries are indexed. In this example, TLB9
2 consists of 20 columns, 92-1 is the 10th column,
92-2 indicates the 20th one. That is, there is a set of entries for each of the 10th and 20th entries. Each entry in each row 92-1, 92-2 of the TLB has a logical address (
L) part, a valid flag/pit part (V), and a real address part (R). TLB logical address part of TLB
, the real address part is called TLBRA.

The contents of the L section and the 7 section read from each row of the TLB 92 are sent to the corresponding logical address comparison circuit 94-1.94-.
2 is compared with the upper pit of the page address in register 91.

The BAA is indexed by the upper pit of the address within the page.

In this example, BAA 93 consists of 2 columns x 20 columns, 9
3-1 and 93-2 indicate the 10th and 20th.

That is, each row has L sets of entries. Each entry in the BAA 93 consists of a real address field (FL) and a valid flag/pit field (V).

The real address comparison circuits 96-1 and 96-2 are the selection circuits 9
'l', l, which is input through 5, 3392
The real address (in-page address) read from the R part of -1 or the real address (in-page address) stored directly in the register 91 by the central processing unit and the corresponding 8M93
-1.

The contents read from the R section of 93-2 are compared. The selection circuit 95 selects the contents of the register 91 when the central processing unit directly stores the real address in the register, and selects the contents of the register 91 when the central processing unit stores the logical address in the register 91.
Select the content of 1. The other real address comparison circuit 97-
1.97-2 compares the real address read from the R section of TLB 92-2 and the real address read from the R section of the corresponding BAA95-1.93-2.

Each of the real address comparison circuits 96-1.96-2.97-
1.97-2 has an output of 111' when the two human forces match.

Real address comparison circuit 96-1.96-2.97-1.9
The comparison result by 7-2 is input to the encoder 98, and after being selected from the result 9 of the logical address comparison circuit 94-1. Stored. The in-page address of the register 91 is stored in the lower part of the register 99.

Thus, the buffer storage address corresponding to the logical address or real address stored in register 91 is stored in register 99. The data read out by indexing the buffer storage using the address of this register 99 is transferred to the central processing unit.

By the way, since the TLBq 2 and the BAA 92 require high speed and a certain amount of capacity, they are usually constructed of bipolar memory. A conventional example of a bipolar memory for such use is shown in FIG.

In Figure 3, input bins AO to A2 bins to As K
The applied address signals are decoded by an X address decoder 110 and a Y address decoder 114, respectively, and then sent to the memory via drivers 111 and 113.
Activate cell 112. In this example, memory cell 112
has a 64-pit configuration consisting of 8 pits x 8 pits.

One pit selected from memory cell 112 is sensed.
It is led to an output circuit 116 via an amplifier 115, and outputs read data from an output bin 'DO (data act) K.

It enters write mode when WE (write enable) is enabled. In the write mode, the input bin DI (data in) passes through the gate 117 and is ANDed with WE by the AND circuit 118 and 119.
The write 1 signal or the write 10&I signal is made valid by the output of 8 and 119, and a write command is issued to the memory cell 112 specified by the address 2 through the driver 113.

When used as the aforementioned TLB or BAA, this type of bipolar memory is arranged in a matrix to achieve a desired word width and bit width.

Now, in recent years, electronic computers have started to become larger and faster due to the development and improvement of ultra-high-density LSIs, and this trend is expected to continue in the future. In this way, while many logic devices such as arithmetic units are being made into LSIs and becoming faster, logic parts including bipolar memory have a gate that spreads addresses to bipolar memory and converges data read from bipolar memory. LS accounts for the majority of that
It is difficult to convert it into an integrated circuit, so its effects cannot be utilized, and there is a strong possibility that it will become a critical bus that limits the machine cycles of one child computer. Furthermore, there is a tendency for the capacity of the main memory to increase, and therefore there is a need for an increase in the capacity of the backup memory. That is, an increase in bile capacity is required. On the other hand, the integration of bipolar memory is progressing, and high-speed memory is also becoming possible. It is not easy to construct a large capacity BAA using a conventional bipolar memory having the configuration as shown in FIG. 3 because the number of backage bins of the bipolar memory increases significantly.

By the way, if the pit memory is configured with 64 words in 4, it can accommodate 64 pits, but the required number of bins reaches 140 bins for both address lines and data lines, and the back cage size of bipolar memory is The number of output bins is reduced by t611.

Japanese Patent Publication No. 57-57784 discloses a device that uses a memory with a built-in number of comparisons to configure a TLB and an applicant's t-type. For example, attempts are being made to solve this problem by incorporating a memory chip into the area surrounded by the dotted line in FIG.

[Problem that the invention seeks to solve]

Japanese Patent Publication No. 57-57784 discloses that the real address read from the TLB is output from the memory chip that makes up the TLB, and then input to the memory chip that makes up the BAA. compared to the address. Therefore, there is a problem that the number of bins required for input/output of the TLB and BAA and the propagation capacity increase.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a storage control device which eliminates the above-mentioned conventional problems and reduces global gaming problems and input/output bins of backup cages.

[Means for solving problems]

The purpose of the above is to divide TLBRA and &S into index logical addresses for each column. This is achieved by

[Effect]

In the present invention, since the TLBRA and the controller are built into one LSIK, propagation delay and the number of bins can be reduced, and the TLHRA is
and BAA are split, so 'I'LBRA.

Even if the capacity of m people is large, the above-mentioned glopage, delay and reduction in the number of bins can be achieved.

〔Example〕

-An embodiment of the present invention will be described below with reference to FIG. .

In the figure, numbers 1 to 31 indicate the bit positions of addresses, and the area surrounded by a square with broken lines is an area where information can be exchanged at high speed. For example, this corresponds to one LSI, and in the following explanation, LSI60, LSI
70. The other numbers above 40 are reference numbers attached to each component.

In FIG. 1, the logical address for instruction fetch or operand fetch is set in register pile 40 for logical addresses. This logical address is 1 to 31
It consists of 31 bits. Also, the directory of entries registered in the address translation buffer is TLBLA,
The data portion that stores the real address is called TLJ3RA. A buffer address array that holds real addresses of data held in buffer memory is called BAA. Backup memory is called BS.

The logical address set in IJAR40K accesses the address translation buffer, buffer address array, and buffer memory. The address conversion package is 20-,
The columns are indexed by bits 12-19 of the logical address, but are implemented differently in FIG. 1 as described below. The buffer address array is 160-, with columns indexed by bits 18-24 of the logical address, but is implemented differently in Figure 1, as described below. T.L.B.
II (By storing A and BAA f in the same LSI, 40- data is read from the BS, but
One row of data can be selected from among them at high speed. When TLBRA and BAA cannot all be stored in one LSI, it is necessary to divide TLBRA and BAA and store them in several LSIs. The purpose of the invention is to demonstrate this method of division.

The column index logical addresses of TLBRA and BAA are
TLs where 18.19 are common and these two pits are different
Since the BRA and BAA columns are never indexed at the same time, the combination of TLBRA and BAA can be divided into up to four groups. In FIG. 1, column index logical address bit 19 is 10" and TLBI(A, BAA
Divide into two parts and convert the 'I'LI3RA, BAA O part where bit 19 is indexed by 10'' to LSI 60K
, TLBRA, BA where the pictogram is indexed by
Part A is stored in the LSI 70. TLBRA 6
1.71 is indexed by logical address bits 12-18,
BAA 62.72 is logical address bit 18°20
-24. The read real addresses are compared by comparators 65 and 75, and the matched row numbers are encoded by encoders 64a64b, 74a, and 74b. T.L.B.
LIA 51 is indexed by logical address pins 12-19. Read logical address bits 1-10 and LA
The logical address pins 1-11 set in R40K are compared by the comparator 52, and the matching number is sent to the encoder 5.
Code with 3. Encoders 64a, 64b, 74α
, 74b is output by selector 80! , R40K set logical address bit 19 and encoder 53
One is selected based on the combination of outputs. The bit 19 is go M.

At this time, the output of encoder 744.74b is invalid.

Conversely, when bit 19 is 1-, encoder 64α,
The output of 64b is invalid. When the TLBLA match signal output from encoder 53 indicates low 0, the outputs from encoders 64b and 74b are invalid. Conversely, when the coincidence signal indicates low 1, the encoder 64eL.

The output of 744 is invalid. The match signal of the RAA selected by the selector 80 is 10 out of 40- of the outputs of B582.
- is selected by the selector 82, and 8 bytes of data is output.

FIG. 1 shows a buffer memory control device for instruction or operand fetch. B58 also during operand store
A circuit for determining which row of 40-1 to enter is constructed based on a similar concept. In addition, when the logical address set to the date 40 is not registered in TI, B, after obtaining the real address corresponding to the logical address by well-known means, the real address register 41 (hereinafter abbreviated as RAR) After setting K and determining the row to be replaced using, for example, an LRU algorithm, the TLBLA stores the logical address pictographs 1-11 in the rows of the columns specified by the logical address bits 12-19, and the TLBRA:
If logical address bit 19 is 10'', TLB) tA6
1 K, if the bit is '1'', TLBRA71 i
C logical address pits 12-18 are set in the corresponding row of the column specified by the actual address pits 41 and 1).
-19 is stored.

In addition, when the block specified by the logical address set in BAA K LAR40y is not registered, the logical address is converted to a real address using TLB and set in RAR+41, and the row to be replaced is set using the LRIJ algorithm, for example. etc., if the logical address pit 19 is 10", then BAA62 K, '1
“Then, in BAA72, logical address pit 18.20-
The real address pits 1-19 set in RAR41K are stored in the row of the column designated by 24. Also Bs
A block specified by the logical address set in LAR40K is transferred and stored in B1.

〔Effect of the invention〕

According to the present invention, data corresponding to a given logical address can be read from and written to a buffer memory at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a buffer memory control device showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional example, and FIG. 3 is a block diagram showing the configuration of a bipolar memory. . 40: Fetch logical address register (LAR)
, 51...Address translation buffer directory (TL
BLA), 61.71... Address translation buffer data section (TLBRA), 62, 72... Buffer address array (BAA), 60.70... Area where information can be exchanged at high speed, 81... Buffer memory (B
S), 91...address register, 92...address translation buffer, 93...buffer address array.

Claims (1)

[Claims] 1. A buffer memory that stores part of the information stored in the main memory, a buffer address array that stores the real addresses of each block stored in the buffer memory, and a read request and a write request that are logically In an information processing device having an address translation mechanism that converts a logical address into a real address when an address is issued, the logical address of the access request is converted into a real address converted using the address translation mechanism and the buffer address array. In order to quickly detect a match with a stored real address, the address translation mechanism and the buffer address array are divided into a plurality of sets by the index logical address of each column, and each set is simultaneously indexed. A buffer memory control device characterized in that at least a real address storage section, a buffer address array, and a real address comparison circuit of a possible address translation mechanism are stored in an area where information can be exchanged at high speed.