JPS6265151A - Memory control system - Google Patents

Abstract

PURPOSE:To attain an instantaneous access to a main memory device in case the same user gives accesses to the same page by providing a function into an address converting mechanism ATB to deliver the control information to a present logic address. CONSTITUTION:A CPU 1 delivers a logic address to an ATB 20 serving as the 1st memory control mechanism. The ATB 20 converts the supplied logic address into a physical address and at the same time delivers continuously the present control information 306 in case the same user gives accesses to the same page. While a TLB 30 serving as the 2nd memory control mechanism delivers the next control information in case the CPU 1 is not executing the same page through the same user. Thus an instantaneous access is possible to a main memory device 2 in case the same user gives accesses to the same page.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a memory management system including an access protection function in a high-performance microcomputer system that can realize virtual memory using a paging method by converting logical addresses to physical addresses. In particular, the present invention relates to a memory management system that can speed up access to a main memory by including a part of a page access determination mechanism within an address translation mechanism.

[Traditional technique]

With advances in integrated circuit technology, personal computers, microcomputers, etc. have become more sophisticated, and 32-bit microprocessors have come into practical use. Various peripherals for 32-bit microprocessors
The importance of SI is increasing.

Among them, the memory management unit (MMU) is particularly important. The MMU is a unit that executes memory management such as virtual memory and memory access protection functions.

In a virtual storage system, gigabytes of virtual space can be used by a dynamic address translation mechanism.

The concept of virtual memory has already been realized in large-scale computers, and the memory space is divided into pages or segments, which are collections of pages. It dynamically converts the main memory into a physical address to be accessed and checks whether the converted address is on the main memory to realize a large memory space. That is, the dynamic address conversion mechanism of a large computer draws a segment table from an address that is the sum of the contents of the segment start register in the CPU and the segment number in the logical address, and calculates the contents of the page table start address and the logical address. Add the page number to the page table to find the first address of the desired page. The real address obtained by adding the intra-page displacement within the logical address to the first address of the obtained page becomes the actual address of the storage device.

If the page at the accessed address is in the main memory, the main memory is accessed using the real address, but if the page to be executed does not exist, the page is transferred between the main memory and the disk device. I'm trying to do a swan big page.

In this case, the page to be swapped out is selected from pages that have not been used in an optimal amount by using an LRU algorithm (least recent use). Furthermore, five large-scale computers have a multi-process function, and even if multiple users commonly access one main memory, they can be controlled in a time-sharing manner, allowing one user to access only one absolute I am trying to access the address space. When a plurality of user areas share a main storage device, each area has a prefix conversion mechanism that converts the real address space into an absolute address space so that each area has a different real address space.

In order to provide a 32-bit microcomputer system with the virtual memory function and access protection function used in such large computers.

Memory management by the MMU is configured to have at least a paging address translation mechanism and a memory protection function. As a protection function, 1. For example, each page has an attribute that indicates how that page can be accessed in the conversion table, and each entry in the table has 2 protection bits that define the form of access. ing. for example.

These two protection bits are used to check whether the main storage device can be accessed in supervisor mode and user mode.

FIG. 2(a) shows a system configuration diagram of a conventional memory management method including an address translation mechanism, prefix translation, and page access control. The central processing unit CPU1 outputs a logical address including at least a page number and an intra-page displacement to the logical address bus 10. In addition, when the data bus 11 writes data to the main memory device 2, it outputs the write data, and when it reads data from the main memory device 9, it inputs the read data. It is connected to the. In addition, in order to execute the prefix conversion mechanism so that the main storage device 2 can be shared and accessed by multiple users, management information for processes executed by each user is required.

(In the case of Pi, a 3-bit CPU access level signal is output from the CPU to the signal line 12. The logical address 10 output from the CPU 1 is output from the address translation mechanism ATB.
(Address Table Block), and is input as a physical address to the address terminal of the main storage device 2 via the physical address bus 201. The physical address 201 is transferred to the main storage device 2, and at the same time is sent to the tri-state latch circuit 202 as link information.
T L B (TableLink Bloc
k) F is also input. In the TLB 30, the upper bits of the physical address set in the latch circuit 202 are input, and it is checked whether or not the page corresponding to the upper bits is currently in the main memory 2, and whether the page is in the main memory 2. In this case, the management information indicating the process identification (PID) for that page, that is, the user designation of that page, is sent to the management information bus 301.
Output to. Additionally, if there is a page in the main storage device 2 that includes the physical address output from the ATB 20,
In order to change the physical address 201 to an absolute address that can be distinguished by a plurality of users, the upper address bits indicating the start address of each user area are applied from the TLB 30 to the upper address line of the main memory device 2 via the tri-state buffer 302. The check circuit 40 inputs the management information 301 including the user-specified PID output from the TLB, further inputs the CPU access level signal 12 indicating at which user level the CPU is executing from the CPU, and checks the physical address 201. The same physical address as TL
If the physical address is in B, a check is performed to see if the physical address is the physical address of the user being used by the CPUI. As a result of checking, if physical address 201
is in main memory 2, and its address is
If the area belongs to the user using the I, the output 401 of the check circuit 40 becomes active, acts on the memory access control circuit 50 and the CPUI, and the CPU
accesses the main memory device 2 to execute a read or write operation. If the logical address 10 output from the CPUI is changed to the physical address 201 by the ATB 20,
, and the page to which that physical address belongs is TLB
Even if the page is within 30, the management information for that page is bus 1.
If the access level information is different from the access level information issued in the main memory 2, the pages are different in the absolute address space of the main memory 2. In this case, the output of the check circuit 40 is
This is a signal that means a memory access prohibition command, and the CPU
I cannot access the main storage device 2, and at this time, in the TLB 30, the management information regarding the user with the same physical address is transferred to the check circuit 40 and the buffer, respectively, and the physical address starting information pointing to the starting address of the user area is stored in the TLB 30. 302, the page to which the physical address that is the output of the ATB belongs is searched within the TLB 30. As a result of the search, if the page to which the physical address 201 belongs does not exist in the main storage device 2, the page to which the physical address 201 belongs is transferred from the external storage device, that is, the disk device, to the main storage device 2 as a page fault,
Transfer less-needed pages to a disk device. This will perform a so-called swap operation. The operation flow in such a conventional MMU is shown in FIG. 2(b).

In FIG. 2(b), the CPU outputs 8 remaining addresses 10 in order to access the memory which is the main storage device 2. This logical address 10 becomes an input to the ATB 20. The ATB 20 converts the logical address 10 into a physical address and outputs it to the physical address bus 201. Even when the physical address 201 is input, the main storage device 2 does not perform the read/write operation. The upper bits of the physical address 201 are set in the latch circuit 202 as link information to access the TLB 30. T.L.B.
30, when the link information is input, the physical address 201
It outputs the corresponding PID management information to the buffer 301, and also outputs the physical address start information, which is the upper bit for indicating the start of the user area, to the buffer 302.

and.

The check circuit 40 compares the management information output from the TLB 30 and the access level signal 12 indicating user designation from the CPUI to determine the appropriateness of memory access. If the access is proper, an OK double signal is output to the output line 401.

The physical address 201 and the physical address head information output from the TLB 30 are given as the upper bits of the absolute address of the main storage device 2 to execute the memory read/write operation and return to the original state.

In the check circuit 40, if the management information from the TLB 30 is different from the user-specified access level signal of the CPU, memory access cannot be performed and the TLB
The page to which the physical address on 201 belongs in 30 is TL
It is necessary to check whether there are any more in B.

If there is, the output from the ATB 20 is stopped. Then, the TLB 30 outputs next physical address head information indicating the head of the next user area having the same physical address to the buffer 302Φ.

In ATB20, instead of the current physical address 201, T
The next physical address equivalent to that output from the LB 30 is registered once, and the same operation is executed for the TLB 30 by outputting the physical address in a cyclical manner. If the physical address existing on 201 does not exist in TLB 30.

Indicates that the page no longer exists in main memory 2. At this time, a page fault occurs.

The MMU notifies the CPUI that the corresponding page does not exist, and
The PUI suspends memory access and performs page swapping according to, for example, an LRU algorithm.

In this way, in the conventional MMU system as shown in FIG. 2(a), the physical address 201 corresponding to the current logical address IO output from the CPUI is
0, and the TLB 30 is accessed using the physical address 201.

The outputted management information 301 is used to check user specifications. Therefore, even if the page to which the logical address 10 outputted from the CPUI belongs is located in the main storage device 2, and is certainly specified by the user who is executing the CPUI, the page configured from the RAM is Since the PID check is performed through two stages of memory consisting of the ATB 20 and TLB 30, access to the main storage device 2 has the disadvantage that access to the main storage device 2 is actually slow. That is, according to the conventional method, the physical address 201 output from the ATB 20 is.

Even if the user specifications are the same, the main storage device 2 cannot be accessed immediately, and access is only possible after inputting the management information 301 output from the TLB 30 to the check circuit 40. Therefore, when the physical addresses are the same but the users are different, or in a steady state other than a page fault, the conventional method has the disadvantage that address translation is slow in execution.

[Purpose of the invention]

The present invention eliminates such drawbacks of conventional MMU and enables AT
If the same user is accessing the same page by providing a mechanism in B that outputs management information for the current logical address.

To provide a memory management method that can immediately access a main storage device using a physical address converted from the logical address, ignoring the management information output from the TLB. In order to achieve the above purpose, the central processing unit (1
) and the logical address (10) output from the central processing unit (1) into a physical address (201), and at the same time, the current management information (306) regarding the current user regarding the converted physical address (201). The first memory management mechanism (20) to output and the converted physical address (201) are input as link information, and the page containing the physical address (201) is transferred to the main memory (
2), at least information for converting the physical address (201) into an absolute address including user area designation, and next management information (305) regarding the next user regarding the physical address (201). Mechanism to output.

and a second memory management mechanism (30) including at least a mechanism for detecting whether a page including the physical address (201) exists in the main storage device (2), and the first memory management mechanism (30). 20) said current management information (30)
6) and selectively inputs the next management information (305) of the second memory management mechanism (30) and inputs the current management information (3).
06) and the next management information (305) and the central processing unit (
1), and a comparison means (40) for comparing the access level signal (12) for user designation outputted from the central processing unit (1), and corresponds to the current logical address (10) outputted from the central processing unit (1). While accessing the page to which the physical address (201) belongs in the same process, the operation of the second memory management mechanism (30) is ignored and the main page is immediately accessed at the current physical address (201). Storage device (2)
and if the current management information (202) output from the first memory management mechanism (20) is not the same process, the second memory management mechanism (30) that inputs the link information Next management information to be output (30
This is achieved by providing a memory management method characterized by converting a physical address (201) into an absolute address based on 5).

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1(a) shows an MMU based on the memory management method of the present invention.
FIG. 2 is a block diagram showing the configuration of FIG.

The central processing unit CPUI outputs a logical address including at least a page number and an intra-page displacement to the logical address bus 10. In addition, the data bus 11 outputs write data when writing data to the main memory device 2, and inputs read data when reading data from the main memory device 2. Connected to CPUI. In addition, in order to execute the prefix conversion mechanism so that multiple users can coexist and access the main storage device 2, the management information of the process executed by each user is sent from the CPU as a 2, for example, 3-bit CPU access level signal. It is output from the CPUI to the signal line 12. c? The logical address 10 output from u1 is sent to an address translation mechanism ATB (Address Table Blo
ck) 20, and becomes the address input of the main storage device 2 via the physical address bus 201 as a physical address. In the present invention.

A part of the page access determination mechanism is included inside this ATB 20, and management information PID 202 indicating the current user designation for the converted current physical address 201 is transmitted to the TLB 3.
The signal is output directly from the ATB 20 without going through the 0, and is input to the check circuit 40. The physical address 201 is transferred to the main storage device 2, and at the same time is transferred to the main storage device 2 as link information via the tryst circuit 202.
Link Block) is also input. In the TLB 30, the upper bits of the physical address set in the latch circuit 202 are input, and it is checked whether or not the page corresponding to the upper bits is currently in the main memory 2, and whether the page is in the main memory 2. In case.

Next user management information indicating the designation of the next user having the same physical address as the physical address 201 is output to the next user management information bus 303. The next user management information 303 is then output to the next management information 305 bus via the tri-state latch circuit 304. Additionally, if there is a page in the main storage device 2 that includes the physical address 201 output from the ATB 20, the first address of the user area is changed to change the physical address 201 to an absolute address that can be distinguished by multiple users. The upper bits of the indicated address, ie, the physical address head information, are applied from the TLB 30 to the upper address line of the main memory device 2 via the tristate buffer 302'.

The check circuit 40 selectively inputs current management information 306 and next management information 305 including process identification (PID) specified by the current user and specified by the next user outputted from the ATB 20 and the TLB 30, respectively, and further inputs the current management information 306 and the next management information 305 outputted from the ATB 20 and the TLB 30, respectively. A CPU access level signal 12 indicating which user level the CPUI is running at.
Enter.

A check is executed to see if the physical address 201 is the physical address of the user used by the CPU 1. As a result of the check, if the physical address 201 is in the main storage device 2, and the current management information 306 specified by the current user output from the ATB 20 and the user level signal 1 are
2 match and the address is in the area of the user using the CPU 1, the output 401 of the check circuit 40 becomes active immediately. That is, ATB2
The main memory device 2 can be accessed at the speed of a read cycle for a single stage RAM containing only 0's. The output of the check circuit 40 acts on the memory access control circuit 50 and the CPU 1, and the CPU 1 accesses the main memory 2 to execute read/write operations. At the moment when the logical address 10 output from the CPUI is changed to the physical address 201 by the ATB 20, even if the page to which that physical address belongs is in the TLB 30, the current management information 306 designated by the current user from the ATB 20 for that page
If the access level information is different from the access level information sent from the CPUI to the bus 12, the pages will be different in the absolute address space of the main storage device 2. In this case, the output of the check circuit 40 becomes a signal meaning a memory access prohibition command, and the CPU cannot access the main storage device 2. In this case, as in the past, the TLB 30 outputs the ATB signal. A search will be made for a page with a redundant physical address. Namely.

The next management information regarding the next user and the netast address start information indicating the start address of the memory area of the next user are searched while being supplied to the check circuit 40 and the three-state latch 302', respectively. As a result of the search, physical address 20
If the page to which 1 belongs does not exist in the main storage device 2,
As a page fault, the page to which the physical address 201 belongs is stored in the external storage device, that is, the disk device and the main storage device 2.
A swap operation will be performed between the two.

The operation flow in the MMU of the present invention is described in the first part.
Figure (shown in bl.

In FIG. 1(b), the CPU outputs a logical address 10 in order to access the memory which is the main storage device. This logical address 10 becomes the input to ATB 20. The ATB 20 converts the logical address 10 into a physical address and outputs it to the physical address bus 201. At the same time, current management information 3 indicating the current user designation for the current physical address 201 converted from the ATB 20
06 is output. The physical address 2 is stored in the memory 2.
01 is input as a part, but the read/write of the memory is not executed yet. The upper address of the physical address 201 is set in the launch circuit 202 as link information and the TLB 30 is accessed. When the TLB 30 inputs the link information.

Next management information 305 regarding the next user corresponding to the physical address 201 is output. At the same time, if the user designation is different for the same physical address as the physical address on the physical address bus 201, this next physical address head information is also output. In the check circuit 40, first, A
The current management information 306 output from the TB 20 and the access level signal 12 indicating user designation from the CPUI are
Comparison is made without going through B30 to determine the appropriateness of memory access. If the access is correct, an OK double signal is output to the output line 401, and the physical address 201 and ATB2 are
0 or the upper bit of the address indicating the beginning of the current user area outputted from the TLB 30 is applied to the address terminal of the main culprit memory W2, the memory read/write operation is executed, and the process returns to the original state. What if the starting address of the current user area was output from the ATB 20 instead of the TLB 30?

Bus 201 is considered an absolute address rather than a physical address. In the check circuit 40, if the current management information 202 from the ATB 20 is different from the access level signal 12 of the current user of the CPUI.

No memory accesses can be made, and only then,
It is necessary to use the TLB 30 to check whether the page to which the physical address on the physical address bus 201 belongs is in the TLB 30. If so, A
Stop output from TB20. Then, the TLB 30 stores next physical address start information in the buffer 302 to indicate the start of the next user area having the same physical address.
Output to. Furthermore, the next management information regarding the next user is outputted to 303, and the third-party latch circuit 304 latches it. The ATB 20 registers the next management information together with the next physical address equivalent to the current physical address 201 output from the TLB 30 instead of the current physical address 201, and performs the same operation on the TLB 30. in this case.

Instead of the equivalent next physical address, a next absolute address including the top address of the next user area as the upper bit may be registered. If the address on the physical address bus 201 does not exist in the TLB 30, this indicates that the page no longer exists in the main storage device 2.

At this time, a page fault occurs and the MMU.

The CPU 1 is notified that the corresponding page does not exist, and the CPU 1 suspends memory access and executes page swapping according to, for example, an LRU algorithm.

In the present invention, as described above, the logical address 10 output from the CPU is input to the ATB 20 and is simultaneously converted into the physical address 201.

Outputs memory/management information that is the same page as the page to which the logical address 10 belongs, which is currently in the main storage device 2 from the logical address 10, and has the highest probability of matching the PID of the user using the CPUI. line 202
This current management information 306 is output to the checkerboard circuit 40.
, and the position of the PID is immediately checked. Therefore.

In the present invention, in a steady state in which the CPUI always accesses the currently accessed page.

Since the page to which the logical address 10 of the main storage device 2 belongs exists, from the logical address 10 to the physical address 2
At the same time as converting to 01, current management information 306 for that logical address is output.

The access level signal 12 output from the CPUI and the checker circuit 40 can immediately match each other. Therefore, in the present invention, the read/write operation of the main memory device 2 is executed while ignoring the operation of the TLB 30. If the logical address 10 output from the CPUI always accesses the same page.

In this way, reading and writing of the main memory device 2 is executed at high speed, but if the logical address 10 output by the CPU is a different page, for example, when a different page is accessed by a jump instruction, the logical address 10 of the jump destination is the CP.
Output from U1.

In such a case, it is necessary to check the management information via the TLB 30 as in the past. That is, the TLB 30 is accessed using the converted physical address 201, and the next physical address head information and the ninth management information are output from the TLB 30. That is, the physical address 201
The next PID of the same page as the page to which the page belongs is output and input to the check circuit 40. Then, it is checked whether it matches the access level signal 12 output from the CPUI. TLB3
0 has a physical address corresponding to the logical address 10 output by the CPUI, and therefore, if that page exists on the main storage device, this indicates that there is a next candidate in the TLB. Therefore.

If there is a next candidate, the output of the ATB 20 is stopped, and next physical address head information corresponding to the next management information is set in the launch circuit 302'.

The next management information is sent to the latch circuit 304.

The check circuit 40 checks the PID again using the next management information. At the same time, the next physical address and next management information are registered in the ATB 20. Then repeat the same process again. If there is no next candidate in the TLB 30, a page fault will occur and the CPU will stop accessing the memory 2 and fetch the corresponding page from the disk device.

〔Effect of the invention〕

The present invention stores the correspondence between logical addresses and user-specified management information as a table in the ATB mechanism that converts logical addresses into physical addresses, and while the CPU is accessing the same page, the current It is immediately determined that the page being accessed is by the same user, and the speed of memory access is improved, resulting in the effect of increasing system throughput.

[Brief explanation of drawings]

FIG. 1 fat is an MMU based on the memory management method of the present invention.
FIG. 2 is a block diagram showing the configuration of. FIG. 1 (bl is a diagram showing the operation flow of the method of the present invention. FIG. 2(a) is a block diagram showing the configuration of an MMU based on the conventional memory management method. FIG. 2(b) is a diagram showing the configuration of the conventional memory management method. It is a diagram showing the operation flow of the system. ■... CPU. 2... Main storage device (memory). 10... Logical address. 11... Data bus and control bus. 12... CPLI access. Level signal. 20...ATB. 30...TLB. 50...Memory access control circuit. 202.302', 304...Three-by-three latch circuit. 301...Management information bus. 302... Three-state buffer circuit. 305... Next management information bus. 306... Current management information bus.

Claims (1)

[Claims] 1) A central processing unit (1) that outputs a logical address, and a central processing unit (1) that converts the logical address into a physical address.
When 1) is executed by the same user and the same page, the first memory management mechanism (20) that continues to output the current management information (306) and the central processing unit (1) are executed by the same user and the same page. A memory management system characterized by comprising a second memory management mechanism (30) that outputs at least next management information when the process is not being executed. 2) The central processing unit (1) and the logical address (10) output from the central processing unit (1) are converted into physical addresses (20
1) and at the same time converting the physical address (
Current management information (3) regarding the current user regarding (201)
06) A first memory management mechanism (20) that simultaneously outputs
Then, the converted physical address (201) is input as link information, and if a page including the physical address (201) exists in the main storage device (2), the user at least starts from the physical address (201). A mechanism for outputting information for converting into an absolute address including area designation and next management information (305) regarding the next user regarding the physical address (201), and a mechanism in which the page containing the physical address (201) is in main memory. a second memory management mechanism (30) including at least a mechanism for detecting whether the information exists in the device (2); and the current management information (306) of the first memory management mechanism (20) and the second memory management mechanism (30). The next management information (305) of the memory management mechanism (30) is selectively inputted, and the current management information (306) and the next management information (305) are output from the central processing unit (1) for user specification. a page to which the physical address (201) corresponding to the current logical address (10) output from the central processing unit (1) belongs; is accessed in the same process, the second memory management mechanism (
30) and ignores the operation of the current physical address (2).
01), and if the current management information (306) output from the first memory management mechanism (20) is not the same process, input the link information. A memory management method characterized in that a physical address (201) is converted into an absolute address based on next management information (305) output from the second memory management mechanism (30). 3) first comparing the current management information (306) output from the first memory management mechanism (20) and the process level (12) output from the central processing unit (1) using the comparison means; If they match, the main storage device is accessed immediately using the absolute address (201) output from the first memory management mechanism (20), and if they do not match, the converted physical address (201) is used. ) as link information to access the second memory management mechanism (30) and output the next next management information (305) regarding the physical address (201), and then output the next next management information (305) and the central processing unit. The process level signal (12) output from (1) is repeatedly compared by the comparison means (40), and the process level signal (12) outputted from the process level signal (12) is repeatedly compared with the user specified from the physical address (201) via the second memory management mechanism (30). 3. The memory management mechanism according to claim 2, wherein the memory management mechanism converts the address into an absolute address containing the address. 4) The memory management mechanism according to claim 2, wherein the first memory management mechanism comprises an ATB. 5) The memory management mechanism according to claim 2, wherein the second memory management mechanism comprises a TLB. 6) When the current management information output from the first memory management mechanism (20) and the access level signal (12) output from the central processing unit (1) do not match, and when the second
When the next management information (305) is output from the second memory management mechanism (30), the next management information (305) and the next physical address output from the second memory management mechanism (30) are 3. The memory management mechanism according to claim 2, wherein the memory management mechanism is registered with a first memory management mechanism (20). 7) Input the next physical address registered in the first memory management mechanism (20) to the second memory management mechanism (30) as next link information, and provide next management information (305) regarding the next user. 7. The memory management mechanism according to claim 6, wherein the memory management mechanism outputs next physical address head information for converting into an absolute address. 8) If the second memory management mechanism determines that the page to which the physical address belongs is not on the main memory, execute page fault control and create a new page on the external storage device that is to be accessed. 8. The memory management mechanism according to claim 7, wherein the memory management mechanism swaps old pages on the main memory.