JPS59180774A - Memory accessing system - Google Patents

Abstract

PURPOSE:To output and input information with a simple circuit configuration, by deciding an HOLD requesting instruction from a microprocessor by means of a priority decision circuit and accessing a local memory corresponding to another microprocessor. CONSTITUTION:An HOLD requesting instruction from a microprocessor mucpu1 is detected by a decoder D1 through a gate G1 and inputted into a priority decision circuit P. When another microprocessor mucpu2 accepts an HOLD requesting signal S3 and is set to an HOLD condition, a bus line L2 is set to a floating condition and the microprocessor mucpu1 accesses a local memory LM2 through another bus line L1. It is also possible to make the access from the microprocessor mucpu2 in the same way, but, when accesses conflict with each other, the priority decision circuit P makes only the HOLD requesting instruction from the microprocessor mucpu1 effective.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory access method that allows information to be exchanged between a plurality of microprocessors.

Prior Art Traditionally, information exchange between multiple microprocessors involves
There are two methods: one is to use a common memory provided on a common pass line, the other is to separate the pass lines and use each of the 10 ports. In the former method, access signals from multiple microprocessors are prioritized, and a microprocessor that is not given the right to use it is placed in a waiting state until another microprocessor relinquishes the right to use it, and this method requires a complex priority circuit. It had the following drawbacks. Moreover, the latter not only requires a large amount of hardware and a low data transmission speed.

The disadvantage is that the software for transfer is also complicated.

Purpose An object of the present invention is to provide a memory access method with a simple configuration by using a HOLD request signal line possessed by a microprocessor in order to exchange information between microprocessors in a roll memory provided for a microprocessor. It is in.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below in accordance with embodiments of the present invention shown in the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention. This example shows a case where the number of microprocessors is two in total, and the microprocessor μ
cpul and μcpu2 each have bidirectional gate Gl
and G2 to the pass lines L1 and L2. Further, local memories LMI and LM2 corresponding to each microprocessor are similarly connected to pass lines L1 and L2 via gates G1 and G2. A HOLD request command sent from the microprocessor to the pass line is detected by decoders DI and D2 connected to pass lines L1 and L2, respectively. The priority determination circuit P receives the detection signal S1 from the decoder D1.
is input! 8 wire j2H; HOLD demand signal S
3, and when the detection signal S2 from the decoder D2 is input, the HOLD request signal S4 is sent to the signal line ρ2. AND circuit G3 outputs 1-I OL D to macroprocessor μCpul!
When the ACK Shintan signal is input, back, line Ll
A signal is sent to the bidirectional gate G1 to make it floating. AND circuit G4 is microprocessor μ
HOLD signal S3 for cpu2 and HOL sent from microprocessor μcpu2 to signal line 4
When the D A CK signal S6 is input, the bidirectional gate G2 is activated so that the pass line L2 is in a floating state.
send a signal to.

FIG. 2 shows an example of the configuration of the priority determination circuit P in which the HOLD command from the microprocessor μcpul is given priority. The detection signal S1 sent from the decoder D1 is outputted to the signal line ρ1 as a HOLD request signal S3, and is also inputted to one input terminal of the AND circuit G5 via the inverter circuit INV. The detection signal S2 sent from the decoder D2 is input to the other input terminal of the AND circuit G5. The output signal of the AND circuit G5 is outputted to the signal 3-H, ρ2 as a HOr-D correction signal S4.

Next, the operation of the memory access method according to the present invention will be explained with reference to FIGS. 1 and 2. First, the case where the microprocessor μcpul accesses (reads/writes) the local memory LM2 will be explained.

The H OLD request command sent from the microprocessor μcpul to the pass line L1 via the bidirectional gate G1 is detected by the decoder D1, and a detection signal S1 is input to the priority determination circuit P. Priority judgment circuit P receives HOL D request signal%
S3 is connected to microprocessor μcpu2 and AND circuit G4
The signal is output through the signal 48 line ρ1. Microprocessor μcpu2 is HOLD! I received the request for reimbursement S3] (OL
When the state is set to D, the HoLD ACK signal S6 is sent to the signal line J24. When the HOLD request signal S3 and HOLD ACK signal %S6 are input to the AND circuit VδG4,
A signal is sent back to the bidirectional gate G2, the pass line L2 is set to a floating state, and the microprocessor μcp
ul accesses local 4-memory LM2 via path line L1.

Next, a case will be described in which the microprocessor μcpu2 accesses the local memory LMI. A HOLD request command sent from the microprocessor μCp u 2 to the pass line L2 via the bidirectional gate G2 is detected by the decoder D2, and a detection signal %S2 is input to the priority determination circuit P. The priority determination circuit P receives the HOLD request signal Jj+S/
Send I to 2 on the signal-vT line, and send the microprocessor μc
input to pul and AND circuit G3. Microprocessor μcpu1 receives HOLD request signal Ji+S4.
When in the OLD state, the HOLD ACK signal S5 is sent to the signal line ρ3 and input to the AND circuit G3. Then, the AND circuit G3 sends a signal to the bidirectional gate G1 to put the pass line L1 in a floating state, and the microprocessor μcpu2 accesses the local memory LM1 via the pass line L2.

HOLD request command from microprocessor μcpul and 1-IQ L from microprocessor μcpu2
If there is a conflict with the D request command, each HOL D
The request command is detected by decoders DI and D2, and the detection signal is input to the priority determination screen P.

Detection signal S1 is output as l-] (l L D 嬰过纬sign S3. On the other hand, detection signal %S2 is input to the input terminal of AND circuit G5, but detection signal S1 is output as AND circuit through inverter TNV. Since it is input to the other input terminal of the circuit G5, the AND circuit G5 remains closed and the power of the HOLD! command from the microprocessor μcpul becomes effective.

In the above embodiment, the case where the 11 microprocessor μcpu1 has priority over the microprocessor μcpu2 has been explained, but even when there are multiple microprocessors, the priority can be arbitrarily set by changing the gate configuration of the priority determination screen P. You can.

As explained in detail above, according to the present invention, it is possible to exchange information without using a particularly complicated priority judgment image, there is no need for a complicated priority judgment image, and the base line control configuration is also simple. It has the effect of

[Brief explanation of drawings]

FIG. 1 is a block diagram of the memory access method of the present invention, and FIG. 2 is a diagram showing the configuration of a priority determination screen in the above embodiment. μc p u l * μcpu2...Microprocessor, LM1, LM2...Local memory, LL,
L2...Pass line, G1. G2... Bidirectional gate, 03-G5... AND circuit, Di, D2... Decoder, P... Priority 1 determination circuit, INV..., f-sober-5 circuit. Patent applicant Ricoh Co., Ltd.-8=

Claims (1)

[Claims] In a memory access method for exchanging information between microprocessors, a plurality of microprocessors having a HOLD mode, a local memory corresponding to the microprocessors, and a priority judgment circuit are connected to each other by R-fHI L from the microprocessor. A HOLD request command is determined by a priority determination circuit, other microprocessors are placed in a HOLD state, and a local memory corresponding to the other microprocessor in a HOLD state is accessed from the microprocessor that sent the HOLD request command. Memory access method.