JPS58109915A - Data transfer controlling system of bus coupling system - Google Patents

Abstract

PURPOSE:To realized high speed control as a whole , by controlling all relating control variables via a bus only when the control variables are changed for the state, not controlling them in a uniform speed. CONSTITUTION:A processor CPU outputting control signal to a process input/ output device PIO5 has a common data memory CM2, and all the CM2 are accessed as virtual PIOs from the corresponding CPU1 and the content is made the same for all the CM2 via a buffer BUF3. A data transfer request memory TRSM7 is written with ''1'', when data from the CM2 corresponding to the CPU1 to the PIO5 are changed and when the data from the PIO5 in the unit driver UD4 to the CPU1 are changed. An address generator ADRG6 generates a specified address with the said request of the TRSM7 and controls the data transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer control method for a path coupling system, and particularly to a data transfer control method suitable for a load-sharing computer system that automatically selects and transfers necessary data.

A conventional method is shown in FIG. This method will be explained below. Each CPU (processing unit) has a common data memory 2 that has all of the PI 10 information and CPU linkage information, and when executing a CPU program, this common data memory 2 is used as the virtual PI 10 or the virtual linkage CPU. The data transfer is performed independently of the bus-coupled data transfer. Note that each common data memory 2 has the same contents because it performs broadcast communication by bus connection. The buffer circuit 3 is a drive circuit that simply enhances signal transfer and has no special function. The unit driver 4 has a bus-coupled transmitter/receiver circuit and a drive machine for the PI 106. The address generation circuit 6 plays a central role in the transfer operation, and sends addresses to each common data memory 2 and unit driver 5. This address is updated sequentially at regular intervals and is permanent. If the address generation circuit 6 now outputs oo3 to the address bus 12, the data shared memory 2 designated as output mode by address 003 outputs data. In this case, the common data memory 2 with number 1 sends out data, and the common data memories 2 with other numbers are designated to receive mode by address 003 and receive data. Similarly, the unit driver 4 also receives data and transfers it to the PI 105.

This method has a simple circuit configuration and is preferable in terms of reliability.

However, the address generation circuit 6 periodically outputs addresses regarding the entire robustness of the PI 10 address area, including addresses where the PI 105 is not mounted. For this reason, P
Transferring the state change of Ilo to the CPU causes a delay of the maximum scan time for one address, which has the disadvantage of being unsuitable for high-speed control. This is because the common data memory 2, as shown in FIG. This is due to the inability to select and output addresses.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed data transfer control method for a bus-coupled system using selective transfer of data.

For a large number of related controlled objects, based on the empirical rule that the proportion of controlled objects that require particularly high-speed control is small, do not control all related controlled objects at a uniform speed [, The present invention attempts to achieve comprehensive high-speed control by performing control according to control requests. Specifically, when a change occurs in the controlled object, only when a change is necessary is a report sent to the bus coupling device and data transfer is attempted. As a result, the load on the low-speed control object is reduced, and accordingly, high-speed control on the high-speed control object becomes possible.

Embodiments of the present invention will be described below with reference to FIGS. 3 to 12.

Figure 3 shows the overall configuration. 1 is the process input/output device vertical (
This is a processing device (hereinafter abbreviated as CPU) that calculates and outputs a K control signal (hereinafter abbreviated as PI10).

Reference numeral 2 denotes a common data memory (hereinafter abbreviated as CM) having all of the PI 10 information and linkage information between the CPUs. Each CM2 has the same memory content by performing broadcast communication through bus connection. 3 is a buffer (hereinafter referred to as B
(abbreviated as UF) circuit, which simply strengthens the signal. 4 is a unit + driver (hereinafter abbreviated as UD), which has a bus connection function,
Has PIlo drive function. 5 is PIlo.

6 is an address generation circuit (hereinafter abbreviated as ADRG), 0M
It reads address output requests from UD2 and UD4, and sends out a specific address based on this request. 7 is a data transfer request memory (hereinafter abbreviated as TR19M), which is built in 0M2 or UD4. In the CMZ, TRAM is connected from the corresponding CPUI to the PIlo
If there is a change in the data for s, this TR8M
In the UD, if there is a change in the data from PIlo to the CPU, write "1" to TR8M to request ADRG to send the address. It requests transmission and attempts to transfer data.

First, to explain the overall operation, each CPU is PI1
0! II and 0M2 for storing all linkage information between each CPU. Then, CPU program execution is performed by regarding this 0M2 as a virtual PI10 or virtual linkage CPU, and directly reading PI10s.
I have nothing to write about. Therefore, the contents of 0M2 are always KP
The content must be the same as I105 and other CMs.

A bus coupling device performs this function, with ADRG6 as the center, 0M2. BUF3. Consists of UD4. ADR
G6 reads the contents of TR8M7 in 0M2 or UDJ, and when determining that there is a data transfer request, sends out the requested address. This will be explained differently. If ADRG6 outputs 003 to the address bus 12, the output mode specified by address 003 is 0.
M2 outputs data. In this case, 0M2 with number 1 sends data, and 0M2 with other numbers is designated to receive mode by address 003 and receives data. Similarly, UD4 also receives data and transfers it to PI105. In this explanation, the functions of TR8M7 were ignored, but next, the functions of TR8M will be included in the description. The purpose of installing TR8M7 is to perform only necessary data transfer and prevent unnecessary data transfer.

In this example, ADRG6 is 00G, 010,020.
It is designed to output every 10 addresses in hexadecimal format. First, if address 000 is output, then address 000 in TR8M of the CM or UD having addresses 001 to OOF is read out. Fourth
As shown in Figure TR8M configuration diagram, assuming that only the 3rd bit is “L”, data transfer is performed at address 003.
This shows that you only need to do this. For this reason, TR
ADRG6 that read the contents of 8M7 is at address 00.
3 and the one designated as output mode by address 003 is a CM, the data of the CM is transferred to other CMs and UDs designated as reception mode.

The UD then forwards its 6 data to the PI 105.

If the contents of pins 1 to 15 of TR8M at address 000 are all O, then ADRG that has read the contents determines that there is no need to transfer data at addresses 001 to 00F, and sends address 010 of the next TR8M. Next, the contents of address 010 are read and the address to be output is determined. In the example in Figure 4, bits 1 to 15 are all 0, so A
DRG6tiI10 addresses 011 to OIF are deemed not to be transferred, and the next address 020 of TR8M7 is taken.

In this way, data can be transferred only to the address specified by TR8M, and the time for one scan from address 000 to the upper limit of the address can be shortened.

Next, TR, 8M7, 0M2. UD4. ADRG6 will be explained in detail.

FIG. 4 shows a configuration diagram of TR8M7. For example, TR8M has an address of 000,010.020. This is a memory whose addresses are allocated in hexadecimal numbers in increments of 10. The contents of this 188M7 indicate whether the CM or UD including this TRAM is requesting data transfer, and whether this TR8M is ADRG.
This means whether the number is 9 or not. To explain using the example in Figure 4, if 0 bit is 11'', TR8M is A
Indicates that it has not been read by DRG6, 0 bit 'mO' indicates that the address in TR8M is not read by DRG6.
Indicates that it was read by. Therefore, if the O bit contains @1, it indicates that a continuous request is in progress.
Also, 1 to 15 sets indicate whether or not addresses XX1 to XXF (X indicates 00 to FF) request data transfer, 10m indicates that data transfer is not required, and -"l" indicates that data transfer is required. . In the example of FIG. 4, the third bit l# at address 000 indicates that the data at address 003 requests data transfer.

Next, see Figures 5 and 6! The functions of the 70M2 will be explained below. FIG. 5 is a block diagram of 0M2. 8 is a dual port memory (hereinafter abbreviated as DPM) having a central function of CM. DPM8 is P! All information on 10 and C
This memory stores PU cage information and is accessible from both the CPU side and the processing device 10 in 0M.

20 is a selection circuit which has the function of storing the address issued from the CPU and at the same time determining whether the CM is selected by the CPU and is 9; 21 is an address buffer;
At the same time as memorizing the address issued by ADRG6, use scissors C.
The processing device 10 has a function of reporting to the processing device 10 whether M is selected and whether it is a circle or not.
:/Comprised of dumb access memory 25. 7 is Moe's TRAM.

26 is a memory that records the input/output addresses used by the CM and flag information indicating the CPU, and is used to determine whether to send or receive data when the 7 address is received from ADRG 6. , which is set in advance. Next, the operation of the CM is explained using the CMI shown in Figure 6.
Ih creation flowchart) K will explain. At the start of operation, all the contents of 188M are set to 11". By doing this, all data output from fi CPU will be transferred to other CMs and PIlo. Next, process The device IO stores the data transferred from PIlo or other CM to the CPU in the DPM. Next, the output data of the DPM, that is, from the CPU, the P
When a change occurs in the data to be transferred to Ilo or another CM, the transfer request data is stored in the dedicated TR8M in the TR8M data format shown in FIG. Note that the above-mentioned change in data can be confirmed by comparing the data stored in the RAM 25 in advance with the contents of the DPM 8. The processing device 10 repeats this verification operation. Next, ADHD6
If there is a data transfer request from PIlo to PIlo, the contents of the specified address of DPM are output.

As described above, the CM can transfer only truly necessary data that has changed.

Next, according to FIGS. 7 and 8, the unit controller (UD)
) operation is explained.

FIG. 7 is a configuration diagram of the UD4. 8o is the input/output memory (hereinafter abbreviated as IOM) which is the center of the UD, and PI10! $
11 memory u, CPU 1111 and QD processing in UD 11
Access town # from both sides of the device 10! This is memo 17.

40 is a selection circuit which has the function of storing the address issued from ADHGa and at the same time determining whether #UD is selected from ADRG. Reference numeral 41 denotes an address buffer, which is a circuit that strengthens the address signal output from the escape fitlO.

43 is a microprocessor constituting the processing device; 44 is a nine-read only memory containing a control program;
45 is a random access memory.

7 is the aforementioned TRAM. Next, the operation of UD is shown in Figure U
This will be explained using the D operation flowchart. 9, T at the start of operation
Set all contents of R8M to @1”K.

By doing this, a request to transfer all data from pilot to CM has been issued.

Next K, J611 device 110 u I OM 80 oP
Go to I 10.

All output information is output to the PI 105. Also PIlo
Compare the data from s to 0M2 and l0M80 data, and if there is a discrepancy, PI1050 person data V
Assuming that C changes are rare, the input data of PIlo is
At the same time, the transfer request data is stored in TR8M7. If the contents of TR8M7 are read to ADHG6, the TR8M data is reset.

As described above, the UD 4 can request the transfer of only necessary data to the PI 105's human information without any changes.

Next, the operation of the ADRG 6 will be explained with reference to FIGS. 9 to 12. FIG. 9 shows a configuration diagram of ADHG6.

The purpose of ADRG is to read the contents of TR8M7 and send an address based on this contents.

Reference numeral 60 denotes a clock generation circuit, and the AD circuit G6 operates according to the timing of this clock. 61 is an AND circuit, which is a gate for a clock signal to the counter 62;

Reference numeral 62 is an up-column for address output which is the center of ADHG, and the count and output increase each time the clock input is input.

63 is a bit memory), and as shown in the bit memory diagram in FIG. 11, each address has one bit of content. 6
4 is a CAR circuit which ORs the output between the shift registers and the output of the pit memory 63.

Reference numeral 65 denotes a 7 rig and 70 lig that stores the output of the OR circuit. 66 is a shift register that stores the contents of TR8M7 read out at the address issued by ADHG6, converts the contents into serial data, and outputs the converted contents. 67 stores the nine addresses output from the counter 62 and sends this result to ADHG.
This is a latch register that outputs the output address of 6. 68 is the core).

- A control signal is output to each circuit using a loop circuit. To explain the operation, as shown in FIG. 7 lips 70 tubes 65
is initially reset, so the output 0 is logic @l”
It has become.

Therefore, the tarok is sent to the counter 6 via the AND circuit 61.
2. When the signal CLK is 0, the counter 6
The output of 2 is also 0, that is, the signal IADDR is 0. This signal IADDR is applied to the bit memory 63 and the output O
M is logic 11” as shown in the JiF11 diagram, so
This is stored in the 7 lip 70 knob 65, and this output GA
TE becomes logical 10m.

Therefore, the signal ICLK also becomes logic ``0'', the counter 62 stops counting, the IADDRO value holds 0, this value is latched in the latch register 67, and the address ADDR is output as 0. Ziad at this address,
TR8M7 of response 0 is read out as a DATA signal (
(The shaded part means valid data) is stored in the shift register 66.

After the time T required for reading and υ of this data DATA has elapsed, the flip-flop 65 is reset, and the AND circuit 61 passes the signal CLK again. This allows the signal ICLK to
is applied to the counter 62, and the output IADL) is 1,2
．． Proceed to 3. In synchronization with this signal IADDR, the shift register also advances three steps as shown in FIG. 12(b).
Outputs output logic 11#. This signal is transmitted to the OR circuit 64
is stored in the flip 70 knob 65, and the gate of the AND circuit 61 is closed. In this way,
The signal IADDR is fixed at 3, and this output is sent to the latch 67.
is applied to the address generation circuit 3 as the output of ADRG.
Output. Slip frog 66 after a certain period of time T has elapsed
is reset and the counter 62 starts counting up. In this way, Al) RG6 becomes TR8M7
It is possible to send an address according to the nine requests written in the .

As described above, according to one embodiment, CM and UDKTR
By attaching 8M, it is possible to select and transfer only the necessary data in the bus coupling device, and as a result, data transfer between the CPU and other CPUs and C
It is possible to speed up data transfer between PU and PI10.
This will be achieved by expanding the application of this device.

As is clear from the detailed explanation above, the present invention allows high-speed data transfer to be achieved in a bus-coupled system.

[Brief explanation of drawings]

1 and 2 are explanatory diagrams of the conventional system, with FIG. 1 being an overall configuration diagram and FIG. 2 being a data transfer memory configuration diagram. 3 to 12 are explanatory diagrams of the system of the present invention, where FIG. 3 is an overall configuration diagram, FIG. 4 is a data transfer request memory configuration diagram, 11g5 is a common data memory configuration diagram, and #! 6 is a common data memory operation flow diagram, FIG. 7 is a unit driver configuration diagram, FIG. 8 is a unit driver operation flow diagram, FIG. 9 is an overall address generation circuit configuration diagram, and FIG. 1O is an address generation circuit time chart. Figure 11 is a bit memory configuration diagram, Figure 12 is a bit memory configuration diagram.
The figure shows an explanatory diagram of the operation of the shift register. 1... Processing device, 2... Common data number, 3...
・Buffer, 4...Unit driver, 5...I/O device, 6...Address generation circuit, 7...Data transfer request memory, 8...Dual port memory, 11
...Data, roof 1 figure number O number 1 book (1 711O Jinsu No. 21 8 tusk 3I2) breathlessness 0 4τH*grL 710t!λ koto 4 m bore S figure ■ 6 figure bud 1 mouth

Claims (1)

[Claims] 1. A plurality of processing devices, a process input/output device, a bus for transmitting data between them, and a bus installed between the bus and each scissor processing device, each of which a plurality of common data memories that store common data; a driver that is installed between the bus and the process input/output device and stores the same content as the common data memories; and an address generator that generates an address for controlling data transfer between the drivers, the data transfer control method of the bus coupling system is implemented, and the common data is stored in the common data memory and the driver. The data transfer length is used to specify the address for which a transfer request has been made. the data transfer request memory, the address generator reads the contents of the data transfer request memory, generates an address signal corresponding to the contents of the data transfer request memory, and performs the data transfer according to the scissor address signal. Transfer control method.