JPH0991244A - Data transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively use a memory and to reduce the area occupied by the memory within a chip. SOLUTION: The data are transferred to a receiving buffer 5 from a sending buffer 4 via a data input/output means 6. Then the buffer 4 becomes empty and the buffer 5 is filled with data. Under such conditions, a DMA(direct memory access) request is sent to a DMA controller 8 from the means 6. At the same time, a full double transfer start signal is sent to a DMA transfer RAM control part 7 by the operation of a full double mode that is previously set. The data on the address shown by an address generation part 3 is fetched by the buffer 4 via a data bus 1 and stored in a data RAM 2, so that the sending transfer surely occurs earlier than the receiving transfer. Then the buffer 5 reads the value out of the bus 1 in the address shown by the part 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a full-duplex DMA (Dire
ct Memory Access) The present invention relates to a data transfer device that inputs and outputs data to and from an external device using transfer.

[0002]

2. Description of the Related Art In recent years, more advanced techniques have been introduced for digital signal processing, and a data transfer device, which is one of the devices used therein, has more transfer words and a larger occupied area. There is a demand for smaller devices and those with lower power consumption.

A conventional data transfer apparatus will be described below with reference to the drawings. FIG. 5 shows an example of a conventional data transfer device. In FIG. 5, 101 is AL
A data bus for transferring data to an arithmetic unit such as U; 102, a data RAM for reading and writing data from the data bus 101; and a data RAM for holding data; and 103, an address generation unit for generating an address to be accessed by the data RAM 102, Reference numeral 104 denotes a transmission buffer that holds data output from the data RAM 102 and transmitted to an external device, 1
Reference numeral 05 is a reception buffer that holds data received from an external device, 106 is a data input / output unit that transmits the data in the transmission buffer 104 to the external device, and stores the received data in the reception buffer 105, and 107 is the data RAM 10
2, D for controlling the address generation unit 103, the transmission buffer 104, the reception buffer 105, and the data input / output unit 106
The MA controller 108 sends a control signal D which indicates whether the DMA function is used for full duplex transfer or half duplex transfer.
DMA control register provided to the MA controller 107,
An external device 109 exchanges data with the data input / output unit 106.

With respect to the data transfer device configured as described above, one transfer operation of the full-duplex DMA operation will be described below. In the conventional data transfer apparatus, in the memory area used for the DMA in the data RAM 102, the area in which the transmission data is held by the full-duplex DMA and the area of the received data are treated separately as shown in FIG. Be seen.

When data is transmitted / received by full-duplex DMA,
Before starting transmission / reception, via the data bus 101, D
A signal of the full-duplex DMA mode is transmitted to the MA control register 108, and the DMA control register 108 receives the full-duplex DMA mode.
The DMA of the DMA controller 107 depends on the mode signal.
Set in full mode.

FIG. 7 shows an example of memory access timing in conventional full-duplex DMA transfer. It is assumed that the external device / data input / output means transfer serial clock in FIG. 7 has a cycle three times or more as long as the instruction clock for driving the data transfer device.

The full-duplex D is shown in FIG. 7 as a time chart below.
The MA operation will be described. Immediately before the timing a in FIG. 7, one word of data is transferred between the external device 109 and the data input / output unit 106, and then the transmission buffer 1
The data is transferred from 04 to the data input / output means 106, the transmission buffer 104 becomes empty, and the data input / output 106
The data is passed from the receiving buffer 105 to the receiving buffer 105, and the receiving buffer 105 becomes full. Then, timing a in FIG.
At this time, a DMA request is issued from the data input / output means 106
It is sent to the MA controller 107.

The DMA controller 107 operates in the full-duplex mode set in advance in response to a request from the DMA, so that at the timing b in FIG.
The operation of the transmission DMA of the heavy DMA is performed.

In the operation of the transmission DMA, the DMA controller 107 causes the address generator 103 to generate the address of the memory in which the transmission data exists, and the data RAM 10
2 causes the data at the address indicated by the address generation unit 103 to be output to the data bus 101, and then the transmission buffer 104 is instructed to fetch the value of the data bus 101, and the processing is completed.

After the transmission DMA, at the timing c in FIG. 7, the operation of the transmission DMA of the full-duplex DMA is performed. The operation of the transmission DMA is performed by the DMA controller 10
7 instructs the reception buffer 105 to output the held data to the data bus 101, and then instructs the address generation unit 103 to change the address, for example, 1024 words, which is different from the address where the transmission data exists. An address of a memory in which reception data having an offset is present is generated, and an instruction is issued to the data RAM 102 to read a value from the data bus 101 at an address indicated by the address generation unit 103, thereby performing reception DMA and full-duplex DMA. One transfer ends.

As described above, even in the conventional data transfer device,
It is possible to input / output data to / from an external device using full-duplex DMA transfer.

[0012]

However, in the above-mentioned conventional data transfer apparatus, the buffer for transferring in the full-duplex mode and the buffer for receiving must be located in separate places in the memory, and the buffer must be transmitted. Data is continuously held in the memory, and the number of words in the memory occupied by the data transferred in the full-duplex mode is simply the sum of the transmission buffer and the reception buffer, that is, the number of words transferred in the full-duplex mode is 2
It is twice.

Further, the memory used is connected to an arithmetic unit such as an ALU via a data bus, is accessed by a high-speed access clock, and does not change the access speed even when the DMA low-speed access is sufficient. That is, the memory used only for input / output has a problem that the area occupied in the integrated circuit chip is larger than necessary, the power consumption is large, and the performance is high.

The present invention solves such a conventional problem. It is not necessary to retain transmitted data, and high-speed memory access is not required for memory access during DMA. It is an object of the present invention to provide an excellent data transfer device that can reduce the power consumption of the memory used for input / output and the occupied area in the chip.

[0015]

In order to achieve the above object, the first configuration of the present invention has a data bus for transferring data to an arithmetic unit such as an ALU, and a read / write operation for the data bus. Data RA that holds data to be executed
M, an address generator that generates an address to be accessed by the data RAM, a transmission buffer that holds data output from the data RAM and transmitted to an external device,
A reception buffer that holds data received from an external device, a data input / output unit that transmits data in the transmission buffer to the external device and stores received data in the reception buffer, and a data RAM to a data bus during DMA transfer. A DMA transfer RAM control unit that controls the timing of reading data and the timing of writing data from the data bus, and a DMA controller that controls the data RAM, address generation unit, transmission buffer, reception buffer, data input / output unit, and DMA transfer control unit. And a DMA control register for giving a control signal to the DMA controller as to whether the DMA function is used for full-duplex transfer or half-duplex transfer.

In addition to the above first configuration, the second configuration of the present invention transfers data to the transmission buffer by DMA and writes the data from the reception buffer by DMA so that the memory access clock can be slowed down. I / O dedicated memory and memory access clock of I / O dedicated memory
An access clock control device that controls the reception buffer and the DMA clock of the I / O dedicated memory to be slow, and an access clock control that gives the access clock control device a signal indicating whether the access clock is fast or slow And a register.

A third configuration of the present invention is, in addition to the first configuration, the access clocks of the transmission buffer and the reception buffer are low speed, the data is transferred to the transmission buffer by DMA, and the data is written from the reception buffer by DMA. The access clock control device controls the memory access clock to a low speed I / O dedicated memory, the access clock control device to control the data DMA memory access clock to a low speed in accordance with the I / O dedicated memory, and the access clock control device to control the access clock to a high speed. And an access clock control register which gives a signal indicating whether the speed is low or low.

[0018]

According to the present invention, the buffer configured to transfer in full-duplex mode and the buffer configured to receive in the full-duplex mode can exist in the same place, and the transmitted data is not kept in the memory. The number of words in the memory occupied by the data to be transferred in the dual mode is simply equal to the size of the transmission buffer or the reception buffer, that is, the number of words to be transferred in the full duplex, and the memory occupation area in the integrated circuit chip is reduced. It can be made smaller.

Further, by newly providing a memory used only for input / output, it is possible to access even with a low-speed access clock, it is possible to support a low-speed access of DMA, and it is possible to reduce power consumption.

Further, the memory used only for input / output is made to be accessed only by the low-speed access clock, so that it is possible to configure the memory at low speed, and the memory used for input / output can be configured with small cells. The area occupied by the memory in the chip can be further reduced.

[0021]

【Example】

(Embodiment 1) Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1 is a block diagram showing a memory transfer device according to a first embodiment of the present invention. In FIG. 1, 1 is a data bus for transferring data to an arithmetic unit such as an ALU, 2 is a data RAM for reading and writing data from the data bus 1, and 3 is a data RAM for holding data. An address generator 4 for generating is a transmission buffer for holding the data output from the data RAM 2 and transmitted to an external device, 5 is a reception buffer for holding the data received from the external device, and 6 is an external data for the transmission buffer 4. Data input / output means for transmitting data to the device or storing received data in the reception buffer 5, 7
Is a DMA transfer RAM controller that controls the timing of reading data from the data RAM 2 to the data bus during DMA transfer and the timing of writing data from the data bus.
Reference numeral 8 is a DMA controller for controlling the data RAM 2, address generation unit 3, transmission buffer 4, reception buffer 5, data input / output means 6, and DMA transfer RAM control unit 7, and 9 is a D controller.
DM for giving a control signal to the DMA controller 8 as to whether the MA function is used in full-duplex transfer or half-duplex transfer
The A control register 10 is an external device that exchanges data with the data input / output unit 6.

With respect to the data transfer device configured as described above, one transfer operation of the full-duplex DMA operation will be described below. First, regarding the memory area, in the present embodiment, the area in the data RAM 2 in which the transmission data is held by the full-duplex DMA and the area of the received data are the same memory as shown in FIG. Become. Full duplex DMA
When data is transmitted / received by, the full-duplex DMA mode signal is transmitted to the DMA control register 9 via the data bus 1 before starting the transmission / reception, and the DMA control register 9 is in the full-duplex DMA mode. Signal to set the DMA mode of the DMA controller 8 to full duplex.

An example of the memory access timing in full-duplex DMA transfer of this embodiment is as shown in FIG. 7 as in the conventional example. It is assumed that the external device / data input / output means transfer serial clock in FIG. 7 has a cycle three times or more as long as the instruction clock for driving the data transfer device. Hereinafter, FIG. 7 will be described as a time chart.

Immediately before the timing a in FIG. 7, the external device 1
After one word of data has been transferred between 0 and the data input / output means 6, the data is transferred from the transmission buffer 4 to the data input / output means 6 and the transmission buffer 4 becomes empty.
The data is transferred from the data input / output means 6 to the reception buffer 5, and the reception buffer 5 becomes full. Then, at the timing a in FIG. 7, the DMA request is issued by the data input / output unit 6.
To the DMA controller 8.

The DMA controller 8 sends a full-duplex transfer start signal to the DMA transfer RAM control unit 7 by a preset full-duplex mode operation in response to a DMA request, and sends it to the address generation unit 3. The address of the memory where the data of exists exists, that is, the address for storing the received data is generated.

Next, the DMA transfer RAM control unit 7 sets the address indicated by the address generation unit 3 in the data RAM 2 at the time of timing b in FIG. 7 so that the transfer of the transmission surely precedes the transfer of the reception. The data is output to the data bus 1, then the transmission buffer 4 is instructed to take in the value of the data bus 1, and the transmission DMA is completed.

When the transmission DMA is completed, the DMA transfer RA
At the timing c in FIG. 7, the M control unit 7 instructs the reception buffer 5 to output the data held therein to the data bus 1, and the address indicated by the address generation unit 3, that is, the data is transmitted. The data RAM 2 is instructed to read the value from the data bus 1 at the address where the data is present, and one transfer of the reception DMA and the full-duplex DMA is completed.

As described above, according to the present embodiment, the reception data is overwritten in the address where the transmission data is stored as soon as the transfer is completed, so that it is generally unnecessary to retain it if it is transferred. The memory in which the transmission data is stored can be effectively used, and the area occupied by the memory in the integrated circuit chip can be reduced.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing a memory transfer device according to the second embodiment of the present invention. In the present embodiment, the same parts as those in the first embodiment are designated by the same reference numerals, duplicate explanations will be omitted, and only different configurations will be explained. The feature of this embodiment is that, as shown in FIG. 3, in addition to the data RAM 2, data is transferred to the transmission buffer 4 by DMA via the data bus 1 and data is transmitted from the reception buffer 5 via the data bus 1. Is written by DMA, and the memory access clock can be slowed down by the I / O dedicated memory 11,
Memory access clock of I / O dedicated memory 11 and transmission buffer 4, reception buffer 5 and I / O dedicated memory 1
Access clock control device 12 for controlling the DMA clock between 1 and 1 to be slow, and an access clock control register 1 for giving the access clock control device 12 a signal as to whether the access clock is fast or slow.
3 is provided, and the DMA between the I / O dedicated memory 11 and the transmission / reception buffers 4 and 5 is configured to be performed by a low-speed clock.

With respect to the data transfer apparatus configured as described above, one transfer operation of the full-duplex DMA operation will be described below. First, regarding the memory area, the memory used for full-duplex transmission / reception in the present embodiment exists in the I / O dedicated memory 11, and the area holding transmission data and the area of received data are The same memory is used as shown in FIG.

When data is transferred by full-duplex DMA,
Before starting transmission / reception, the data stored in the data RAM 2 such as the calculation result must be transferred to the I / O dedicated memory 11. In that case, the I / O dedicated memory 1 is transferred to the access clock control register 13 via the data bus 1.
The access clock control device 12 controls the access clock control device 12 to access the data bus 1 of the I / O dedicated memory 11 at high speed by applying a high-speed access control signal from the access clock control register 13. To do. By this control, the access clock of the I / O dedicated memory 11 and the access clock of the data RAM 2 become uniform speed, and the preparation for transfer is completed.

After that, the data RA is transmitted via the data bus 1.
The data stored in M2 is transferred to the I / O dedicated memory 11, and all the data to be transmitted is transferred to the I / O dedicated memory 1
When 1 is received, the I / O dedicated memory 11 is accessed only by DMA, and is not accessed at high speed. Therefore, the access clock control register 13 is connected to the I / O dedicated memory 1 via the data bus 1.
The access clock control device 12 gives a signal for making the access clock of 1 low speed, and the access clock control device 12 receives the low speed access control signal of the access clock control register 13
The access to the data bus 1 of the I / O dedicated memory 11 is controlled to be performed at a low speed. After transferring all the data to be transferred, the area of the data RAM 2 where the transfer data is stored can be used freely.

After this point of time, the access clock control device 12 controls the transmission buffer 4 and the reception buffer 5 to access the data bus at a low speed.

At this time, since one word of the transmission / reception DMA is generally performed in units of 8 bits or more, the access clock of the I / O dedicated memory 11, the transmission buffer 4, and the reception buffer 5 is set to be slower than the conventional access clock. Even if you do, there will be no problem.

Further, before starting transmission / reception, a full duplex DMA mode signal is transmitted to the DMA control register 9 via the data bus 1, and the DMA control register 9 is set to full 2
D of the DMA controller 8 by the heavy DMA mode signal
Set the MA mode to full duplex.

An example of the memory access timing in the full-duplex DMA transfer of this embodiment is as shown in FIG. 7 as in the conventional example. It is assumed that the external device / data input / output means transfer serial clock in FIG. 7 has a cycle three times or more as long as the instruction clock for driving the data transfer device. Hereinafter, FIG. 7 will be described as a time chart.

Immediately before the timing a in FIG. 7, the external device 1
After one word of data has been transferred between 0 and the data input / output means 6, the data is transferred from the transmission buffer 4 to the data input / output means 6 and the transmission buffer 4 becomes empty.
The data is transferred from the data input / output means 6 to the reception buffer 5, and the reception buffer 5 becomes full. Then, at the timing a in FIG. 7, the DMA request is issued by the data input / output unit 6.
To the DMA controller 8.

The DMA controller 8 sends a full-duplex transfer start signal to the DMA transfer RAM control section 7 by a preset full-duplex mode operation in response to a DMA request, and sends it to the address generation section 3. The address of the memory in which the data exists is generated, that is, the address of the I / O dedicated memory 11 that generates the address for storing the received data is generated.

Next, the DMA transfer RAM control unit 7 ensures that the transfer of the transmission occurs before the transfer of the reception, at the timing b of FIG.
1 outputs the data at the address indicated by the address generator 3 to the data bus 1, then issues an instruction to the transmission buffer 4 to take in the value of the data bus 1, and the transmission DMA is completed.

When the transmission DMA is completed, the DMA transfer RA
At the timing c in FIG. 7, the M control unit 7 instructs the reception buffer 5 to output the data held therein to the data bus 1, and the address indicated by the address generation unit 3, that is, the data is transmitted. I / at the address with the data
An instruction is issued to the O-dedicated memory 11 to read a value from the data bus 1, and the reception DMA and full-duplex DMA are executed.
One transfer of is completed. The difference from the first embodiment is that the access clock for the data bus 1 of the I / O dedicated memory 11, the transmission buffer 4, and the reception buffer 5 is low speed.

As described above, according to the present embodiment, the reception data is overwritten in the address in which the transmission data is stored as soon as the transfer is completed, so that it is generally unnecessary to retain it if it is transferred. The memory in which the transmission data is stored can be effectively used, and the area occupied by the memory in the integrated circuit chip can be reduced. Furthermore D
It is possible to reduce the memory access clock at the time of transfer of MA, and it is possible to reduce power consumption.

(Embodiment 3) Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram showing a memory transfer device according to the third embodiment of the present invention. In the present embodiment, the same parts as those in the second embodiment will be designated by the same reference numerals, redundant description will be omitted, and only different configurations will be described. The feature of the present invention is that, as shown in FIG. 4, in addition to the data RAM 2, data is transferred to the transmission buffer 15 via the data bus 1 by DMA, and the data is transferred from the reception buffer 16 via the data bus 1 to the data buffer 2. I / O dedicated memory 14 written by DMA and having a low memory access clock, and transmission buffer 15 and reception buffer 1 having a low access clock
6, an access clock control device 17 for slowing the memory access clock for the data bus 1 of the data RAM 2, and an access clock control register for giving the access clock control device 17 a signal indicating whether the access clock is fast or slow. 18 is provided, and DMA between the I / O dedicated memory 14 and the transmission / reception buffers 15 and 16 is configured to be performed with a low-speed clock.

With respect to the data transfer device configured as described above, one transfer operation of the full-duplex DMA operation will be described below. First, regarding the memory area, the memory used for full-duplex transmission / reception in the present embodiment exists in the I / O dedicated memory 14, and the area holding transmission data and the area of received data are The same memory is used as shown in FIG.

When data is exchanged by full-duplex DMA,
Before starting transmission / reception, the data stored in the data RAM 2 such as the calculation result must be transferred to the I / O dedicated memory 14. In that case, the access clock control register 18 is supplied with a signal for slowing the access clock of the data RAM 2 via the data bus 1, and the high-speed access control signal of the access clock control register 18 causes the access clock control device 17 to cause the data RAM 2 to operate.
The data bus 1 is controlled to be accessed at low speed. By this control, the access clock of the I / O dedicated memory 14 and the access clock of the data RAM 2 have the same speed, and the preparation for the transfer is completed.

After that, the data RA is transmitted via the data bus 1.
The data stored in M2 is transferred to the I / O dedicated memory 14, and all the data to be transmitted is transferred to the I / O dedicated memory 1
4 receives, the access to the data RAM 2 is
It is only accessed at high speed and never accessed at low speed. Therefore, the access clock control register 18 is supplied with a signal for increasing the access clock of the data RAM 2 via the data bus 1, and the high-speed access control signal of the access clock control register 18 causes the access clock control device 17 to start the data The RAM 2 is controlled to access the data bus 1 at high speed. After transferring all the data to be transferred, the area of the data RAM 2 where the transfer data is stored can be used freely.

At this time, since one word of the send / receive DMA is generally performed in units of 8 bits or more, the access clock of the I / O dedicated memory 14, the send buffer 15, and the receive buffer 16 is always slower than the conventional access clock. Even so, no problem occurs.

Further, before starting transmission / reception, a full duplex DMA mode signal is transmitted to the DMA control register 9 via the data bus 1, and the DMA control register 9 is set to full 2
D of the DMA controller 8 by the heavy DMA mode signal
Set the MA mode to full duplex.

An example of the memory access timing in the full-duplex DMA transfer of this embodiment is shown in FIG. 7 as in the conventional example. It is assumed that the external device / data input / output means transfer serial clock in FIG. 7 has a cycle three times or more as long as the instruction clock for driving the data transfer device. Hereinafter, FIG. 7 will be described as a time chart.

Immediately before the timing a in FIG. 7, the external device 1
After one word of data has been transferred between 0 and the data input / output means 6, the data is transferred from the transmission buffer 15 to the data input / output means 6, the transmission buffer 15 becomes empty, and the data input / output means 6 The data is passed from the receiving buffer 16 to the receiving buffer 16, and the receiving buffer 16 becomes full. Then, the DMA request is sent from the data input / output unit 6 to the DMA controller 8 at the timing a in FIG.

The DMA controller 8 sends a full-duplex transfer start signal to the DMA transfer RAM control section 7 by a preset full-duplex mode operation in response to a DMA request, and sends it to the address generation section 3. The address of the memory in which the data exists is generated, that is, the address of the I / O dedicated memory 11 that generates the address for storing the received data is generated.

Next, the DMA transfer RAM control section 7 makes sure that the transfer of the transmission takes place before the transfer of the reception without fail at the timing b in FIG.
4 causes the data at the address indicated by the address generator 3 to be output to the data bus 1, then issues an instruction to the transmission buffer 15 to take in the value of the data bus 1, and the transmission DMA is completed.

When transmission DMA is completed, DMA transfer RA
At the timing c in FIG. 7, the M control unit 7 instructs the reception buffer 16 to output the data held therein to the data bus 1, and the address indicated by the address generation unit 3, that is, the data is transmitted. I at the address with the data
/ O dedicated memory 14 is instructed to read a value from the data bus 1 to receive DMA and full-duplex DM
One transfer of A is completed. Here, the difference from the second embodiment is that the access clock for the data bus 1 of the I / O dedicated memory 14, the transmission buffer 15, and the reception buffer 16 is low speed.

As described above, according to the present embodiment, the reception data is overwritten in the address where the transmission data is stored as soon as the transfer is completed, so that it is not generally necessary to retain it if it is transferred. The memory in which the transmission data is stored can be effectively used, and the area occupied by the memory in the integrated circuit chip can be reduced. Also, D
It is possible to reduce the memory access clock at the time of transfer of MA, and it is possible to reduce power consumption. Further, the I / O dedicated memory is always required to operate at a low speed, a cell having a small area can be used, and the occupied area of the memory can be further reduced.

[0054]

As described above, according to the present invention,
Since a DMA transfer RAM control unit that controls the timing of reading data from the data RAM to the data bus and the timing of writing data from the data bus during DMA transfer is provided, the received data is transferred to the address where the transmission data is stored. By overwriting as soon as possible, it is possible to effectively use the memory that stores transmission data that does not need to be retained if it is transferred, and reduce the area occupied by the memory in the integrated circuit chip. can do.

In addition to the DMA transfer RAM controller, the present invention also transfers data to the transmission buffer by DMA via the data bus, writes data from the reception buffer via DMA via the data bus, and writes the memory access clock. Access clock control for controlling the I / O dedicated memory that can be slowed down, the memory access clock of the I / O dedicated memory, and the DMA clock between the send / receive buffer and the I / O dedicated memory to be slowed down In addition to the above effects, the DMA device and the access clock control register for providing the access clock control device with a signal for speeding up or slowing down the access clock are provided.
It is possible to reduce the memory access clock at the time of transfer, and it is possible to reduce power consumption.

In addition to the DMA transfer RAM control section, the present invention also provides a low-speed access clock transmission buffer and reception buffer, and a D-buffer to the transmission buffer via a data bus.
The data is passed by MA, the data is written from the reception buffer via the data bus by DMA, and the access clock control device that makes the memory access clock to the data bus of the data RAM and the I / O dedicated memory having a low access clock low speed And an access clock control register for giving a signal to the access clock control device for increasing or decreasing the access clock, the I / O dedicated memory can always operate at low speed in addition to the above effect. Since a cell having a small area can be used, the area occupied by the memory can be further reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a data transfer device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a memory area used for full-duplex DMA in this embodiment.

FIG. 3 is a block diagram showing a data transfer device according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a data transfer device according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional data transfer device.

FIG. 6 is a configuration diagram of a memory area used in a conventional full-duplex DMA.

FIG. 7 is a configuration diagram of a memory area used for conventional full-duplex DMA.

[Explanation of symbols]

1 Data Bus 2 Data RAM 3 Address Generator 4 Transmit Buffer 5 Receive Buffer 7 DMA Transfer RAM Controller 8 DMA Controller 9 DMA Control Register 10 External Equipment 11 Low Speed I / O Dedicated Memory 12 I / O Dedicated Memory Access Clock control device 13 Access clock control register for I / O dedicated memory 14 Low speed I / O dedicated memory 15 Low speed transmission buffer 16 Low speed reception buffer 17 Access clock control device for data RAM 18 Access clock control register for data RAM

Claims (3)

[Claims] 1. A data bus for transferring data to and from an arithmetic unit such as an ALU, a data RAM for reading and writing data corresponding to the data bus and holding data, and an address for generating an address to be accessed by the data RAM. A generator, a transmission buffer that holds the data output from this data RAM and transmitted to an external device, a reception buffer that holds the data received from the external device, and the data in the transmission buffer can be transmitted to the external device, Data input / output means for storing the received data in the reception buffer, a DMA transfer RAM control unit for controlling the timing of reading data from the data RAM to the data bus during DMA transfer, and the timing of writing data from the data bus, and the data RA.
M, an address generator, a transmission buffer, a reception buffer, a data input / output unit, and a D for controlling a DMA transfer RAM control unit
A data transfer device comprising a MA controller and a DMA control register for giving a control signal to the DMA controller as to whether the DMA function is used in full-duplex transfer or half-duplex transfer. 2. Passing data to the transmission buffer by DMA,
Data is written by DMA from the receive buffer and the memory access clock can be slowed down, and the memory access clock of the I / O dedicated memory and the DMA clock of the send / receive buffer and the I / O dedicated memory 2. The data according to claim 1, further comprising: an access clock control device for controlling so as to reduce the speed and an access clock control register for giving the access clock control device a signal indicating whether the access clock is increased in speed or reduced in speed. Transfer device. 3. An access clock of a transmission buffer and a reception buffer is low speed, data is transferred to the transmission buffer by DMA, data is written from the reception buffer by DMA, and a memory access clock is a low speed I / O dedicated memory. I / O for memory access clock of data DMA
2. The data according to claim 1, further comprising: an access clock control device for controlling the access clock at a low speed in accordance with a dedicated memory; and an access clock control register for giving a signal to the access clock control device to increase or decrease the access clock. Transfer device.