JPH01259441A - Bus interface device - Google Patents

Abstract

PURPOSE:To improve the throughput of a module by arranging a DMA (direct memory access) interface controller having a transfer control circuit at the contact between a main bus and a local bus. CONSTITUTION:A DMA main interface controller 3 is provided with a main-side address counter 3a which determines the address of a main memory 1 and a main-side sequencer 3b which controls the control line of the main bus. Further, a local-side address counter 3c which determines the address of a local memory 4 and a local-side sequencer 3d which controls the control line of the local bus are provided. Therefore, the main-side sequencer 3b and the local-side sequencer 3d can latch data on a data bus controller or output it to the controller 3e whether sequencers of each other get respective bus use rights or not. Consequently, the bus on the side where a task is terminated is immediately opened. Thus, the bus is used for another task, and the throughput of the whole of the system is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus interface device, and particularly to a DMA (Direct) between a main memory and a local memory.
The present invention relates to a bus interface device having a configuration in which a controller for performing memory access (Memory Access) transfer is placed at a contact point between a main bus and a local bus.

[Conventional technology]

In the conventionally known bus interface device having a DMA function, as shown in FIG. 7, the DMA controller 7 is separated from the bus controller 8, and the DMA controller 7 is not located at the contact point between the main bus and the local bus. , when performing DMA transfer between memories 1 and 4 on each bus, the local memory 4 is accessed and the DM
The local bus is used when latching data into the A controller 7, and the local bus is also used when sending data from the DMA controller 7 to the bus controller 8. Therefore, the local bus is used twice every time a unit of information is transferred.

[Problem to be solved by the invention]

In the above conventional technology, when performing DMA transfer using a method in which a DMA controller is connected to a local bus and the bus controller interfaces between the main bus and the local bus, the DMA controller latches data and transfers the data. Since the local bus is monopolized twice when outputting the local bus, it becomes an obstacle when other devices use the local bus, and this hinders the improvement of the processing capacity of the module having the local bus.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus interface device that can reduce the exclusive time of a local bus during DMA transfer execution and improve the processing ability of a module.

[Means to solve the problem]

The above purpose is to control the main C, which controls the entire system.
A main bus that transmits information between PUs and individual functional modules, and a local bus that is independent of the main bus that transmits information within modules incorporating local CPUs that exclusively process individual functions within each functional module. bus, and between the memories installed on each bus.
In a system that transmits information by MA transfer, a main memory access circuit outputs an address to be accessed to the main bus side and transfers data to a main memory connected to the main bus having the target address. , a local memory access circuit that outputs an address to be accessed to the local bus side and performs data transfer with a local memory connected to the local bus having the target address is provided, and the main memory access circuit and A DMA interface controller having a transfer control circuit for mutually exchanging data with the local memory access circuit is arranged at a contact point between the main bus and the local bus.

[Effect]

The DMA main face controller includes a main side address counter that determines the address of the main memory, a main side sequencer that controls the main bus control line, a local side address counter that determines the local memory address, and a local bus control line. Because the main sequencer and the local sequencer have a local sequencer that controls the
Data can be latched or output onto the data bus controller. Therefore, the bus on the side where the task has been completed is immediately released. As a result, the bus can be used for other tasks, increasing overall system processing power.

In addition, by placing the DMA interface controller at the intersection of the main bus and local bus, the number of times the local bus is used per unit of information transfer is reduced from two times in the conventional method to one time, reducing the exclusive time of the local bus during DMA transfer. The throughput of functional modules with local buses is improved.

〔Example〕

The present invention will be explained in detail below with reference to the embodiments shown in FIGS. 1, 2, 4, and 5, as well as FIGS. 3 and 7.

FIG. 1 is a block diagram showing an embodiment of the bus interface device of the present invention. In FIG. 1, 1 is a main memory, 2 is a main CPU, and 3 is a DMA interface controller.The DMA interface controller 3 is arranged at the contact point between the main bus and the local bus, and the address lines of the other party of the main bus and the local bus, Directly controls data and control lines. 4 is a local memory, 5 is a local CPU, and 6 is a local input/output device.

Figure 2 shows the DMA interface controller 3 in Figure 1.
FIG. 2 is a block diagram showing an example of functional components of the FIG.

There is a main side address counter 3a that outputs an address on the main bus side, a main side sequencer 3b that controls the control line on the main bus side, a local side address counter 3C that outputs an address on the local bus side, and a main side sequencer 3b that outputs an address on the local bus side. There is a local sequencer 3d that controls control lines, and in addition, a data bus controller 3e that controls data, a word counter 3f that manages the amount of data to be transferred, and a data transfer timing between buffers and between buffers and memory. It consists of a sequence controller 10 for controlling. The block consisting of the main side address counter 3a and main side sequencer 3b which handles the main side is called main memory access circuit A, and the block consisting of the local side address counter 3c and local side sequencer 3d which handles the local side is called local memory access circuit A. A transfer control circuit C is a block consisting of a data bus controller 3e, a word counter 3f, and a sequence controller 10, which are commonly used as a circuit B.

The main sequencer 3b and the local sequencer 3d are synchronized with each other by in-circuit signals, and the word counter 3f notifies each sequencer 3b, 3d of the remaining transfer amount.

The data bus controller 3e includes each sequencer 3b, 3
The direction of data and the number of pits are controlled by the signal d.

In the above configuration, execution of DMA transfer from local memory 4 to main memory 1 will be explained with reference to FIGS. 1 and 2. Main CPU2. Local CPU5. From the local input/output device 6 to the DMA interface controller (
(Hereafter referred to as DIC) When a DMA transfer command comes to 3, D
The IC 3 acquires the right to use the local bus by the local sequencer 3d, and takes in data at the address indicated by the local address counter 3c from the local memory 4.

When the data on the local side is determined, the main sequencer 3b acquires the right to use the main bus. The DIC 3 which has obtained the right to use the main bus writes data to the address of the main memory 1 indicated by the main side address counter 3a. After confirming that data has been stored on the main side, the DIC 3 activates the local sequencer 3d and starts capturing the next data.

In addition, each sequencer 3b, 3d receives a notification from the word counter 3f that the transfer amount has reached the set value, or sends a DM when an error occurs in the sequence on each bus.
End A transfer.

According to this embodiment, as shown in FIG. 3(a), the number of times the local bus is used during DMA transfer between the main memory 1 and the local memory 4 is compared to the conventional case shown in FIG. 3(b). DMA transfer efficiency is improved. Also, local C
It is less likely to interfere with the use of the local bus by r'U5, and has the effect of improving the processing capacity of the entire functional module.

Next, another embodiment of the present invention will be described using FIG. 4. FIG. 4 shows the data bus controller 3e of the transfer control circuit C shown in FIG.
FIG. 2 is a block diagram illustrating an embodiment using a First In First Out buffer. In Figure 4, we are now moving from local memory 4 to main memory 1.
When performing DMA transfer to the data buffer 9.2, if the data buffer 9.2 is empty, it becomes possible to import data from the local memory 4 regardless of the state of the main bus, and if there is data in the data buffer 9.1. At this time, it is possible to send data to the main memory 1 regardless of the state of the local bus. When data buffer 9.1 becomes empty, data is transferred from data buffer 9.2.

The sequence controller 10 controls the timing of data transfer between buffers and between buffers and memory. In FIG. 4, D indicates a data line, E indicates a main bus data line, and F indicates a local bus data line.

According to this embodiment, as shown in FIG. 6(b), it becomes possible to use the bus continuously and the actual data transfer speed increases, so the DMA transfer of the same amount of data as in the conventional method is possible. In addition to the effects of the embodiments shown in FIGS. 1 and 2, this also has the effect of further improving the processing capacity of the entire system.

Next, still another embodiment of the present invention will be described using FIG. 5. Figure 5 shows a circuit that arranges data buffers for two or more pieces of data in parallel in the transfer control circuit C of Figure 2, sends the data to an empty buffer, and extracts the data from the buffer where the data has entered (hereinafter referred to as data buffer). FIG. 2 is a block diagram showing an embodiment in which distributors (denoted as distributors 11 and 12) are provided. In FIG. 5, when a DMA transfer is now performed from the local memory 4 to the main memory 1, the local data distributor 12, which has received data from the local memory 4, transfers the data to the data buffer 9.3 and the data buffer 9.3. The main side distributor 11 takes out the data from the buffer written earlier and sends the data to the main memory 1. The sequence controller 1 to roller 10 control the data transfer timing between the local side distributor 12 and the local memory 4, the data transfer timing between the main side distributor 11 and the main memory 1, and the writing and reading of data in the data buffer. Control.

According to this embodiment, as shown in FIG. 6(b), it becomes possible to use the bus continuously and the actual data transfer speed increases, so the same amount of data as the conventional method can be used. The effective bus holding time during DMA transfer is shortened, and in addition to the effects of the embodiments shown in FIGS. 1 and 2, the processing capacity of the entire system can be further improved.

〔Effect of the invention〕

As explained above, according to the present invention, the number of times the local bus is occupied during DMA transfer between the main memory and the local memory is reduced to 1/2 compared to the conventional method, and the local bus can perform other tasks. , it is possible to improve the performance of a module having a local bus.

Also, DMA between main memory and local memory
Since the data transfer speed during transfer execution can be doubled compared to conventional methods, the actual bus exclusive time is reduced, and the information transfer capacity of the bus per unit time is increased, resulting in a functional module with a bus and a system with functional modules. This has the effect of being able to improve the abilities of people.

[Brief explanation of the drawing]

1 is a block diagram showing an embodiment of the bus interface device of the present invention, FIG. 2 is a block diagram showing an embodiment of the mechanical components of the DMA interface controller of FIG. 1, and FIG. 3 is a block diagram showing an embodiment of the mechanical components of the DMA interface controller of FIG. FIG. 4 is a diagram showing the flow of data during conventional DMA transfer, and FIG.
FIG. 5 is a block diagram in which a FIF○ buffer is used in the data bus controller shown in FIG. 5. FIG. 5 is a block diagram in which data buffers are used in parallel in the data bus controller in FIG. 7 is a diagram showing bus exclusive dust when performing DMA transfer when the embodiment shown in FIG. 2 and the embodiments shown in FIGS. 4 and 5 of the present invention are used, and FIG. FIG. 2 is a block diagram of a device having functions. 1... Main memory, 2... Main Cr'U, 3.
DMA interface controller, 3a... Main side address counter, 3b... Main side sequencer, 3c... Local side address counter, 3d...
・Local side sequencer, 3e...Data bus controller, 3f...Word number counter, 4...Local memory, 5...Local CI"'U, 6...I/O equipment, 9.1゜9 .2,9.3,9.4...Data buffer, 10...Sequence controller, 11.
...Main side data distributor, 12...Local side data distributor Figure 3 (α) (b) Shima 4 ward (α)

Claims (1)

[Claims] 1. Incorporating a main CPU that controls the entire system, a main bus that transmits information between individual functional modules, and a local CPU that exclusively processes individual functions within the individual functional modules. In a system that has the main bus for transmitting information inside the module and an independent local bus, and that transmits information by DMA transfer between memories installed on each bus, an access control system provided on the main bus side. a main memory access circuit that outputs a target address and performs data transfer with a main memory connected to the main bus having the target address;
A local memory access circuit provided on the local bus side outputs an address to be accessed and performs data transfer with a local memory connected to the local bus having the target address, and the main memory access circuit A bus interface device characterized in that a DMA interface controller having a transfer control circuit for mutually exchanging data between the main bus and the local memory access circuit is arranged at a contact point between the main bus and the local bus. . 2. F of two or more pieces of data in the transfer control circuit
A bus interface device according to claim 1, further comprising an IFO buffer. 3. A claim in which the transfer control circuit is provided with data buffers for two or more pieces of data in parallel, a circuit for sending data to an empty buffer, and a circuit for extracting data in the order of the buffers to which the data was sent. 2. The bus interface device according to item 1.