JPH0318144A - Lan adaptor - Google Patents

Abstract

PURPOSE:To heighten the efficiency of DMA transfer by performing data transfer among a LAN controller, a processing circuit, and a data transfer control circuit when no DMA is transferred. CONSTITUTION:Data transmission/reception with a LAN transmission line 10 is controlled with the LAN controller 12, and interface control for a host side bus 14 is performed with a bus controller 16. A memory 18 can be directly accessed by the controllers 12 and 16, and the arbitration of the request of direct access for the memory 18 is performed at the processing circuit 20. And the data transfer among the controller 12, the processing circuit 20, and the data transfer control circuit 22 is performed by evading a period where the data transfer of DMA is being performed between the LAN controller 12 and the processing circuit 20. Thereby, it is possible to make the control circuit 22 act for the access of the MPU 20 to the controller 12 without competing with the data transfer of DMA.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Actions Examples Effects of the Invention [Summary] Converting the computer system bus into a LAN transmission line Regarding the LAN adapter connected to the L, it is possible to perform internal DMA transfer efficiently.
The purpose of providing an AN adapter is to provide a LAN controller that controls data transmission and reception with the LAN transmission line, a bus controller that controls the interface to the upper level bus, and a memory that is directly accessed by the LAN controller and the bus controller. a data transfer control circuit that matches the width of data handled by the LAN controller and the processing circuit by buffering data transferred between the two; teeth,
A means for transferring data between the LAN controller when the direct access data transfer is not being performed, and a means for transferring data between the processing circuit and the processing circuit when the direct access data transfer is not being performed. and means for transferring data between. [Industrial Field of Application] The present invention connects a computer system bus to a LAN adapter that connects a LAN transmission line.

According to this type of adapter, data can be sent from the computer system bus to the LAN transmission path, and the
Data can be imported from the N transmission line onto the computer system bus. Therefore, it becomes possible to use the data on the upper side (Ill) on the LAN, and it becomes possible to use the data on the LANI on the upper side as well. [Prior Art] In the computer system shown in FIG.
(local storage unit) 50-1, PM (processor module) 52-1 provided respectively in 50-2
．． 52-2 is connected to the bus 14, and this bus 14
includes a disk adapter 54, a line adapter 56...
A LAN adapter is also connected.

FIG. 8 shows the configuration of a conventional LAN adapter 58, in which transmission and reception of data (frames) to and from other systems via the LAN transmission line 10 is performed via the LAN.
It is controlled by a controller 12.

Also, the interface control for the upper-level bus 14 is performed by the bus controller 16, and the memory 18 is controlled by the LAN controller 12 and the bus controller 16.
is directly accessed (DMA). This memory 18 is provided in the MPU 20, and the MPU
20, the LAN controller 12 for the memory 18;
DMA requests of bus controller 16 are being arbitrated.

As a result, the LAN controller 12
．． Collisions between DMA transfers performed by the bus controller 16 are avoided, and these LAN controllers 12. Data is transferred between the LAN transmission path 10 and the upper-level bus 14 via the bus controller 16 during the memory day. Note that a bus 60 is provided inside the LAN adapter 5, and the LAN controller 12. Bus controller 16. MPU20 is connected. Here, the bus width of the LAN controller 12 and the MPU 20
If the bus width of the internal bus 60 is different from that of the internal bus 60, a data transfer control circuit is provided between them.

In this data diversion control circuit, the LAN controller 12
A data operation is performed to match the congestion (bus width) of data handled by the processing circuit 20 and the processing circuit 20 by buffering the data transferred between the two. For example, if the data width of the LAN controller 12 is 2 bytes and the bus width of the MPU 20 is 4 bytes, the data transferred from the LAN controller 12 to the MPU 20 is divided into two 2-byte units and DMA-transferred to the data transfer control circuit. ．． In the data transfer control circuit, those 2-byte wide data are
It is converted into byte-wide data, and the 4-byte-wide converted data is transferred to the MPU 20 by DMA. Furthermore, when data is transferred by DMA from the MPU 20 to the LAN controller 12, the 4-byte width data transferred from the MPU 20 to the data transfer control circuit by DMA is
The data is divided into byte-wide data and sequentially transferred to the LAN controller 12 by DMA.

Therefore, the bus width of the LAN controller 12 is
It becomes possible to handle the bus width as the same as a bus width of 0, and it becomes unnecessary for the LAN controller 12 to send out a transfer request every time 2-byte data is transferred by DMA. Therefore, the DM of the LAN controller 12, which has a narrow bus width,
The A transfer request is sent in units of the wide bus width of MPU 20, and the number of times the request is sent is reduced. As a result, it is possible to reduce the time that the LAN controller 12 occupies the internal bus 60 and increase the data transfer speed between the LAN transmission line 10 and the bus 14.

[Prior Art] However, in the conventional LAN adapter (58) provided with a data transfer control circuit, data transferred by DMA between the LAN controller 12 and the MPU 20 is buffered. A certain amount of time is required from the start of DMA data transfer between the data transfer control circuit and the LAN controller 12 until the start of DMA data transfer between the MPU 20 and the data control circuit.

Therefore, if a request to access the internal register of the LAN controller 12 is issued from the MPU 20 during that time, the data transfer control circuit and the LAN controller 12
Conflict occurs between DMA transfer between MPIJ 20 and access to LAN controller 12 of MPIJ 20. If a conflict occurs, DMA transfer must be given priority. The present invention has been made in view of the above-mentioned conventional circumstances, and
The purpose of this is to enable efficient DMA transfer even if a processing circuit access request to the LAN controller is issued while DMA transfer is being performed between the LAN controller and the data transfer control circuit. Our goal is to provide LAN adapters that will [Means for Solving the Problems] In order to achieve the above object, a LAN adapter according to the present invention is configured as shown in FIG. In the same figure,
Data transmission and reception with the LAN transmission line 10 is controlled by a LAN controller 12, and interface control with respect to the upper-level bus 14 is performed by a bus controller 16. And LAN controller 12 and bus controller 1
6, the memory 18 is directly accessed, and a request for direct access to the memory 18 is arbitrated in the processing circuit 20 provided with this memory 18. In addition, the data transfer control circuit 22 buffers data transferred between the LAN controller 12 and the processing circuit 20.
2 and the width of data handled by the processing circuit 20 are matched.

Here, the data transfer control circuit 22 includes means 24 and means 2.
6 is included.

Among these, the means 24 transfers data between the LAN controller 12 and the LAN controller 12 when the direct access data transfer is not performed.

Further, the means 26 transfers data between the processing circuit 20 and the processing circuit 20 when the direct access data transfer is not performed. [Operation] In the present invention, the LAN controller 12. Since data is transferred between the processing circuit 20 and the data transfer control circuit 22, the DMA
It becomes possible to have the data transfer control circuit 22 access the LAN controller 12 by the MPU 20 without conflicting with data transfer.

[Example] Hereinafter, a LAN adapter according to the present invention (
A preferred embodiment of 5th day) will be explained below. In Figure 2, M
The PU20 is provided with a memory 18, and the MPU
A data transfer control circuit 22 is provided between the LAN controller 20 and the LAN controller 12. And between the LAN controller 12 and the data control circuit 22, the register address inside the LAN controller,
Read instruction (read instruction), write instruction (write instruction). DMA address. DMA data. Request for DMA transfer (HOLD). DMA transfer authorization (HLDA) is being transferred.

Also, between the MPU 20 and the data transfer control circuit 22,
N command. OUT command. Access address and subsequent instruction (read instruction) when issuing IN and OtJT instructions
．． Write instruction (write instruction). DMA address. DM
A data, bus use request (BUS-REQ). Bus use grant (BUS-GRANT) is being transferred. In FIG. 3, the configuration of the data transfer control circuit Pi22 is explained, and the internal processing circuit 30 performs buffering of DMA data.

Further, the data transfer control circuit 22 includes a register 32 (REQ
). 34 (FIN). 36 (i-DATA). 3B
(o-DATA). 40 (i-ADH), 42 (
o-ADR), which are accessed by internal processing circuitry 30. Among these, the register 32 has the MPU 20 for the LAN controller 12.
Data indicating the presence or absence of an access request is written to the register 34, and data indicating completion of the requested access operation is written to the register 34. Further, the register 36 holds data read from the LAN controller 12 (when an IN command is issued), and the register 38 holds data written to the LAN controller 12 (when an OtJT command is issued). Additionally, the register 40 holds the successive address of the LAN controller 12 (when an IN command is issued), and the register 42 holds the write address of the LAN controller 12 (when an OUT command is issued).

The first bit of the register 32 is used to indicate that the MPU 20 has issued a request to read the internal register of the LAN controller 12, and the next bit is used to indicate that the MPU 20 has issued a request to write to the internal register of the LAN controller 12. It is used to indicate that.

Here, in the internal processing circuit 30, the above register 3
2.34.36.3B. Transfer of data (the above-mentioned commands, instructions, etc.) using 40.42 is performed between DMA data transfers.

For example, when the MPU 20 writes data to the internal register of the LAN controller 12, the internal processing circuit 3 indicates that no DMA transfer is being performed with the MPU 20.
If confirmed as 0, the register address and write data sent from the MPU 20 are received by the internal processing circuit 30,
These are stored in registers 42 and 38, respectively, and the second bit of register 32 is set to a value indicating this request.

And between the LAN controller 12 and D lvi A
When it is confirmed that no transfer is being performed, a write instruction is given from the internal processing circuit 30 to the LAN controller 12, and the LAN controller 12 is placed in the write mode.

Furthermore, among the internal registers of the LAN controller 12,
The data held in the register for three days is written to the address indicated by the register 42, and when the completion of the writing is confirmed, the second bit of the register 34 is set. As a result, a subsequent deletion instruction is issued to the MPU 20, and completion of writing is notified.

However, this interrupt is issued when it is confirmed that no DMA transfer is being performed with the MPU 20. Furthermore, when the MPU 20 reads data from the internal register of the LAN controller 12, if it is confirmed that no DMA transfer is being performed with the MPU 20, the register address sent from the MPU 20 is written to the register 40. , the first bit of register 32 is set.

When it is confirmed that no DMA transfer is being performed with the LAN controller 12, the read instruction is transferred to the LAN controller 12.
is applied to the controller 12 and the LAN controller 12
is considered to be a continuous mode. As a result, data is read from the designated register inside the LAN controller 12 indicated by the address held in the register 40 and written to the register 36.

Furthermore, when the completion of reading is confirmed, the second bit of the register 34 is set.

Thereafter, when DMA data transfer is not being performed with the MPU 26, a read instruction is given to the MPU 20 by interruption. When this interrupt is given, the data transfer control circuit 22
The data in the register 36 is transferred to the MPU 20 when DMA transfer is not being performed between the MPU 20 and the MPU 20 .

Then, the interrupt request from the LAN controller 12 is
In the case where P U 2 0 accepts the request, if it is confirmed that no DMA transfer is being performed with the MPU 20, the register inside the target LAN controller 12 (
The address indicating the address (where data indicating the detailed cause of the interrupt is stored) is stored in the register 40, and the address in the register 32
The first bit of is set. Next, it is determined whether or not DMA transfer is being performed with the LAN controller 12. If it is confirmed that the DMA transfer is not being performed, the LAN controller 1
2 is assumed to be a read mode.

Further, data indicating the detailed cause of the interrupt is read from the register inside the LAN controller 12 indicated by the address held in the register 40, and the data is stored in the register 36.
is written to. Once the completion of this writing is confirmed,
The first bit of register 34 is set.

When it is confirmed that DMA transfer is not being performed with the MPU 20, a continuation instruction is given to the MPU 20 by an interrupt.

Thereafter, when it is confirmed again that DMA transfer is not being performed with the MPU 20, the data in the register 36 is transferred to the MPU 20. In Figure 4, MPU20 is LA
The operation when writing data to the internal register of the N controller 12 is explained.

In the figure, a DMA transfer request is issued from the LAN controller 12 (HOLD), and when the transfer is permitted (HLDA), the data wordO. wordl is LA
The data are sequentially transferred from the N controller 12 to the data transfer control circuit 22. and request for bus use (BUS-RE
Q) is issued from the data transfer control circuit 22 to the MPU 20, and when the request is granted (BUS GRANT)
, data wordy. Data W assembled from wordl
ORDO is transferred from the data transfer control circuit 22 to the MPU 20
MA is transferred.

Next time, DM from the LAN controller 12
ATransferred data wo r d 2. word3
The assembled data WORDI is transferred to data transfer control circuit 2.
2 is transferred by DMA to the MPU 20. Furthermore, when the data wordy and wordl are being DMA transferred from the LAN controller 12 to the data transfer control circuit 22, the data WORDO is being transferred from the data transfer control circuit 22 to the MP
Before the DMA transfer to U20, the OUT instruction is sent to MPU2.
0 (a) and given to the data transfer control circuit 22. Then, when the DMA transfer of the data wordy and wordl is completed, the LAN controller 12 is put into the write mode, and the data (W-DATA) is written into the specified register inside the LAN controller 12 (b).

The end occurs after the data WORDO is DMA transferred to the MPU 20 and before the next DMA transfer is started.
Notification to U20 via interrupt (c). FIG. 5 explains the operation when the MPU 20 reads data stored in the internal register of the LAN controller 12.

In this case, the data wordy and wordl are connected to the LAN.
During DMA transfer from the controller 12 to the data transfer circuit 22 and before data WORDO is DMA transferred from the data transfer control circuit 22 to the MPU 20, an IN command (a) is issued and given to the data transfer control circuit 22. ．． When the DMA transfer of data word and wordl is completed, the LAN controller 12 is placed in read mode, and the data (
R-data) is read (b). At the end of this reading, the data WORDO is sent to the MPU 20.
The MPU 20 is notified by an interrupt after the DMA transfer is performed and before the next DMA transfer is started (C). Furthermore, when the data WORDI is DMA transferred from the data transfer control circuit 22 to the MPU 20 and the next DMA transfer is completed, the data (R-data) that was read from the LAN controller 12 to the data transfer control circuit 22 is transferred.
is transferred from the data transfer control circuit 22 to the MPU 20 (d). In FIG.
20 gives an interrupt request to the data transfer control circuit 22 (a).

Next, after the first DMA transfer of data word and wordl is completed and before the next DMA transfer is started, the L
The AN controller 12 is put into read mode and the interrupt ! The register storing data (R-data) indicating the ¥ detail factor is read (b).

When the DMA transfer of data WORDO is completed, the data transfer control circuit 22 notifies the MPU 20 of the completion of reading by an interrupt before the next DMA transfer is started (C). Thereafter, when the second DMA transfer is completed, the interrupt detail factor data (R-data) that has not been read from the LAN controller 12 to the data transfer control circuit 22 is read from the data transfer control circuit 22 to the MPU 20. As explained above, according to this embodiment, the data transfer control circuit 22 acts as the access of the MPU 20 to the LAN controller 12 when DMA transfer is not performed between the LAN controller 12 and the MPU 20, so that the LAN controller Conflict between access to 12 and DMA transfer can be avoided. Therefore, an access request to the LAN controller 12 is transmitted between the LAN controller 12 and the data transfer control circuit 2.
No matter what timing is issued from the MPU 20 while DMA transfer is being performed between the data transfer control circuit 22 and the LAN controller, the data transferred by DMA from the LAN controller will not overflow.

Therefore, the DMA transfer data will not be lost, making it possible to improve the efficiency of DMA transfer within the LAN adapter (5 days).

[Effects of the Invention] As explained above, according to the present invention, data transfer is performed between the LAN controller, the processing circuit, and the data transfer control circuit when DMA transfer is not being performed. By having the data transfer control circuit perform processing @path accesses to the LAN controller, conflicts between these accesses and DMA transfers can be avoided. Therefore, DMA transfer can be performed reliably without errors, and DMA
This makes it possible to increase the efficiency of transfer.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of the invention, Fig. 2 is an explanatory diagram of the configuration of the embodiment, Fig. 3 is an explanatory diagram of the configuration of the data transfer control circuit in the embodiment, and Figs. 4, 5, and 6 are illustrations of the implementation. FIG. 7 is an explanatory diagram of the configuration of a computer system using a LAN adapter; FIG. 8 is an explanatory diagram of the configuration of a conventional LAN adapter. 32, 34, 36. 38, 40, 42 registers.

Claims (1)

[Claims] LA that controls data transmission and reception with the LAN transmission line (10)
N controller (12), a bus controller (16) that performs interface control for the upper side bus (14), and a memory (18) that is directly accessed by the LAN controller (12) and bus controller (16). (18)
a processing circuit (20) that arbitrates requests for direct access to
), LAN controller (12), and processing circuit (20)
A data transfer control circuit (2) that matches the width of data handled by the
2), and the data transfer control circuit (22) transfers data between the LAN controller (12) and the LAN controller (12) when the direct access data transfer is not performed between the LAN controller (12) and the LAN controller (12). and means (26) for transferring data to and from the processing circuit (20) when said direct access data transfer is not occurring between said processing circuit (20). A LAN adapter characterized by: