JPH05324535A - Data transfer device - Google Patents

Abstract

PURPOSE:To operate a command chain by providing a transfer mode storage means for setting of the transfer mode including a transfer form and interrupt permission, a transfer processing execution means, and an end report generating means. CONSTITUTION:A DMA 203 is provided with a control register 233, a transfer processing execution part 234, an end report generating part 235, and a queue control part 236. Permission or inhibition of end report generation can be set to the transfer mode storage means to obtain the same effect as masking so that the end report generating means 235 generates the end report in accordance with this setting. Therefore, this setting can be performed simultaneously with command setting, and operation of the command chain is possible. Especially, if the execution indication of the command chain is set by the control register 233, debugging is easier than the case that the execution indication of the command chain is set by another register, and programming is easy.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device.

[0002]

2. Description of the Related Art Conventionally, a plurality of data transfer paths are provided, and a DMA (Direct Memory Access) is arranged for each of the ports,
There is an idea to achieve various types of data transfer by controlling the data transfer direction at each port by this DMA.

For example, when considering a system having a CPU, a main memory, a disk, etc., the main memory and the CP
Connects with U, disk, etc. by multiple data transfer paths,
The DMA arranged in each of the ports makes it possible to achieve various transfer modes defined by the data transfer direction, the other party, and the like.

FIG. 2 shows the configuration of the data transfer system assembled according to the conventional idea.

In this figure, 101 and 131 are I / Os.
These I / O ports 101 and 131 are
It is connected to a CPU, a disk controller, or the like. Hereinafter, for convenience of explanation, the I / O port 101 is a CPU.
In addition, the I / O port 131 is assumed to be connected to the disk controller. 102 to 104 are DMAs, 10
7 is a memory, and here, I / O ports 101 and D
Between MA 102, I / O port 131 and DMA 104
, DMA 102 and DMA 104, DMA 1
02 and DMA103, DMA104 and DMA10
3 and a system configuration having a data transfer path between the DMA 103 and the memory 107.

[0006] The I / O port 101, when writing data to the memory 107 and when transferring data to the I / O port 131, has a DReq indicating a data transaction request.
A signal (DMA request signal) is output on the signal line 109, and then, a DAck signal (DMA permission signal) is output on the signal line 110, and then write or transfer data is output on the data bus 108.

When reading data from the memory 107 and when reading data from the I / O port 131, the I / O port 101 outputs a DReq signal indicating a data request onto the signal line 109, After that, when the DAck signal is output to the signal line 110, the data on the data bus 108 is taken in. Then I / O port 1
01 will send the fetched data to the CPU.

[0008] The I / O port 131, when writing data to the memory 107 and transferring data to the I / O port 101, has a DReq indicating a data transaction request.
The signal is output onto the signal line 133, and thereafter, the DAck signal (DMA permission signal) is output onto the signal line 134, and then the write or transfer data is output onto the data bus 132.

Further, the I / O port 131 outputs a DReq signal indicating a data request onto the signal line 131 when reading data from the memory 107 and when reading data from the I / O port 101. After that, when the DAck signal is output to the signal line 133, the data on the data bus 132 is taken in. Then I / O port 1
The reference numeral 31 sends the fetched data to the disk controller.

The DMAs 102 to 104 have control registers, the contents of these registers are programmed by the CPU, and the DMAs 102 to 104 operate according to the contents of the setting command.

2B to 2D show the DMA 103 as an example of the control register.
As described above, the DMA 103 is the DMA 102 and the DMA
The control register 104 has a structure corresponding to the transfer destinations of 104 and the memory 107.

The control register includes a mode display register (MODE) as shown in FIG. 2 (b) showing the contents of the transfer command and an address display as shown in FIG. 2 (c) showing the start address of the transfer destination memory. Register (Ad
2d) and a data transfer number display register (Len) as shown in FIG. 2D showing the data transfer number.

The mode display register has a transfer direction display bit (bit 0) indicating the data transfer direction and a partner DMA display bit (bits 1 and 2) indicating the partner DMA.

When the transfer direction indication bit is "0", it indicates the read mode, and when it is "1", it indicates the write mode. Counter DMA display bit is bit 1
Is a bit for the DMA 102, and bit 2 is the DMA 10
4 is a bit corresponding to 4, and when “1” is set in each bit, the DMA 102 corresponding to that bit
Alternatively, 104 indicates that it is a partner with which data transfer is performed. For example, the transfer partner is D
In the case of MA 102, bit 1 corresponding to this is set to "1", and bit 2 corresponding to DMA 104 is set to "0".

The address register is for writing the start address of the transfer target area of the memory 107, and is counted up and updated with the transfer processing. As a result, the access address for each transfer process is specified. The data transfer number display section counts down in accordance with the transfer processing, and thus all the transfer target data can be transferred reliably.

The length register is for writing the number of data to be transferred, and is counted down in accordance with the transfer processing, and when it becomes "0", the transfer processing is completed.

The structure of the control register of the DMA 103 has been described above. However, the control registers of the DMAs 102 and 104 have the same structure, but since their transfer partners are the I / O port or the DMA, their control is controlled. There is no register that is necessary when the other party has memory, that is, the address register,
Other mode registers and length registers are similarly provided. Regarding the mode register, the DMA 102
As for the partner DMA display bit of, for example, bit 1 is DMA1
03, bit 2 is for the DMA 104, and the partner DMA display bits of the DMA 104 are, for example, bit 1 for the DMA 102 and bit 2 for the DMA 103.

Reference numeral 105 denotes a bus controller, which is a DMA
In response to a BRQ (Bus Request) signal from 118, the internal bus is arbitrated and a bus permission signal is given to the DMA 103 when the bus use right is set.

Reference numeral 106 denotes a mode (write / write) of the memory 107.
A memory controller that performs read) control, and DMA
A mode of the memory 107 is set according to a read / write instruction from 103.

Each of the DMAs 103 to 105 generates an end notification signal on the signal lines 124, 125 and 126 at the end of its own transfer process. 127 is a mask setting register,
Reference numeral 128 is a masking AND gate opposite to each of the DMAs 103 to 105, and 129 is an OR gate.
The end notification signals from 03 to 105 are input to the OR gate 129 via the corresponding AND gates 128, and C from the OR gate 129 via the signal line 130.
Supplied to PU. The mask setting register 127 is for each DM
A DMA 10 is provided with bits corresponding to A103 to A105.
This is to prevent the CPUs other than the ones requiring the end notification among 3 to 105 from being transmitted. That is,
What the CPU wants to know is the termination of the DMA located at the most downstream side of the transfer path. Therefore, it is necessary to mask the end notification from another DMA. Therefore, the register 127
Of the respective bits, only the bit corresponding to the DMA requiring the end notification is set to the logical "0", and the bit corresponding to the other DMA is set to the logical "1".
28 is opened and closed to pass or prohibit the end notification.

Next, the operation of the system configured as above will be described. First, when executing data transfer in the system, each DMA 102 is executed by the CPU.
Programming of all the control registers of ~ 104 will be completed, and then a start signal will be given to each DMA. Here, a case of writing data from the I / O port 101 to the memory 207 will be described.

In this case, the DMA 10 is involved in the transfer.
2, 103, and their respective control registers are set as follows.

The control register of the DMA 102 is
The direction display bit 0 of the mode display register is “1” because it is the write mode, and the transfer destination DMA display bit 1
For bit 2, since the other party is the DMA 103, bit 1 is "1" and bit 2 is "0".

The control register of the DMA 103 is
The direction display bit 0 of the mode register is "1" because it is the write mode, and the transfer partner DMA display bits 1 and 2 are "1" because the partner is the DMA 102.
Bit 2 is set to "0".

In the mask register 127, the bits of the DMA 102, DMA 103,
If it corresponds to the DMA 104, the most downstream DMA
Since only the bit corresponding to 103 is set to 0, "101"
Is set.

With the above settings, the DMA 102 initially waits for the DReq signal indicating the data transaction request from the I / O port 101, DMA1.
03 is waiting for the Req signal from the DMA 102.

When the DReq signal appears on the signal line 109, the start condition is satisfied thereby, so that the DMA1
02 confirms that the internal buffer is empty, and then confirms that signal line 1
Issue a DAck signal to 10 and then I / O port 10
The data sent from 1 is received via the bus 108 and written in the internal buffer.

When data is present in the internal buffer due to this writing, the DMA 102 causes the signal line 112 to cause the DMA 103 to receive the data in the internal buffer.
Issue a Req signal on top.

Then, in response to this, the DMA 103 confirms that the internal buffer is empty, and then outputs an Ack signal to the signal line 113. Then, the DMA 102 changes the signal line 1
The Req signal on 12 is cleared and the data in the internal buffer is sent out on the bus 111. Since the DMA 103 outputs the Ack signal onto the signal line 113 and is in a data waiting state on the bus 111 at the same time, the data sent from the DMA 102 on the bus 111 is stored in the internal buffer.

When data also exists in the internal buffer of the DMA 103, the BRQ is applied to the signal line 118.
Send a (bus request) signal.

Then, the bus controller 105 determines that D
The BRQ signal from the MA 103 is set as an arbitration target, and the DMA1
When the bus use right is set in 03, a BAK (bus use permission) signal is output on the signal line 119. DMA103 is
Upon receiving this BAK signal, a write command signal is output on the signal line 120. As a result, the memory controller 106 sets the signal line 123 on the write mode. And D
The MA 103 outputs an address signal on the signal line 121 and a data signal on the signal line 122, and the memory 107
Write data to.

The processing proceeds in this way, and the DMA 10
2. The DMA 103 ends the processing relating to the transfer processing in this order, and at the end of each processing, the signal lines 124,
An end notification signal is output on 125. This end notification signal is output from the DMA 102 first, but since the end notification of this DMA 102 is masked by the AND gate 128, CP
Not transmitted to U. Therefore, only the end notification of the DMA 103 is notified to the CPU.

By the way, recently, it is also considered to perform a command chain in such a system.

That is, a plurality of transfer commands are set at once in the control register of each DMA, and the plurality of commands are continuously executed.

In this case, the mask register is also set at the same time.

[0036]

However, since the mask register is set, the command chain is considered to have no merit.

For example, when two commands are set in the DMA, if the first command requires a mask of "01" and the second command requires a mask of "10", the mask is set for each command. It will be set again. The timing of this setting can be taken by the end notification of the previous command, but until this setting is completed, DMA processing cannot be performed, and in the end, it becomes close to command resetting and operation as a command chain. Is virtually impossible.

The present invention has been made in view of the above problems of the prior art, and an object of the present invention is to provide a data transfer device capable of operating a command chain.

[0039]

In the data transfer apparatus of the present invention, a DMA is provided for each port of a plurality of data transfer paths.
And a transfer mode storage unit for setting a transfer mode including a transfer mode and interrupt permission,
Transfer processing executing means for executing the data transfer processing in the transfer mode indicated by the transfer mode storing means, and when the processing of the transfer processing executing means is completed and the interrupt permission is set in the interrupt permission storing means. And a termination notification generating means for generating a termination notification to the CPU.

The above-mentioned transfer mode storage means can be constituted by a control register in which a plurality of them are combined in a queue structure and an execution instruction of the command chain can be set.

[0041]

According to the present invention, it is possible to set permission / prohibition for the generation of the end notification in the transfer mode storage means, and the end notification generation means generates the end notification according to the presence or absence of the setting, similarly to the mask. Since the effect of is obtained, the setting can be performed at the same time as the command setting, and the command chain can be operated.

In particular, if the command register execution instruction is set in the control register, debugging is easier than when the command chain execution instruction is set in another register. It also makes programming easier.

[0043]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a system configuration of a data transfer apparatus according to an embodiment of the present invention.

First, in FIG.
9 is an I / O port, and these I / O ports 201,
Reference numeral 229 is connected to a CPU, a disk controller, and the like. Hereinafter, for convenience of description, the I / O port 20
1 is connected to the CPU and the I / O port 229 is connected to the disk controller. 202-204 is D
MA and 207 are memories, and here, between the I / O port 201 and the DMA 202, the I / O port 229 and the D are connected.
MA204, DMA202 and DMA204, DMA202 and DMA203, DMA204
And the DMA 203, and between the DMA 203 and the memory 207, data transfer is performed.

This I / O port 201 is connected to the memory 207.
DR indicating a data transaction request when writing data to the I / O port 229 or when writing data to the I / O port 229
The eq signal (DMA request signal) is output on the signal line 209, and then the DAck signal (DMA permission signal) is output on the signal line 210, and then write or transfer data is output on the data bus 208.

When reading data from the memory 207 and when reading data from the I / O port 229, the I / O port 201 outputs a DReq signal indicating a data request onto the signal line 209, After that, when the DAck signal is output to the signal line 210, the data on the data bus 208 is taken in. Then I / O port 2
01 will send the fetched data to the CPU.

The I / O port 229, when writing data to the memory 207 and when transferring data to the I / O port 201, has a DReq indicating a data transaction request.
A signal (DMA request signal) is output on the signal line 231, and then, a DAck signal (DMA permission signal) is output on the signal line 232, and then write or transfer data is output on the data bus 230.

When reading data from the memory 207 and when reading data from the I / O port 201, the I / O port 229 outputs a DReq signal indicating a data request onto the signal line 231. After that, when the DAck signal is output to the signal line 231, the data on the data bus 230 is taken in. Then I / O port 2
29 sends the fetched data to the disk controller.

The DMAs 202 to 204 have control registers, the contents of these registers are programmed by the CPU, and the DMAs 202 to 204 operate according to the contents of the setting command.

FIG. 1B shows the DMA 203 as an example of the internal structure of the DMA.

As shown in this figure, the DMA 203 comprises a control register 233, a transfer processing execution unit 234, an end notification generation unit 235, and a queue control unit 236.

As described above, the control register 233 has the DMA 203, the DMA 202, the DMA 204, and the memory 207 as the transfer partners, and the control register has a structure corresponding thereto.

This control register has a mode display register (MODE) as shown in FIG. 1C showing the contents of the transfer command and an address display as shown in FIG. 1D showing the start address of the transfer destination memory. Register (Ad
d) and a data transfer number display register (Len) as shown in FIG. 1E showing the data transfer number.
As shown in (f), it consists of a queue-structured FIFO.

The mode display register includes a transfer direction display bit (bit 0) indicating the data transfer direction, a partner DMA display bit (bits 1 and 2) indicating the partner DMA, an interrupt enable display bit (bit 6), and a command chain. The command display unit is provided with a command chain display bit (bit 7) indicating that the command is to be performed and other display bits (bits 3 to 5).

When the transfer direction display bit is "0", it indicates the read mode, and when it is "1", it indicates the write mode. Counter DMA display bit is bit 1
Is a bit for the DMA 202, and bit 2 is the DMA 20
4 is a bit corresponding to 4, and when “1” is set in each bit, the DMA 202 corresponding to that bit
Alternatively, 204 indicates that it is a partner with which data transfer is performed. For example, the transfer partner is D
In the case of MA 202, bit 1 corresponding to this is set to “1”, and bit 2 corresponding to DMA 204 is set to “0”.

The interrupt permission display bit indicates that it is in a disabled state when it is "0", and it indicates that it is in a enabled state when it is "1". Therefore, this interrupt permission display bit is set to "1". The end interrupt signal is generated at the end of the transfer process only when the transfer process is completed, and the end interrupt signal is not generated when the transfer process is completed when the bit is set to "0".

This interrupt permission display bit is the DMA2 concerned.
It is set to "1" only when 03 is located on the most downstream side of the transfer path, and is set to "0" otherwise.

The command chain display bit indicates that the command chain is not executed when it is "0", that is, another command is not continuously set after the command which is currently executed, and "1". In the case of, the command chain is performed, that is, it indicates that another command is continuously set after the transfer command which is the current execution target.

The address display section is counted up and updated in accordance with the transfer processing, whereby the access address for each transfer processing is specified. The data transfer number display section counts down in accordance with the transfer processing, and thus all the transfer target data can be transferred reliably.

Next, the control register is constituted by the FIFO as described above, and the mode display register, the address display register and the data transfer number display register are set to 1
It is set as a set and is shifted in units of this set each time one transfer process is completed.

The structure of the control register of the DMA 203 has been described above. However, the control registers of the DMAs 202 and 204 have the same structure, but since their transfer partners are the I / O port or the DMA, their control is controlled. The register does not have a register necessary when the other party includes a memory, that is, an address display register, and the other mode display register and data transfer number display register are similarly provided. Regarding the mode display register, the transfer partner DMA display bit of the DMA 202 is
For example, bit 1 is for DMA 203, bit 2
Is for the DMA 204, and the transfer partner DMA display bit of the DMA 204 is, for example, bit 1 is DMA2.
02, bit 2 is for DMA 203. Hereinafter, this setting will be described.

Returning to FIG. 1B, the transfer processing execution unit 234.
Is a part that performs the above transfer processing according to the setting contents of the control register 233.
Give to 36. The end notification generation unit 235 confirms bit 6 of the mode register in response to the execution end notification signal from the transfer process execution unit 234, and when the content is "1", the signal line 22
5. Generate end notification on 5. The queue control unit 236 confirms bit 7 of the mode register in response to the execution end notification signal from the transfer process execution unit 234, and when the content is "1", shifts the control register by one command set.

Returning to FIG. 1A, 205 is a bus controller that arbitrates the internal bus, and 206 is a memory controller that controls the mode (write / read) of the memory 207.

The operation of the system configured as above will be described. First, when executing data transfer in the system, each of the DMAs 202 to 20 is executed by the CPU.
Programming will be completed for all the control registers of No. 4 and then a start signal will be given to each DMA. Here, the process () of writing the data from the I / O port 201 to the memory 207 is executed, and then the data from the I / O port 201 is input to the I / O port 2
The process () for transferring to 29 is executed, and finally the memory 2
A case of executing the process () for transferring the data from 07 to the I / O port 201 will be described. Like this 3
When two processes are continuously executed, the DMA 202 is involved in all of the processes, and therefore its control register is programmed with a command queue structure so that the processes are executed in that order.
Since 3 is involved in processing, its control register is programmed with a command queue structure so that processing is executed in that order.
, The control register is programmed only for the processing so that only the processing is executed. At this time, the address display register and the transfer number display register are set at the same time. Also, depending on how the interrupt permission display bit is set, an end notification may be generated only when the last process is completed, or an end notification may be generated at each end of each process, or Of these, the end notification can be generated only at the end of the required process for a special reason, for example, only at the end of the process. The case where the end notification is generated only in this case will be described.

Regarding each process, each DMA 202 to 20
The setting contents of the control register 4 are as follows.

When writing data from the I / O port 201 to the memory 207.

In this case, the DMA 20 is involved in the transfer.
2, 203, and their respective control registers are set as follows.

The control register of the DMA 202 is
The direction display bit 0 of the mode display register is “1” because it is the write mode, and the transfer destination DMA display bit 1
Bit 2 is "1" because the other party is the DMA 203, bit 2 is "0", interrupt enable bit 6 is "0" because it is not the most downstream of the transfer path, and the command chain display bit is the subsequent processing. From doing "1"
Is set.

The control register of the DMA 203 is
The direction display bit 0 of the mode display register is “1” because it is the write mode, and the transfer destination DMA display bit 1
For bit 2, since the other party is the DMA 202, bit 1 is "1", bit 2 is "0", and interrupt enable bit 6 is the most downstream of the transfer path, but as described above, only at the end of the last process. The interrupt notification is set to “0”, which is prohibited because the interrupt notification is generated, and the command chain display bit is set to “1” because the subsequent processing is performed.

Data from the I / O port 201 is transferred to I
When transferring to the / O port 229.

In this case, the DMA 20 is involved in the transfer.
2, 204, and their respective control registers are set as follows.

The control register of the DMA 202 is
The direction display bit 0 of the mode display register is “1” because it is the write mode, and the transfer destination DMA display bit 1
Bit 2 is “0” because the other party is the DMA 204, bit 2 is “1”, the interrupt permission bit 6 is “0” because it is not the most downstream of the transfer path, and the command chain display bit is the subsequent processing. From doing "1"
Is set.

The control register of the DMA 204 is
The direction display bit 0 of the mode display register is "0" because it is the read mode, and the transfer partner DMA display bit 1,
Bit 2 is "1", bit 2 is "0", and interrupt permission display bit 6 is the most downstream of the transfer path because the other party is the DMA 202, but as described above, at the end of the last process. Only the interrupt notification is generated, so the prohibition "0" is set, and the command chain display bit is set to "0" because there is no subsequent processing.

When transferring data from the memory 207 to the I / O port 201.

In this case, the DMA 20 is involved in the transfer.
2, 203, and their respective control registers are set as follows.

The control register of the DMA 202 is
The direction display bit 0 of the mode display register is "0" because it is the read mode, and the transfer partner DMA display bit 1,
2 is a series of processes in which bit 1 is “1”, bit 2 is “0” because the other party is the DMA 203, interrupt enable bit 6 is the most downstream of the transfer path, and the process is set in the control register. Since it is the last, the permission state is set to "1" and the command chain display bit is set to "0".

The control register of the DMA 203 is
The direction display bit 0 of the mode display register is "0" because it is the read mode, and the transfer partner DMA display bit 1,
Bit 2 is "1" because the other party is the DMA 202, bit 2 is "0", interrupt enable bit 6 is "0" which is prohibited because it is not the most downstream of the transfer path, and the command chain display bit is this Also in this case, "0" is set.

Then, by the above setting, first, DMA
202 and 203 are processing modes, and DMA204 is a processing mode. Initially, the DMA 202 is in a state of waiting for a DReq signal indicating a data transaction request from the I / O port 201, and the DMA 203 is in a state of waiting for a Req signal from the DMA 202. The DMA 204 waits for the Req signal on the signal line 217 from the DMA 202.

When the DReq signal appears on the signal line 209, the start condition is satisfied by this, so that the DMA2
02 confirms that the internal buffer is empty, and then confirms that signal line 2
Send DAck signal to 10 and then I / O port 20
The data sent from 1 is received via the bus 208 and written in the internal buffer.

When data is present in the internal buffer due to this writing, the DMA 202 causes the signal line 212 to cause the DMA 203 to receive the data in the internal buffer.
Issue a Req signal on top.

In response to this, the DMA 203 confirms that the internal buffer is empty, and then issues an Ack signal to the signal line 213. Then, the DMA 202 causes the signal line 2
The Req signal on 12 is cleared and the data in the internal buffer is sent out on the bus 211. Since the DMA 203 outputs the Ack signal on the signal line 213 and is in a data waiting state on the bus 211 at the same time, the data sent from the DMA 202 on the bus 211 is stored in the internal buffer.

When data also exists in the internal buffer of this DMA 203, BRQ is applied to the signal line 218.
Send a (bus request) signal.

Then, the bus controller 205 determines that D
The BRQ signal from the MA 203 is set as an arbitration target, and the DMA2
When the bus use right is set to 03, a BAK (bus use permission) signal is output on the signal line 219. DMA203
Upon receiving this BAK signal, a write command signal is output on the signal line 220. As a result, the memory controller 206 sets the signal line 223 on the write mode. And D
The MA 203 outputs an address signal on the signal line 221, a data signal on the signal line 222, and the memory 207.
Write data to.

The processing proceeds in this way, and the DMA 20
2. The DMA 203 finishes the processing relating to the transfer processing in this order, but since the interrupt permission display bit in the mode register of the DMA 202, 203 is set to "0", it ends on the signal lines 224, 225. No notification signal is issued.

Since the command queue display bit of the DMAs 202 and 203 is set to "1", each control register is shifted at the end of the processing. As a result, the DMA 202 processes and the DMA 203
Is in processing mode.

Then, the DMA 202 has the I / O port 20
It is in a state of waiting for the DReq signal indicating the data transaction request from 1. The DMA 204 is already the DMA 20 as described above.
It is in the state of waiting for the Req signal from 2. Also, I
The / O port 229 outputs a DReq signal indicating a data request onto the signal line 231, and is in a state of waiting for a DAck signal on the signal line 232.

On the other hand, the DMA 203 is in the processing mode and sends a BRQ (bus request) signal to the signal line 218. Then, the bus controller 205
When the bus right is set in A203, the signal line 219
Issue a BAK (Bus Permission) signal on top. DMA203
Receives the BAK signal and outputs a read command signal on the signal line 220. As a result, the memory controller 20
6 sets the read mode on the signal line 223. Then, the DMA 203 outputs an address signal on the signal line 221, and stores the data signal on the signal line 222 in the internal buffer. When data is present in the internal buffer in this manner, the DMA 203 causes the Req on the signal line 214 to cause the DMA 202 to receive the data in the internal buffer.
Give a signal. However, since the DMA 202 is in the processing mode, the signal line 215 is transmitted from this DMA 202.
Since the Ack signal is not output above and the condition is not satisfied, DMA2
When the internal buffer of 03 is full, this DM
The A203 interrupts the read from the memory 207 and waits for the Ack signal from the DMA202 in that state.

Regarding the processing, when the DReq signal appears on the signal line 209, DMA is transmitted in response to the signal.
202 confirms that the internal buffer is empty, and then issues a DAck signal to the signal line 210, and then the I / O port 2
The data sent from 01 is received via the bus 208 and written in the internal buffer.

When data is present in the internal buffer due to this writing, the DMA 202 causes the signal line 217 to cause the DMA 204 to receive the data in the internal buffer.
Issue a Req signal on top.

In response to this, the DMA 204 confirms that the internal buffer is empty, and then outputs the Ack signal to the signal line 217. Then, the DMA 202 causes the signal line 2
The Req signal on 17 is cleared and the data in the internal buffer is sent out on the bus 211. Since the DMA 204 outputs the Ack signal on the signal line 217 and is in a state of waiting for data on the bus 211 at the same time, the bus 211
The data sent out from the DMA 202 is stored in the internal buffer.

When data also exists in the internal buffer of this DMA 204, DAc is placed on the signal line 232.
After outputting the k signal, the data in the internal buffer is transmitted on the signal line 230.

The I / O port 229 clears the DReq signal in response to the DAck signal from the DMA 204 to enter the data reception standby state, and then takes in the data sent on the signal line 230.

The processing proceeds in this way, and the DMA 20
2. The DMA 204 finishes the processing relating to the transfer processing in this order. However, since the interrupt permission display bit in the mode register of the DMA 202, 204 is set to "0", the processing ends on the signal lines 224, 226. No notification signal is issued.

Further, the DMA 202 shifts the control register to enter the processing mode.

As a result, in response to the Req signal already output from the DMA 203, the DMA 202 confirms that the internal buffer is empty, and then outputs the Ack signal on the signal line 215. Then, the DMA 203 causes the Req on the signal line 214 to
The signal is cleared and the data in the internal buffer is sent to the bus 211. Since the DMA 202 outputs the Ack signal on the signal line 215 and is in a data waiting state on the bus 211 at the same time, the D sent on the bus 211 is transmitted.
The data from MA 203 is stored in the internal buffer. As a result, an empty space is created in the internal buffer of the DMA 203, and data reading from the memory 207 is restarted.

When data is present in the internal buffer of the DMA 202, DAck is applied to the signal line 210.
Signal and then the data in the internal buffer to the bus 208
Send it up.

The I / O port 201 is D on the signal line 210.
The DReq signal is cleared by the Ack signal, and the bus 208
Capture the above data.

The processing proceeds in this way, and the DMA 20
3. The DMA 202 finishes the processing relating to the transfer processing in this order. However, since the interrupt permission display bit in the mode register of the DMA 203 is set to “0”, the termination notification signal is output on the signal line 225. Absent. But,
After that, since the interrupt permission display bit “1” is set in the mode register of the DMA 202 where the processing ends, the end notification signal is output to the signal line 224 at the same time as the processing ends. Thereby, the CPU can confirm the end of all the processes of.

[0099]

As described above, according to the present invention, it is possible to set permission / prohibition for the generation of the end notification in the transfer mode storage means, and the end notification generation means sends the end notification according to the presence or absence of the setting. Since the same effect as the mask of occurrence is obtained, such setting can be performed at the same time as the command setting, and the command chain can be operated.

Particularly, if the command chain execution instruction is set in the control register, the debugging can be performed more easily than when the command chain execution instruction is set in another register. It also makes programming easier.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data transfer system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration when a system having a plurality of data transfer paths is assembled according to a conventional idea.

[Explanation of symbols]

 201, 229 I / O ports 202-204 DMA 205 bus controller 206 memory controller 207 memory 233 control register 234 transfer processing execution unit 235 end notification generation unit 236 queue control unit

Claims (2)

[Claims] 1. A data transfer device constituting a DMA arranged for each port of a plurality of data transfer paths, comprising: a transfer mode storage unit for setting a transfer mode including a transfer mode and an interrupt permission; and the transfer mode. A transfer processing executing means for executing the data transfer processing in the transfer mode indicated by the storing means, and a CPU when the processing of the transfer processing executing means is completed and the interrupt permission is set in the interrupt permission storing means. And a termination notification generating means for generating a termination notification for the data transfer apparatus. 2. The data transfer apparatus according to claim 1, further comprising a control register in which a plurality of transfer mode storage means are formed in a queue structure and an instruction to execute the command chain can be set.