JPS61214049A - Bus control system - Google Patents

Abstract

PURPOSE:To improve the using efficiency of a local bus by securing the control where an input/output processor gives up the using right of an adaptor bus when it acquires this using right and then acquires again said right when it receives the read data from a main memory. CONSTITUTION:A system bus 50 is used for connection among a main memory 10, a central processor 20 and an input/output processor 30. While a local bus 60 connects the processor 30 to adaptors 41-4N. These adaptors 41-4N acquire the using right of the bus 60 when an access is given to the memory 10 and then give up this right after informing the adaptor recognition information to the processor 30. While the processor 30 gives an access to the memory 10 by means of the access information after acquiring the using right of the bus 50 and conforms the acquisition of the answer information of the memory 10. At the same time, the controller 30 sends the adaptor recognition information and the answer information onto the bus 60 after acquiring the using right of the bus 60. Thus the fine control is given to the exclusive time of the bus 60 and the using efficiency of the bus 60 is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus control system, particularly to a main memory device (hereinafter referred to as MMU).
), a central processing unit (hereinafter referred to as CI"U), and an input/output processing unit (hereinafter referred to as IOP), and a second bus that connects the IOP and an adapter (hereinafter referred to as ADP). The present invention relates to a bus control method in an information processing apparatus equipped with an ADP. ADP refers to hardware for interfacing a second bus with an input/output device such as a magnetic disk device or a magnetic tape device 2 communication network.

(Prior Art) In this type of conventional bus control system, Ai) When accessing MMtJ from P9tll, for example, for a memory read operation, first, the right to use the local bus is acquired, and then the second bus In order to issue an MMLI read instruction above, an MMU read instruction command and MMU address are sent onto the local bus.

The IOP receives all the MMU read instruction commands via the local bus, acquires the right to use the system bus, and then sends the MMU read instruction command and MM[J read address on the system bus, and reads the MMU from the MMU. Wait for data response.

When the MMU fully opens the system bus and receives a data response,
The IOP once takes this data into its internal register and relinquishes the right to use the system bus.

Subsequently, the IOP sends the MMU read data taken into the internal register to the local bus. When the ADP receives the MMU read data sent onto the local bus, it relinquishes all rights to use the local bus.

(Problems to be solved by the invention) In such a conventional system, as shown in Fig. 3,
Timing t from ADP to MM[J. When a read request is made in , the local bus becomes exclusive to one specific ADP at timing t5-1 when the read data from the MMU arrives on the local bus and is sent to the ADP, and other ADPs are not connected to the local bus. This is a problem in terms of system efficiency. especially.

If the system bus is so crowded that it is difficult to obtain the right to use it, the efficiency of using the local bus will deteriorate accordingly.

Therefore, an object of the present invention is to provide a bus control method that improves the efficiency of local bus use.

(Means for Solving the Problems) The system of the present invention is a bus control system for an information processing device that includes a first bus that connects an MMU, a CPU, and an IOP, and a second bus that connects an IOP and an ADP. , ADP acquires the right to use the second bus when accessing MM[J, and after notifying the IOP of the access information and adapter recognition information, completely relinquishes the right to use the second bus, and
When P acquires the right to use the first bus, it uses the access information to fully access the MMEJ and recognizes that it has obtained the response information from the MMU.When it acquires the right to use the second bus, it accesses the adapter recognition information and response information from the second bus. It is characterized in that it is sent out on two buses.

(Operation) In the present invention, direct coupling between the second bus and the first bus is eliminated, and when the ADP acquires the right to use the second bus, it temporarily relinquishes the right to use the second bus, and the IOP MM
When the read data from U is received, the IOP becomes the second
The efficiency of using the second bus is improved by performing control such that the right to use the bus is completely lost and then acquired.

(Embodiment) FIG. 1 is a time chart showing the operation of an embodiment of the present invention, and FIG. 2 is a hardware configuration diagram common to this embodiment and the conventional example described above. Referring to FIG. 2, this hardware is.

MMUlo, CPU20. l0P30. N ADP4
1 to 4N, a system bus 50, and a local bus 60. System bus 50 is M
Connects MUI O, CPU20 and l0P30, and local bus 60 connects l0P30 and ADP41 to
4Nf, connected. Each usage right for the system bus 50 and local bus 60 is as follows.

Permission or disapproval is determined according to each request by a device (not shown).

Next, the operation of this embodiment will be explained with reference to FIG.

In order for ADP4X (X=1 to N) to read access to MMUlo, it is first necessary to acquire the right to use the local bus 60, but a detailed explanation thereof will be omitted, and it is assumed that the right to use has been acquired at timing t.

It is assumed that the MMU read instruction command is sent to the local bus 60 at timing t1, and then the MMU read address and the recognition information of the ADP4X are sent to the local bus 60 at timing t1.

The l0P30 holds the recognition information from the ADP4X, makes the necessary request to acquire the right to use the system bus 50, and when it is acquired, transmits the MMU read instruction command and the MMU read address to the system bus 5 at timing t2.
0 and waits for a data response from MMUIO.

It should be noted that at timing t2, the ADP4X relinquishes the right to use the local bus 6o and uses the other adapter 4Y (Y
=1~N.

However, Y〆X) is to make the local bus 60 usable.

l0P30 starts at timing t2, MMU 10 O read - 6 = output data is sent to the system bus 50, and l0P30
The system bus 50 is dedicated to the system bus 50 at timing t31 when it is input, and is released at timing t3. Then I
The OP makes a request to acquire the local bus 60, and when this request is accepted, it sends the MMU read data and the held recognition information of the adapter 4X onto the local bus 60 at timing t4. And M.M.U.
When the read data is received by the adapter 4X, the right to use the local bus 60 is relinquished and released at timing t.

Therefore, as shown by diagonal lines in FIG. 1, the local bus 60 is connected at timing t. to t2 and from timing t4 to t5 are dedicated to the adapter 4X, and from timing t2 to t4-1 is released. As a result, conventionally the timing t is as shown in FIG.
. It can be seen that the entire time dedicated to the local bus 60 can be significantly shortened, whereas the time from t to t was dedicated to the adapter 4X.

(Effects of the Invention) According to the present invention, as described above, by finely controlling the dedicated time of the local bus, it is possible to improve the usage efficiency of the local bus.

[Brief explanation of the drawing]

FIG. 1 is a time chart for explaining one embodiment of the present invention, FIG. 3 is a time chart for explaining a conventional example, and FIG. 2 is a hardware configuration diagram common to this embodiment and the conventional example. are shown respectively. 10... Main memory unit (MMU), 20...
...Central processing unit (CPU), 30...Input/output processing bag [(IOP), 41.42...4N...
・Adapter (ADP, ). 50...System bus, 60...Local bus.

Claims (1)

[Scope of Claims] A bus control method in an information processing device that includes a first bus that connects a main storage device, a central processing unit, and an input/output processing unit, and a second bus that connects the input/output processing unit and an adapter. wherein, when the adapter acquires the right to use the second bus when accessing the main storage device, the adapter notifies the input/output processing device of access information and adapter recognition information, and then relinquishes the right to use the second bus; When the input/output processing device acquires the right to use the first bus, it accesses the main storage device using the access information, recognizes that it has obtained response information from the main storage device, and acquires the right to use the second bus. A bus control system characterized in that when the adapter recognition information and the response information are acquired, the adapter recognition information and the response information are sent onto the second bus.