JPH04163657A - Data transfer control system - Google Patents

Abstract

PURPOSE:To realize the effective operation of a main storage device and the improvement of the transferring efficiency of a bus by accessing continuously the main storage device for plural independent addresses and commands. CONSTITUTION:An information processor 1 is constituted of a main storage bus 13, plural processors 2 connected to the main storage bus 13, and the main storage device 5. Here, the same or another bus master is made capable of issuing the independent addresses and commands during a period of time after the bus master issues the address or the command until data is transferred from the main storage device 5, and in this case, the main storage device 5 is made to execute continuously the access of the data for plural independent addresses and commands. Thus, the main storage device 5 can be made to operate effectively, and in addition, the transferring efficiency of the bus can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a main memory device that can be used on a main memory bus when a main memory device and a plurality of processing devices that access the main memory device are connected via the main memory bus. The present invention relates to a data transfer control method for controlling data transfer.

[Conventional technology]

Conventionally, as a data transfer control method for controlling data transfer on the main memory bus, one bus master transfers addresses and commands.

After the data transfer for the address and command is completed, the same or another bus master transfers the address and command.

[Problem to be solved by the invention]

However, in the conventional data transfer control method described above, while the main storage device is accessing data,
Devices other than the bus master connected to the main memory bus are
Even if there is a data transfer request, it is not possible to issue an address or command, and the address and command are issued after the main memory has finished accessing the data and outputted the data, so access to the main memory The disadvantage was that it was delayed. □ The present invention improves these conventional drawbacks, and its purpose is to prevent delays in accessing the main memory, operate the main memory effectively, and improve bus transfer efficiency. The object of the present invention is to provide a data transfer control method that allows

[Means to solve the problem]

The present invention provides a main memory bus data transfer control method in which a main memory device and a plurality of processing devices accessing the main memory device are connected, in which one of the plurality of processing devices uses the main memory bus. After gaining the right to become the first bus master,
After issuing a first address and command requesting the transfer of data in the main memory device to the bus, and until the main memory device outputs the data to the main memory bus, another processing device When the second bus master obtains the right to use the second bus master, the second bus master is configured to be able to issue the second address and command even during the above period,
When a second address and command are issued during the above period, the main storage device immediately starts accessing data to the second address and command after completing data access to the first address and command. It is designed to do this.

[Effect]

After the first bus master issues a first address and command requesting the transfer of data of the unique device.

During the period until the main memory outputs data to the main memory bus, the second bus master that has obtained the right to use the bus can issue the second address and command even during the above period. In this case, the main storage device accesses data to the second address and command immediately after completing the data access to the first address and command. This allows the main memory to be accessed continuously for two independent addresses and commands, allowing the main memory to operate effectively.

Bus transfer efficiency can be improved.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

This embodiment includes a main memory bus 13, a plurality of processing devices 2 connected to the main memory bus 13, and a main memory device 5. More specifically, the main memory bus 13 includes a control bus 11 and an ACD bus 12, and each processing device 2
is provided with a bus monitoring section 3 connected to the control bus 11 to monitor the bus status and control the device, and a data processing section 4 that issues addresses and commands, inputs data, and processes data. The main storage device 5 includes a bus monitoring section 6, an address command holding section 7 that can hold addresses and commands for two transfers, and a memory section 1.
0, a data holding unit 8 that temporarily holds data from the ACD bus 12 and data from the storage unit 10, and a storage unit 1.
0 is provided.

Next, regarding the data transfer control processing operation on the main memory bus 13 in such a configuration, FIGS. 2(&) to (d)
, will be explained using the time charts of FIGS. 3(a) to 3(d).

In Figure 2 (1) to (d) and Figure 3 (a) to Mouse),
Signals CLK, CMD, RDY, ACD are shown. Here, the signal CLK is a clock signal,
In this embodiment, the main memory bus 13vi operates in synchronization with this clock signal CLK. The signal CMD is used by one bus master to send addresses and commands to the ACD bus 12.
The signal RDY is a signal on the control bus 11 indicating that data to be read from the main memory device 5 is ready.

Further, the signal ACD is a signal indicating the state of the ACD bus 12. Note that the signals CMD and RDY are the clock signal CL.
It is output in synchronization with K and is active when it is LOW.

Further, in the signal ACD, the period C indicates that the address and command are fixed on the ACD bus 12, and the R
During the period D, the data read from the main memory 5 is AC
C and RD
If n is the same, the address and n
n commands and data correspond to each other.

First, referring to the time charts in FIGS. 2(al) to (d), the bus monitoring unit 3 of the first bus master is in state A.
When the data processing unit 4 issues the signal CMD at the timing of state A and the data processing unit 4 issues CA to the ACD bus 12, the bus monitoring unit 6 of the main storage device 5 issues the signal CMD at the timing of state A.
I confirm that the MD was issued and withdraw it.

The CA is held in the address command holding unit 7. Next, if the storage control unit 9 is not accessing the storage unit 10, the bus monitoring unit 6 transfers the command from the address command holding unit 7 to the storage control unit 9, and also transfers the address to the storage unit 10, and then transfers the command to the storage control unit 9. 9 accesses the storage unit 10 for the sent command.

If the second bus master has obtained the right to use the bus during the period of stay 1-B from when the first bus master issues the CA until the main memory 5 outputs data, this second
In the bus master, the bus monitoring unit 3 issues a signal CMD to the control bus 11, and the data processing unit 4 issues CB to the ACD and bus 12. The bus monitoring unit 6 of the main storage device 5 is
When the signal CHD is issued at the timing of state B, MR causes c3 to be held in the address command holding section 7. The head section 10 outputs the data for CA to the data holding section 8, and the data holding section 8 outputs it to the ACD bus 12 as RDA. After that, the control unit 9 stores the memory unit 1.
The bus monitoring unit 6 is notified that the access to 0 has ended, and the bus monitoring unit 6 outputs the signal RDY to the control bus 11 at the timing of state C. By receiving this signal RDY, the first bus mask recognizes that the data RDA has been determined and stores the RDA in the data processing section 4.

In the main storage device 5, when the storage control unit 9 notifies the bus monitoring unit 6 that the access to the storage unit 1o for the CA has ended, the address and command are held in the address command holding unit 7.

Start the next access. That is, when the bus monitoring section 6 transfers the CB command held in the address command holding section 7 to the storage control section 9 and transfers the address to the storage section 10, the storage control section 91'i.

Note: Access Kurabe 10, and access C from storage unit 10.
When data for B is output, the same operation as in RDAO is performed.

In addition, the time charts in FIGS. 3(a) to (d) show the address and command C c * CD + Cg
* This is a time chart when CF is issued continuously and the main memory bus 5 is in the most crowded state, and the RDc t RDD I RD for that address and command
This shows the case where only g + RDy is output.

〔Effect of the invention〕

As explained above, the present invention enables the same bus master or another bus master to issue independent addresses and commands after the bus master issues addresses and commands until the data is transferred from the device. In this case, the main memory is designed to access data continuously for multiple independent addresses and commands, so the main memory cannot operate effectively. , and has the effect of improving bus transfer efficiency.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2(a)
3(a) to 3(d) are time charts for explaining the data transfer control operation in the present invention. In FIG. 1, 1... information processing device, 2... processing device, 3... bus monitoring section, 4... data processing section, 5... main storage device, 6... bus monitoring 7...Address command holding unit, s...Data holding unit, 9...Storage control unit, 10
...Storage unit, 11...Control bus, 12...ACD
Bus, 13...main memory bus. Agent Patent Attorney Johei Yamashita

Claims (1)

[Claims] In a main memory bus data transfer control method in which a main memory device and a plurality of processing devices that access the main memory device are connected, one of the plurality of processing devices obtains the right to use the main memory bus. During the period after becoming the first bus master and issuing a first address and command requesting the transfer of data from the main memory device to the bus, until the main memory device outputs data to the main memory bus, When another processing device obtains the right to use the bus and becomes the second bus master, the second bus master is configured to be able to issue the second address and command even during the above period, and When the second address and command are issued, the main storage device accesses the data to the second address and command immediately after the data access to the first address and command is completed. A data transfer control method characterized by: