JPS5619572A - Buffer memory control system - Google Patents

Buffer memory control system

Info

Publication number
JPS5619572A
JPS5619572A JP9339779A JP9339779A JPS5619572A JP S5619572 A JPS5619572 A JP S5619572A JP 9339779 A JP9339779 A JP 9339779A JP 9339779 A JP9339779 A JP 9339779A JP S5619572 A JPS5619572 A JP S5619572A
Authority
JP
Japan
Prior art keywords
byte
buffer memory
odd number
frequency
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9339779A
Other languages
Japanese (ja)
Other versions
JPS5837633B2 (en
Inventor
Hirosada Tone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54093397A priority Critical patent/JPS5837633B2/en
Publication of JPS5619572A publication Critical patent/JPS5619572A/en
Publication of JPS5837633B2 publication Critical patent/JPS5837633B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the frequency that the buffer memory is in busy state, by the transfer processing of the block data of a given byte number via a plurality of buffer registers having a given byte width. CONSTITUTION:When the data having the size of one block MXL as 8X8 bytes are processed via the bus 8-byte in width L between the bus and the main memory unit MCU, the data of an even and odd number byte are simultaneously stored in the even and odd number byte buffer memories 1-0, 1-1 via a plurality of even number information, odd number information registers 2-0, 2-1 and even number byte and odd number byte write-in registers 3-0, 3-1. Accordingly, in comparison with the usage of one set of information register and write-in register in 8-byte, the frequency that the buffer memory is busy is reduced, allowing to reduce the frequency of the increase of the block unit and of the buffer memory-not-found without increasing the busy state.
JP54093397A 1979-07-23 1979-07-23 Buffer memory storage control method Expired JPS5837633B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54093397A JPS5837633B2 (en) 1979-07-23 1979-07-23 Buffer memory storage control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54093397A JPS5837633B2 (en) 1979-07-23 1979-07-23 Buffer memory storage control method

Publications (2)

Publication Number Publication Date
JPS5619572A true JPS5619572A (en) 1981-02-24
JPS5837633B2 JPS5837633B2 (en) 1983-08-17

Family

ID=14081160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54093397A Expired JPS5837633B2 (en) 1979-07-23 1979-07-23 Buffer memory storage control method

Country Status (1)

Country Link
JP (1) JPS5837633B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5930289A (en) * 1982-08-06 1984-02-17 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Hierarchical memory system
JPS5956118A (en) * 1982-09-25 1984-03-31 Shinko Electric Co Ltd Controlling method of automatic weighing supply device
JPS60136874A (en) * 1983-12-26 1985-07-20 Hitachi Ltd Vector processor
JPS6121543A (en) * 1984-07-10 1986-01-30 Matsushita Electric Ind Co Ltd Data transfer device
JPS61224051A (en) * 1985-03-29 1986-10-04 Fujitsu Ltd Buffer memory control system
US8312218B2 (en) 2006-02-27 2012-11-13 Fujitsu Limited Cache controller and cache control method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6128228U (en) * 1984-07-25 1986-02-20 日本航空電子工業株式会社 polyhedral key switch

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5930289A (en) * 1982-08-06 1984-02-17 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Hierarchical memory system
JPS5956118A (en) * 1982-09-25 1984-03-31 Shinko Electric Co Ltd Controlling method of automatic weighing supply device
JPH059727B2 (en) * 1982-09-25 1993-02-05 Shinko Electric Co Ltd
JPS60136874A (en) * 1983-12-26 1985-07-20 Hitachi Ltd Vector processor
JPH0414384B2 (en) * 1983-12-26 1992-03-12 Hitachi Ltd
JPS6121543A (en) * 1984-07-10 1986-01-30 Matsushita Electric Ind Co Ltd Data transfer device
JPS61224051A (en) * 1985-03-29 1986-10-04 Fujitsu Ltd Buffer memory control system
JPH0510694B2 (en) * 1985-03-29 1993-02-10 Fujitsu Ltd
US8312218B2 (en) 2006-02-27 2012-11-13 Fujitsu Limited Cache controller and cache control method

Also Published As

Publication number Publication date
JPS5837633B2 (en) 1983-08-17

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