JPS63288351A - Write/read-out circuit for memory block - Google Patents

Abstract

PURPOSE:To execute read and write of a data by continuing freely the sequence of a block, by using a block select memory and its control circuit, and first of all, setting the address information and the block selecting information. CONSTITUTION:In case of writing and reading out a data to and from a pattern data memory 53, a write/read-out start address data is set to a pattern address counter 56. In order to loop an address of a block select memory 67, a loop end address is set to a loop end register 69. A loop end address data is given on a signal of a BUS1...BUSn and set. Subsequently, block selecting information is written periodically and successively.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a memory block writing/reading circuit, and in particular to a pattern/reading circuit in a semiconductor testing device.
It is used in data memory write and read circuits.

(Prior Art) A writing/reading circuit for a pattern data memory in a semiconductor trial sales apparatus generally has a logic circuit configuration as shown in FIG. In FIG. 6, 51 is a bidirectional bus driver, 52 is an AND circuit, 53 is a pattern data memory, and 57 is a delay element. Here the CPU (
Bus line BLIS1...BUSn of central processing unit H)
The signal consists of a plurality of bits and becomes data to be written or read from the pattern data memory 53. Also, B
USI...BLISn signals are transmitted to blocks 31, 32, . . . of pattern data memory. . . 3n address information and bidirectional bus driver circuit 11.12. . . . It also serves as block selection information for 1n. Bidirectional bus driver circuit 11.12. . . . 1n selection information is loaded to the block selection counter 55, and address information of the pattern data memory 53 is loaded to the pattern address counter 56, each with a 5ETGK signal. The output of the block selection counter 55 becomes the input signal of the block selection circuit 54,
Bidirectional bus driver selection signals 81, 82 . ...3n is selected. Signal S1.82. . . 3n selects the bidirectional bus driver 51 and becomes an input to the AND circuit 52 at the same time.

Sl is the input signal of AND circuit 21, S2 is AND circuit 2
Similarly, the input signals 83...5n become the input signals of the AND circuits 23...2n. This AN
In the D circuits 21...2n, the logical product of the WM double signal CUP signal and the Sl...Sn signal is taken, and the write enable signal (WE) of the pattern data memory 53 to be written is obtained. Become.

In the circuit shown in FIG. 6, if the WM double signal is "1" (yes), the mode is set to write one data into the pattern data memory 53, and if it is "O" (no), data is written from the pattern data memory 53. The mode is set to read. In the write mode, as shown in FIG. 7, the time a cycle for providing write address information and block selection information and the time b cycle for providing write data are processed in a time-division manner. Similarly, in the case of read mode, the time a for providing read address information and block selection information is shown in FIG.
The cycle and the b cycle for obtaining read data are processed in a time-sharing manner. In either case, address information and block selection information must be given at the same time in a cycle, that is, in the same cycle, so bus line B,
LIS1...BUSn will be divided and processed.

For example, pattern data memory 31. ...3n is 4
If the memory is 096 words x 16 bits, BUS1
・-BUSl2 becomes the address information, and BLIS13・
...BLJS16 becomes block selection information. Therefore,
In this case, 16 blocks of pattern data memory can be handled.

Here, when writing data continuously to the pattern data memory 53, or when writing data to the pattern data memory 53,
When reading data continuously from 3, as shown in Figure 9,
First, the address value to be read and written and the block selection value 0 are given in a cycle, and from the next b1 cycle, b2. Data is read or written as b3.... The block selection counter 55 is b
The pattern data memory 53 is counted up by one count every cycle, and the pattern data memory 53 is counted up by one count. ...3n
are selected one after another. Block selection counter 55 is n
-1, the block selection counter outputs a carry signal, counts up the pattern address counter 56, and advances the address of the pattern data memory 53. At this time, the block selection counter is low 1.
The process returns to O, and is counted up again from the beginning to n-1, and the pattern address counter 56 is incremented by 1. Thereafter, reading or writing is performed in the same manner.

(Problems to be Solved by the Invention) Next, when reading data continuously from a certain memory block of the pattern data working memory 53, when reading data into a memory block, or when reading data from a discontinuous memory block, When reading or writing data to or from a block (of the memory 53), address information and block selection information must be provided each time as shown in FIG. Therefore, this example has the following drawbacks.

(1) Writing data to and reading data from discontinuous pattern data memory blocks always requires both address information and block selection information.
It is impossible to write or read only data.

(2) Writing and reading data to and from discontinuous pattern data memory blocks requires address information and selection information for each piece of data, which increases writing and reading time.

The present invention has been made in view of the above circumstances, and when storing data into a pattern data memory in a semiconductor testing device or the like, or when reading data, address information and block selection information are first set. Due to circumstances, from now on,
The object of this invention is to enable continuous writing to or reading from any pattern data memory block without address information and block selection information, thereby improving the above-mentioned conventional problems.

(Means and effects for improving the problem) The present invention provides a pattern data memory that stores information for each block;
a bidirectional bus driver provided between a bus line of a CPLJ (central processing unit) and the pattern data memory; a block selection circuit for selecting a block of the pattern data memory; and a block from the CPU. a block select memory that sequentially stores selection information and selects the output of the block selection circuit according to the information;
A write or read address setting means for the pattern data memory, a register for recording a set value by the CPU, a block select counter whose count value changes every time a write or read cycle changes, and a block select counter for this counter. Compare the output with the output of the register, and select the block select according to the result.
an address comparator for resetting a counter and changing the address value of the address setting means; and a multiplexer for switching between the output of the block select counter and block selection information from the CPU to the block select memory. This is a memory block write/read circuit. That is, the present invention uses a block select memory and its control circuit in a circuit that controls data writing or reading from a memory block, and by first setting address information and block selection information, You can write or read only data without CPU intervention for each data, without address information and block selection information.
This allows the blocks to be executed in any order in succession.

(Example) An example of the present invention will be described below with reference to the drawings. 1st
This figure is a block diagram of the same embodiment, but since this is an example in which it corresponds to that of FIG. 6, the same reference numerals are used for corresponding parts. In FIG. 1, reference numeral 51 denotes bidirectional bus driver circuits 11, 12, . ...1n is a bidirectional bus driver.

This bidirectional bus driver 51 has pattern data,
Memory 53 and bus line signals BUS1...BUSn
When the DIR signal is ``1'', the direction is the write direction, and when the DIR signal is ``O'' (no), the direction is the read direction.

52 AND circuits 21.22. - 2n is a circuit for obtaining a write permission signal WE necessary for writing data into the pattern data memory 53, and a circuit for obtaining a block selection signal 31. S2. . . . It is output when the three logical products of Sn and the WM multiplied signal CLIP signal are established. WM double signal This signal determines whether to write or read data into the pattern data memory 53, and is "1" when writing and "'0" when reading.

Pattern data memory 53 is memory block 31
．． 32. ...3n, and this block 31.32.
. . 3n is a memory in which functional test patterns necessary for semiconductor testing are stored.

The block select memory 67 is a pattern data memory 31, 32, 3n for reading or writing.
and bus line BUS1. BUS2゜・・・BLISn
Bidirectional bus drivers 11.12. . . 1n and stores information for outputting a write permission signal WE to the selected pattern data memory. This block select memory 67 is connected to the bus line 5usi...BUS
Block selection information is taken in and stored in order from the n side, but this is only the first time information is stored; subsequent block selection information
The operation of the select memory 67 is left to the block select counter 68. The block selection circuit 54 decodes the output data signal O from the block select memory 67 and outputs the output signal S1. S2.

...Outputs one signal among Sn. This signal 81
．． 82. . . . The bidirectional bus driver 51, pattern data memory 53, and AND circuit 52 are selected by Sn.

The pattern address counter 56 is an address counter that sets write and read addresses of the pattern data memory 53. The first address setting is to set the data on bus lines BUS1...BLISn to 5E.
The address counter 56 is loaded by the TCK1 signal. Thereafter, the count is increased by the INCP signal applied to the UP input terminal of the pattern address counter 56.

Block select counter 68 is an address counter that sets the address of block select memory 67. Block select counter 68 R8T
The input terminal is cleared by the TR signal before starting data read/write transfer to the pattern data memory 53. Also, the block select counter 68 is cleared by the TR signal before writing the block select data to the block select memory 67.

Loop end register 69 is the block select register.
This register specifies the loop end address of memory 67. Data is set to the loop end register 69 by setting the address data on bus lines BUSI...BLISn by the 5ETCK2 signal.

Address comparator 70 is a digital comparator that detects whether the loop end address set in loop end register 69 and the contents of block select counter 68 match. The block select counter 68 is counted up from 0,
1 until it matches the contents of loop end register 69
, 2°... and C delayed by the delay line 66.
It is counted up by the PU signal. If the contents of both A and 8 match, the address comparator 70
A coincidence signal C0IN is output from the A-8 terminal of the .

The AND circuit 72 is a circuit that performs the logical product of the C0IN signal and the CUP signal in order to obtain a clear signal for the block select counter 68. The output signal of this AND circuit 72 is delayed by a delay line 73, and then passes through an OR circuit 74 to R8T of the block select counter 68.
terminal and the block select counter 68 is cleared. Multiplexer 71 is a circuit that selects address data of block select memory 67. The address selected by this multiplexer 71
The data includes data provided by the bus lines BUS1...BUSn and data provided from the output Q of the block select counter 68, and is selected by the BS signal. In other words, when the BS signal is "1", the address data of bus lines BLIS1...BUSn is "0".
'' (none), the address data output from the block select counter 68 is selected.

Next, the operation of FIG. M1 will be explained with reference to the time charts of FIGS. 2 to 5. First, when writing data to the pattern data memory 53 in FIG. 1 or reading data from the pattern data memory 53,
As shown in Fig. 2, a-cycle BLJSl...BLI
The write/read start address data given by the Sn signal is set in the pattern address counter 56 by the 5ETCK1 signal. Next, block select
A loop end address necessary for looping the addresses of the memory 67 from address O to address X is set in the loop end register 69. This loop end address data is given on the BLISI...BLISn signals of cycle b shown in FIG.
It is set in the loop end register 69 by the TCK2 signal. Next C1 cycle, C2 cycle...
- Then, the block selection information given on the signals of BIJSl...BUSn is sequentially written in C1 cycle, C2 cycle, and so on. For example, as shown in Figure 3, a
An address "0" at which writing or reading from the pattern data memory 53 is to be started is written in the pattern address counter 56 in a cycle. Next, in cycle b, data "2" for using the block select counter 68 as a ternary counter is written in the loop end register 69. This "2" is fixed once written. Also, block select in C1 cycle
The pattern data memory 53 to which you want to read or write old data for the first time to the address ゛O'° of the memory 67
Block selection information of the pattern data memory 53, for example, "5" is loaded into the IQ, and block selection information of the pattern data memory 53 to be written or read for the second time to address "1" of the block select memory 67 in the C2 cycle, for example, "'3' is written and address 112 of block select memory 67 is written in C3 cycle. The block selection information of the pattern data memory 53 to which writing or reading is to be performed for the third time, for example, ``1'' is written into l. In the circuit shown in FIG. 1, if the WM other signal is "1" (true), the mode is set to write data to the pattern data memory 53, and if it is O" (none), the mode is set to read data from the pattern data memory 53. Become.

In the case of the recess mode, as shown in FIG. 4, the TR signal becomes "O" (None), the reset of the block select counter 68 is released, and the BS signal becomes "0" (None).
The multiplexer 71 selects the output signal Q (initial value IIO'') of the block select counter 68, which becomes the address input of the block select memory 67.

In the first 01 cycle, the address of the block select memory 67 is “0” and the output O is block “5”.
That is, the block selection circuit 54 selects S5 (not shown), the bidirectional bus driver 15 (not shown) is selected, and the
The ND circuit 25 (not shown) outputs the S5 signal, WM and other signals C
The logical product of the three LIPffi numbers is taken, and it becomes a write permission signal, which is sent to address "0" of 35 (not shown) of the pattern data memory 53 on bus lines BUS1...8.
LISn data is written. After the writing of the pattern data memory 35 is completed, the CUP signal passes through the delay element 66 and becomes a count up signal for the block select counter 68, and its output signal Q is incremented by +1 and the address of the block select memory 67 is This will indicate “1”.

In the second 02 cycle, the address of the block select memory 67 is "1" and the output O is block "3".
That is, the block selection circuit 54 selects S3, the bidirectional bus driver 13 (not shown) is selected, and the AND circuit 2
3 (not shown), 83 signal, WM other signal CUP signal 3
A logical product is taken, and a write enable signal WE is obtained, which is the address of the pattern data memory 33 (not shown).
The data of BUSl...BUSn is written to 0''.

After the writing of the pattern data memory 33 (not shown) is completed, the 0LIP signal passes through the delay element 66.
This becomes a count up signal for the block select counter 68, and its output signal Q is incremented by 1 to indicate the address "2" of the block select memory 67.

In the third 03 cycle, the address of the block select memory 67 is "2" and the output O is block "1".
That is, the block selection circuit 54 selects S1, the bidirectional bus driver 11 is selected, and the AND circuit 21 selects S1.
The three logical ANDs of the signal, WM and other signals CUP signal are taken,
The pattern data memory 31 becomes a snobbery permission signal.
BU S 1-B LI S to the address ゛'O°゛
n data is written. At this time, the output signal Q of the loop end register 69 is set to "2" in advance, and in the C3 cycle, the block select
Since the counter 68 also becomes "2", the input terminals A and 8 of the address comparator 70 match, and -rescue force A-8
becomes “1” (ant). The AND circuit 72 selects the address
Theory 8 between the coincidence output A-B of the comparator 7o and the CUP signal! The product is calculated, and its output signal passes through the delay element 73 and becomes a count up signal for the pattern address counter 56, so that the pattern address counter 56 is incremented by one.

Also, it passes through the OR circuit 74, and the block select
This becomes the reset signal for the counter 68, and the output signal Q becomes °'
0', and the address of the block select memory 68 returns to its initial value "0". Thereafter, writing is performed in the same manner.

In the case of the read mode, as shown in FIG. 5, the TR signal becomes '1' (reset), the reset of the block select counter 68 is released, and the BS signal becomes O'' (none). The multiplexer 71 selects the output signal Q (initial value "O") of the block select counter 68, which becomes the address input of the block select memory 67.

Further, since the WM multiplication signal is "0" (absent), the AND circuit 52 cannot perform a logical product, so no write permission signal is output.

In the first 01 cycle, block select memory 6
The address of 7 is "0", and the output 0 is block "5", that is, the block selection circuit selects 85 (not shown), the bidirectional bus driver 15 (not shown) is selected, and the pattern data After the contents of address "0" of the memory 35 (not shown) are read out to BUSl...BLISn, the CUP signal that has passed through the delay element 66 is sent to the block select block.
This becomes a count up signal for the counter 68, and its output signal Q is incremented by 1, indicating the address "1" of the block select memory 67.

In the second 02 cycle, the address of the block select memory 67 is "1" and the output O is block "3", that is, the block select circuit 54 selects S3 (not shown) and the bidirectional bus driver 13 (not shown). (not shown) is selected, and the address “0” of the pattern data memory 33 (not shown) is selected.
After the contents of “” are read out to BUSl...BUSn,
The CUP signal passed through the delay element 66 becomes a count up signal for the block select counter 68, and its output signal Q is incremented by +1 and sent to the block select memory 67.
This will indicate the address “2” of .

In the third 03 cycle, the address of the block select memory 67 is "2" and the output O is block "1".
That is, the block selection circuit 54 selects Sl, the bidirectional bus driver 11 is selected, and the pattern data memory 3
The contents of address "ON" of 1 are read out to 5usi...BUSn. At this time, the output signal Q of the loop end register 69 is set to 2 in advance, and in the C3 cycle, the block select counter 68 is also set to "2". Therefore, the input terminals A and B of the address comparator 70
A match is found, and -rescue force A-8 becomes "1" (ant).・The AND circuit 72 performs a logical product of the coincidence output A-B of the address comparator 70 and the CUP signal, and the output signal passes through the delay element 73 and becomes a count-up signal for the pattern address counter 56, and the pattern・
The address counter is incremented by 1. Further, it passes through the OR circuit 74 and becomes a reset signal for the block Φ select counter 68, the output signal Q becomes "0", and the address of the block select memory 67 returns to the initial value "0". Thereafter, reading is performed in the same manner. Note that the present invention is not limited to the embodiments only, and can be applied in many ways. For example, in FIG. 1, only the bus line (via the bidirectional bus driver 51) to the pattern data memory 51 is DM.
A (D 1rect M memory A access
) bus line, and can be similarly applied to data writing or reading.

[Effects of the Invention] As explained above, the present invention provides the following effects.

(1) To write or read data in discontinuous pattern data memory blocks, first set the address information and block selection information in the block select memory. Only data can be written or read continuously without any information.

(2i) Capturing or reading data in the parent pattern data memory block reduces the writing or reading time because the CPU no longer needs to provide address information and block information for each data item. I can do things.

(3) In discontinuous pattern data blocks,
You can freely set the order of blocks in which you want to write or read data.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of one embodiment of the present invention, Figures 2 to 5
The figure is a time chart showing the effect of the same configuration, FIG. 6 is a block diagram of a conventional circuit, and FIGS. 7 to 10 are time charts showing the effect of the same structure. 51... Bidirectional bus driver, 52... AND circuit, 53... Pattern data memory (31 to 3n are memory blocks), 54... Block selection circuit, 5
6... Pattern address counter, 67... Block select memory, 68... Block select counter, 69... Loop end register, 70... Address comparator, 71... ...Multiplexer. Applicant's agent Patent attorney Takeshi Suzue Foolish plan Figure 1 Figure 4

Claims (2)

[Claims] (1) Pattern data that stores information for each block.
a memory, a bidirectional bus driver provided between a CPU (central processing unit) bus line and the pattern data memory, a block selection circuit for selecting a block of the pattern data memory, and the CPU a block select memory for sequentially accumulating block selection information from and selecting an output of the block selection circuit according to the information; address setting means for writing or reading from the pattern data memory; and address setting means for writing or reading from the pattern data memory; A register that stores a value, a block select counter whose count value changes every time a write or read cycle changes, and the output of this counter is compared with the output of the register, and the block select counter is set according to the result. an address comparator that resets a counter and changes the address value of the address setting means; and a multiplexer that switches between the output of the block select counter and block selection information from the CPU to the block select memory. A memory block write/read circuit characterized by: (2) the pattern via the bidirectional bus driver;
The bus line to the data memory is connected to DMA (Direct).
2. The memory block write/read circuit according to claim 1, wherein the memory block write/read circuit is replaced with a bus line for memory access.