JPS63121191A - Input and output controller for random access memory - Google Patents

Input and output controller for random access memory

Info

Publication number
JPS63121191A
JPS63121191A JP61267068A JP26706886A JPS63121191A JP S63121191 A JPS63121191 A JP S63121191A JP 61267068 A JP61267068 A JP 61267068A JP 26706886 A JP26706886 A JP 26706886A JP S63121191 A JPS63121191 A JP S63121191A
Authority
JP
Japan
Prior art keywords
signal
data
writing
reading
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61267068A
Other languages
Japanese (ja)
Inventor
Takafumi Suzuki
Hideki Takei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP61267068A priority Critical patent/JPS63121191A/en
Publication of JPS63121191A publication Critical patent/JPS63121191A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To simultaneously read and write data in the same address by reading the data while an active signal is active when a reading signal and a writing signal are simultaneously active and writing the data with the delay of a delay circuit.
CONSTITUTION: A device is provided with the selection circuit 1 of the reading signal 102 and the writing signal 10 and an address and data storing circuit 2 in random access memories 3, 5. The selection circuit 1 of the reading and writing signals is constituted of a comparison circuit for comparing the writing signal with the active signal and the delay circuit 4 for delaying a signal outputted from the comparison circuit, reads the data when the reading signal 102 and the writing signal 100 are simultaneously active and writes the data with the delay for the delay circuit. Thereby, when the reading signal and the writing signal are simultaneously inputted, the written data is stored and after the data is read, the data is written.
COPYRIGHT: (C)1988,JPO&Japio
JP61267068A 1986-11-10 1986-11-10 Input and output controller for random access memory Pending JPS63121191A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61267068A JPS63121191A (en) 1986-11-10 1986-11-10 Input and output controller for random access memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61267068A JPS63121191A (en) 1986-11-10 1986-11-10 Input and output controller for random access memory

Publications (1)

Publication Number Publication Date
JPS63121191A true JPS63121191A (en) 1988-05-25

Family

ID=17439587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61267068A Pending JPS63121191A (en) 1986-11-10 1986-11-10 Input and output controller for random access memory

Country Status (1)

Country Link
JP (1) JPS63121191A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03278394A (en) * 1990-03-27 1991-12-10 Nec Corp Synchronous sram device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03278394A (en) * 1990-03-27 1991-12-10 Nec Corp Synchronous sram device

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