JPS62280795A - Image display control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention (Field of Industrial Application) What is the present invention? ! The present invention relates to an image display control circuit that performs control such that a plurality of types of display screens are independently obtained from image display data output from each of a number of memory brains.

(Prior Art) In medical tomography (also referred to as CT), multiple bits of overlay data are superimposed on intensity data for each dot and displayed as an image on a CRT. That is, binary image information such as explanatory characters or graphs is superimposed and displayed on the tomographic image (image image). In this case, overlay data of multiple pits, or multiple overlay memory brains, are not always displayed, but each brain is masked appropriately, and the combination of arbitrary brains is displayed on the CRT. is displayed. As an overlay method, instead of simply stretching the display screen over the entire surface, it is possible to set multiple types of screens, such as dividing the display screen horizontally and setting one window, and adjusting the position of these divisions and the window. The size and two positions of can be programmed arbitrarily.

Examples of display screens are shown in FIGS. 4 and 5. FIG. 4 is a diagram showing an image covered by two horizontally divided screens, and the screen is divided into approximately two equal parts by horizontally divided screen 1 and horizontally divided screen 2. Fifth
The diagram shows the first memory brain 0 and the second memory brain 1.
FIG. 12 is a diagram in which a window is provided on a horizontally divided screen that covers the entire surface of the superimposed image, and only the data of the first brane O is displayed in the window.

A conventional control circuit for obtaining the above-mentioned overlay image is shown in FIG. In the figure, 1 is a CRT controller that outputs the read address of the overlay data written in the overlay memory brain 2 and also performs CRT display control operations. etc. are programmed in advance, and reading is performed according to that program. Overlay memory brain 2 is No, 0 to N
It is composed of N+1 memory brains up to CR
The overlay image data to be displayed on T is stored.

3 is a parallel converter that converts, for example, 8 dots worth of parallel overlay brain data into serial data and outputs it.
There are N+1 serial converters, one of which is connected to each brain of the overlay memory brain 2.

Reference numeral 4 denotes a mask control register that removes unnecessary overlay brain data by supplying a clear enable signal to the corresponding parallel-to-serial converter 3 based on written mask information for each memory brain.

Reference numeral 5 denotes an OR (logical sum) circuit which inputs and synthesizes the overlay brain data converted into N+1 serial data of the parallel/serial converter 3. In the above circuit, the overlay brain data outputted from the overlay memory brain 2 based on the read address programmed with the horizontal split screen, window position, size, etc. is simultaneously transmitted to the parallel-to-serial converter for each brain for 8 dots. 3 is output. In order to cancel unnecessary memory brain data based on preset mask information, the mask III register 4 sends a brain mask enable signal to the parallel/serial converter F9!33 corresponding to the unnecessary memory brain, and・Clear the serial converter 3 so that it does not output any output.

The parallel-to-serial converter 3 that has not been cleared outputs the memory brain data as serial data. This parallel-to-serial conversion is performed because the access time of the read address of the CRT controller 1 cannot keep up with the sweep speed of the CRT, so eight dots are simultaneously read out and output serially to increase the speed eight times. Therefore, the number of dots simultaneously output from the overlay memory brain 2 is determined by the required speed increase factor.

(Problems to be Solved by the Invention) However, in such a conventional control circuit, it is not possible to independently perform mask control for each type of display screen at any time in each horizontally divided screen and window display.

That is, when an overlay memory brain consisting of an overlay memory brain is masked by a mask enable signal, the mask cannot be removed unless the mask information in the mask control register is changed, regardless of the type of memory brain (horizontal split screen, window). I can't. Also, when an overlay memory brain is mask disabled, the type of display screen of that memory brain (horizontal split screen).

Regardless of the window), it continues to be displayed unless the mask information of the mask control register is replaced with m.

Therefore, it is not possible to perform mask control independently at any time, such as displaying an overlay memory brain at a certain time, masking it at a different time, and displaying it again the next time. Next, considering the case of displaying horizontally divided screen 1 and horizontally divided screen 2 in Fig. 4, in order to realize this display screen, for example, horizontally divided screen 1 is placed on top of one memory brain, and horizontally divided screen 1 is placed on top of another one. It is necessary to store and display the data of the horizontally split screen 2 at the bottom of the memory brain, and the corresponding part of the thin memory brain in the middle of the screen of one memory brain is masked only at that time as described above. Therefore, it is not possible to allocate data to that part.Therefore, even if horizontally divided screen 1 and horizontally divided screen 2 are written in one memory brain, the same result will occur. Therefore, in this case, one memory brain can be divided into two
Since the third screen is shared, the memory capacity per screen will inevitably be reduced, which will cause problems if the screen requires a large memory capacity, that is, if you want to display large amounts of information using screen scrolling. becomes.

Also, as shown in Fig. 5, the horizontally split screen displays the first memory brain O of overlay memory brain 2 and the memory brain 1 of 12 overlapping each other, and the window displays only the first memory brain O of overlay memory brain 2. When displaying, the data in the first memory brain 1 in the portion corresponding to the window must be masked. Performing such an erasing operation each time requires software to carry out the sequence of clearing the data once loaded, which increases the burden on the software and wastes memory.

In this way, in the case of conventional overlay display, each screen cannot be masked independently, so there are problems such as small memory capacity per screen ■ Increased software project burden ■ Wasteful use of memory, etc. was occurring.

The present invention has been made in view of the above points, and its purpose is to perform mask control on each overlay memory brain individually for multiple types of display screens, so that the memory of the overlay memory brain is always available for use. iI that can be maintained and display multiple types of display screens as needed.
The object of the present invention is to obtain an image display control circuit.

(Means for Solving the Problems) The present invention solves the above problems by independently obtaining a plurality of types of display screens from the output image display data of each brain of a plurality of memory brains. The image display control circuit includes a control means for generating a screen identification signal indicating the type of display screen, and a memory brain that stores mask information for each type of display screen, and a control means for generating a screen identification signal indicating the type of display screen, and a memory brain that stores mask information for each type of display screen, and detects the mask by the screen identification signal from the control means. A register for selectively outputting information, a masking means for masking the image display data using mask information from the register, and a synthesizing means for adding and synthesizing the masked image display data for each of the memories. This is a characteristic feature.

(Function) The overlay memory brain outputs the display data for the display screen according to the memory address from the control means, and the display data from the overlay memory brain is output based on the contents previously set by the display screen type identification signal output at the same time. The data is masked and the output data of each memory brain is synthesized by a synthesizing means.

(Example) Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an image display control circuit according to an embodiment of the present invention. In the figure, reference numeral 10 is an overlay memory brain which is composed of four memory brains and is connected so as to simultaneously output 8 dots of display data. 11 is a memory address terminal,
For example, the four display screen type identification signal terminals (S+,
82, W.

B) is a CRT controller that outputs display data from the overlay memory brain 10 according to a memory address and also sends a display screen type identification signal to the encoder 12. The encoder 12 receives the type identification signal, converts it into a 2-bit binary code, and outputs a read address for brain mask information corresponding to the type of display screen.

Reference numeral 13 denotes an address bus of, for example, 32 bits from the CPU (not shown), which is input to the decoder 15 and mask control register file 16 via the buffer 14. The middle and lower 2 bits of the 32-bit address signal are input to the mask control register file 16 as a write address, and the decoder 15 decodes the address data and generates a write enable signal that enables the mask control register file 16 to be written. Occur. 17 is a 16-bit data bus, of which the lower 4 bits are input to the mask control register file 16 via a buffer 18. FIG. 2 shows an example of mask information stored in the memory space of the CPU. However, the shaded area indicates an unused portion. The mask control register file 16 has a 4×4 bit configuration as shown in FIG.
The write address of the lowest two bits of 3 is the binary number OO~
Mask the display screen type corresponding to the number 11 υlid
Specify and write to the register file 16 for use.

For example, the specification of the type is as follows.

O○...W (window) 01...B (base) 1o...Sl (horizontal split screen 1) 11...82 (horizontal split screen 2) One is from the register file 16 for mask control. This is a mask circuit that masks data from the memory brain so as not to be displayed using mask information for each overlay memory brain, and has four mask circuit units corresponding to each of the four overlay memory brains 2. Each mask circuit unit is composed of eight AND gates as shown in the figure. 21 is a parallel/serial converter that converts the 8-bit output of each OR circuit 20 into serial data.

Next, the operation of the embodiment configured as described above will be explained.

When a CPU (not shown) generates an address and data for arbitrary screen mask information to access the mask control register file 16, the decoder 15 uses the address bus 13. An address signal passed through the buffer 14 is received and decoded, and if a corresponding code is detected, a write enable signal is applied to the mask control register fill 16 to enable Bi writing. For data input of the mask control register file 16, the lower 4 bits of the data bus 17,
The lower 2 of address bus 13 is used for write address input.
Since the bits are connected, by making it writable, the type of display screen can be selected using the 2 bits of the input/output address, and the allocation of the overlay memory brain 2 to each type of display screen can be performed using the data from the data bus 17. Wealth gathering. An example of the contents written in this mask control register file 16 is shown in FIG.

On the other hand, the CRT controller 11 outputs a signal corresponding to the current display screen, and the encoder 12 converts it into a 2-bit signal. For example, if both sides of the current display are B, the B terminal of the CRT controller becomes active.
A binary number 01 is output through the encoder 12, and becomes a read address for the mask control register file 16. The mask control register file 16 uses this read address as shown in FIG.
Mask information 1" is output to memory brain 3, and mask information 0 is output to memory brain 1 and memory brain 2. Since the mask circuit 19 is composed of an AND gate, The 8-dot information of memory brain O and memory brain 3 of overlay memory brain 2 is output from one mask circuit, and memory brain 1 is outputted from one mask circuit.
The information of ゜2 is not output. In the OR circuit 20,
The information of the memory brain 0.3 is added, converted into serial information by the parallel-to-serial converter 21, and input to the CRT, where it is combined with separately applied image data and displayed. As the memory address by the CRT controller 11 is updated, the type information of the display screen is output to the encoder 12, and the display screen corresponding to the position of the screen on the CRT is sequentially changed and displayed, as shown in FIGS. 4 and 5. Complete the screen as shown without delay.

As described above, according to the present invention, different types of display screens can be quickly switched and displayed at any time without erasing the display data written in the overlay memory brain 10.

Note that the present invention is not limited to the above embodiments. For example, although an example is shown in which an AND circuit is used as the mask circuit 19, a direct register 7 of a shift register may also be used. In that case, the outputs of the shift registers, which are dot serial data for each masked brane, are combined together. In addition, the overlay memory brain targeted for tIll III was a memory brain that did not output one bit per brain, but it is a memory brain with several stages of bits, such as a color display memory with a 3-bit configuration of R, G, and B. It is also possible to control

(Effects of the Invention) As explained above, according to the present invention, it is possible to individually perform mask control on multiple types of display screens and obtain a composite screen of a horizontally divided screen and a window without erasing the memory of the overlay memory brain. Can be done. Furthermore, it is possible to use the memory space effectively and obtain a plurality of types of display screens as needed.

Therefore, the required memory capacity can be reduced and the burden on software can be lightened. Furthermore, since information can be stored in separate memory brains for each screen while displaying multiple types of screens, it is possible to cope with cases where one screen requires a large memory capacity, such as screen scrolling.

[Brief explanation of drawings]

FIG. 1 shows an image display control circuit device 18 according to an embodiment of the present invention.
Configuration block diagram, FIG. 2 is a diagram showing an example of mask information stored in the memory space of the CPU, FIG. 3 is a diagram showing an example of the configuration of a register file for mask control, FIGS. 4, 5
The figure shows the display screen 1-j, and FIG. 6 is a block diagram of a conventional image display control circuit. 1.11... CRT controller 2.1o... Overlay memory brain 3.21...
・Parallel/serial converter 4...Mask control register 5.20...OR circuit 12...Encoder 13
...Address bus 14,18...Buffer? 15
... Decoder 16 ... Mask control register file 17 ... Data bus 19 ... Mask circuit patent applicant Yokogawa Medical Systems Co., Ltd. Figure 2 Figure 35 Figure 4 Figure 5

Claims (1)

[Claims] In an image display control circuit that controls to independently obtain a plurality of types of display screens from image display data output from each brain of a plurality of memory brains, a control means for generating a screen identification signal indicating the type of display screen; a memory brain and a register that stores mask information for each type of display screen and selectively outputs the mask information according to a screen identification signal from the control means; and a mask means that masks the image display data using the mask information from the register. and a synthesizing means for adding and synthesizing the masked image display data of each of the memories.