JP2863561B2 - Memory read control circuit of CRT display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CRT display device that converts a character code stored in a code buffer into a video signal and displays the video signal on a CRT display unit. The present invention relates to a memory read control circuit of a CRT display device with improved timing for reading data.

2. Description of the Related Art A CRT display device incorporating a CRT used as a terminal device of an information processing device or the like is configured, for example, as shown in FIG.

That is, at the time of the writing operation, the main control unit 1 composed of a main processor or the like stores the character code of the character to be displayed on the CRT display unit 4 in the latch circuit 2b, and sends the character code to the CRT control unit 5 through the buffer circuit 2a. Set the write address. Next, the main controller 1 sends a command to the CRT controller 5 to write the corresponding character code into the code buffer 3. Then CR
The T control unit 5 sends a write control signal to the latch circuit 2b, and sends an address signal a of a write address set through the buffer circuit 2a to the code buffer 3. Then, the character code is stored in the corresponding address of the code buffer 3. The code buffer 3 stores, in addition to the character codes, head address values indicating the storage locations of the head character codes of the respective lines on the display screen. Generally, such a storage method is called a low table method.

That is, in the code buffer 3, a character code area 3a and a head address area 3b are formed as shown in FIG. In the character code area 3a, the character codes D of each line displayed on the CRT display unit 4 are stored in order. For example the character code D ₁₁ of the first character of the first line is stored in the address AD _1, each character code of the first row second and subsequent are sequentially stored below. And the address AD ₂
Character codes D ₂₁ of the first character of the second line is stored in the.
The head address area 3b, a character code each start address value indicating the storage location of the character code D of the first character of each line in the area _{3a AD 1, AD 2, ...} , AD N respective address
B _1, B _2, ..., are stored in the B _N.

Next, when reading and displaying the characters written as described above, the CRT control unit 5 reads the _first address value AD1 of the first line to the code buffer 3 in synchronization with the internally generated character clock signal c. It sends the address signal a indicating the address B _1. Code buffer 3, when the address signal a is inputted, and outputs the corresponding start address value AD _1. When CRT controller 5 reads the start address value AD ₁ via the buffer circuit 6, and sends the start address value AD ₁ to re-code buffer 3 as the read address signal a.
Hereinafter, the start address AD is synchronized with the character clock.
Sequentially sends each address AD consecutive shows each character location for one row following the ₁ sequentially to the code buffer 3.

As a result, the code buffer 3 sequentially sends the character codes D ₁₂ , D ₁₃ , D ₁₄ ,... On the same line from the first character code D ₁₁ in the storage location designated by the _first address value AD ₁ to the character generator 7.

The character generator 7, as shown in FIG.
A dot pattern of a character corresponding to each character code D and designated by the character code D is stored as, for example, a dot matrix 8 of [16 × 16]. When the line address signal b and the character clock signal c having the period T _C are input from the CRT control unit 5, each horizontal row of dot rows belonging to the vertical dot position indicated by the line address signal b is formed. The dots d _{0 to} d ₁₅ are output as the parallel dot data signal d.

Since the line address signal b output from the CRT control unit 5 indicates the dot position in the vertical direction of the dot matrix 8, every time one line (for one scan) is displayed on the CRT display unit 4, the CRT is displayed. It is counted up by a counter built in the control unit 5. It is cleared to 0 when the display of dot data for one line of characters is completed.

The parallel / serial converter 9 dot clock signal e from the CRT control unit 5 has the character clock signal c and a period T _D is input. Then, in response to the input of the character clock signal c, each dot data of the parallel dot data signal d is fetched internally, and each fetched dot data is sequentially output every time the dot clock signal e is input. That is, the input parallel dot data signal d is converted into a serial dot data signal f and transmitted to the next digital / analog converter (hereinafter abbreviated as D / A converter) 10.

The D / A converter 10 converts the input digital serial dot data signal f into an analog video signal g and sends it to the CRT display unit 4. The CRT display unit 4 converts the input video signal g into a horizontal synchronization signal h input from the CRT control unit 5.
And display on the display screen using the vertical synchronization signal i.

FIG. 7 is a time chart showing the relationship among the video signal g, the horizontal synchronization signal h, and the character clock signal c. As shown, the horizontal synchronizing signal h is included in the video signal g.
Display period T _S containing blank period T _B and a data signal which does not include a data signal including a horizontal blanking interval is formed.

Then, during a blanking period T _B in which nothing is displayed on the CRT display unit 4 of the video signal g, the CRT control unit 5 stores the character code to be displayed in the next display period T _S in the code buffer 3. Read the start address value AD. That is,
When the value LA of the line address signal b counted by the internal count is cleared to 0, the display of the dot pattern character for one line has been completed, and the CRT control unit 5 determines the first character code of the next line. It is necessary to read the storage location, and in response to the rising edge of the first character clock signal c after the start of the blanking period T _B , the address B is designated by the address signal a and the head stored in the corresponding address B is specified. The address value AD is read via the buffer circuit 6. And
The head address value AD is sent to the code buffer 3 as an address signal a.

[Problems to be Solved by the Invention] However, the following problems still exist in the CRT display device configured as shown in FIG.

That is, if the number of times the image displayed on the CRT display unit 4 is rewritten in one second is defined as a refresh frequency,
Obviously, the higher the refresh frequency is, the more the image does not flicker for the observer, and the image looks clear without tired eyes. Therefore, CRTs for monitors that display characters and graphics
In the display device, it is necessary to increase the refresh frequency.

Refresh frequency is the frequency f _V of the vertical synchronizing signal i, the increase this, when the number of scanning lines is constant,
It is necessary to increase the frequency f _H of the horizontal synchronizing signal h. When the frequency f _H of the horizontal synchronization signal h is increased, the current number of characters that can be displayed in one horizontal line of the display screen and the number of horizontal dots of the dot pattern that constitutes one character are maintained.
It is necessary to increase the frequency f _D (period T _D ) of the dot clock signal e and the frequency f _C (period T _C ) of the character clock signal c.

Increasing the frequency f _D of the dot clock signal e, it is necessary to increase the frequency response performance of the parallel / serial converter 9, to obtain a parallel / serial converter with high frequency characteristics are particularly technical difficulties Since there is no dot clock signal e
Of no particular problem even when increasing the frequency f _D.
The same applies to the next D / A converter 10.

However, the CRT control unit 5 is the blanking period T in _B, since the start address AD stored in response to the rise of the character clock signal c to the code buffer 3 is to read through the buffer circuit 6, If the frequency f _C of the character clock signal c is increased, the reading process may not be able to be completed in the cycle T _C , and there is a concern that an erroneous address may be specified or an address may not be specified at all.

In order to eliminate such inconvenience, the CRT control unit 5 must be replaced with a high-speed one that can access the code buffer 3 in a short time, and the code buffer must be replaced with a high-speed one. There is a problem that costs rise significantly.

The present invention has been made in view of such circumstances, and uses a particularly high-speed CRT control unit and a high-speed memory code buffer by increasing the period of a character clock signal only during a fetch period in a blanking period. CRT display device that can increase the frequency of the character clock signal and dot clock signal without increasing the refresh frequency, and can greatly improve the image quality of displayed characters without significantly increasing the manufacturing cost It is an object of the present invention to provide a memory read control circuit.

[Means for Solving the Problems] In order to solve the above problems, a memory read control circuit of a CRT display device according to the present invention comprises a character code for one screen to be displayed on a CRT display unit and a first character of each line in the character code. It has a row table type code buffer for storing each head address value indicating the storage location of the code, and reads the head address value of the code buffer in response to the character clock signal during the blanking period of the video signal. The address of the leading address value is sent to the code buffer, and each character code stored after the corresponding address is sequentially sent out from the code buffer, and each sent character code is sent to the video buffer in response to a character clock signal. In a CRT display device that converts each signal into a signal and displays the corresponding character pattern on the CRT display device, A frequency divider that divides the clock signal and outputs a frequency-divided signal; and a time-counting circuit that counts the time required to read the first address value from the code buffer from the start time of the blanking period as a predetermined fetch period. A frequency division signal insertion circuit for inserting a frequency division signal into the character clock signal only during the fetch period.

[Operation] In the memory read control circuit of the CRT display device configured as described above, the cycle of the frequency-divided signal output from the frequency divider is longer than the cycle of the character clock signal. For example, when the frequency division ratio of the frequency divider is 1 / N, the cycle becomes N times. Then, the frequency-divided signal insertion circuit inserts the frequency-divided signal only during the fetch period determined within the blanking period of the character clock signal.

Therefore, for example, the CRT control unit reads the start address value from the code buffer in synchronization with the rising edge of the portion of the character clock signal whose period has become longer, so that there is enough time before the next rising edge of the character clock signal. Exists. Therefore, it is possible to prevent an error from occurring in the reading process of the head address value.

Since the period other than the fetch period of the character clock signal is the original short period, the output period of the character code output from the code buffer is the period of the original character clock signal. That is, the cycle of the character clock signal is extended only when the head address value is read from the code buffer.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a memory read control circuit of the CRT display device of the embodiment. The same parts as those in FIG. 4 are denoted by the same reference numerals.

During a write operation, a main control unit 1 comprising a main processor
Then, a character code and an address to be displayed on the CRT display unit 4 are set in the latch circuit 2 and the CRT control unit 11. And
The CRT control section 11 sends a write control signal to the latch circuit 2b and sends an address signal a read through the buffer circuit 2a to the code buffer 3. Thus, the character code D for one screen to be displayed on the CRT display unit 4 is stored in the character code area 3a shown in FIG. 5 in the code buffer 3, and at the same time, the start address value AD of each line is stored in the start address area 3b.
Is stored. Character generator 7 contains a CRT
The dot pattern of each character to be displayed on the display unit 4 is stored as a [16 × 16] dot matrix 8 in an area designated by the corresponding character code D, for example, as shown in FIG.

Next, a description will be given of a reading operation. In the CRT control section 11, a register for temporarily storing each head address value AD read from the code buffer 3 via the buffer circuit 6, and a vertical direction of the dot matrix 8 are provided. A counter is provided for counting the value LA (0 to 15) of the line address signal b for specifying the dot position. Further, the CRT control unit 11
Sends a blanking signal j for setting a blanking period T _B in the video signal g shown in FIG. 7 to the character clock signal generation circuit 12 and the correction output from the character clock signal generation circuit 12. It takes in the character clock signal k and sends out the corrected character clock signal k to the character generator 7 and the parallel / serial converter 9.

The parallel / serial converter 9 converts the parallel dot data signal d output from the character generator 7 into a serial dot data signal f in synchronization with the dot clock signal e output from the CRT control unit 11. The D / A converter 10 converts the serial dot data signal f output from the parallel / serial converter 9 into an analog video signal g and sends it to the CRT display unit 4. The CRT display unit 4 converts the input video signal g into a CRT control unit 11
Are displayed using the horizontal synchronizing signal h and the vertical synchronizing signal i sent from the STA.

The character clock signal generation circuit 12 is, for example, a second
It has the circuit configuration shown in the figure.

Blanking signal j which defines the blanking period T _B input from the CRT controller 11, a Futchi period T _F for CRT controller 11 reads the start address value AD of the code buffer 3 to the counting circuit 13 for counting Applied. This timing circuit
Reference numeral 13 denotes five-stage flip-flops 14a, 14b, 14 connected in series.
c, 14d, 14e, an inverter 15, and an AND gate 16. Then, the blanking signal j is applied to the input terminal D of the first flip-flop 14a, a character clock signal as a reference having a period T _C outputted from the oscillator 17 to the clock terminal of the flip-flops 14a~14e m is input. Therefore, as shown in FIG.
The output signal of the last-stage flip-flop 14e lags the blanking signal j by almost four periods (4T _C ). Then, the level of the output signal is inverted by the inverter 15,
The inverted signal n is input to the AND gate 16. The output signal o of the first-stage flip-flop 14a is input to the other end of the AND gate 16. Accordingly, as shown in FIG. 3, the output signal of the AND gate 16 is a fetch period signal p having a fetch period T _F equal to four times the period T _C (4T _C ).

The fetch period signal p output from the clock circuit 13 is input to the next frequency-divided signal insertion circuit 18. The input fetch period signal p is input to one end of an OR gate 19, and the other end of the OR gate 19 is input with a reference character clock signal m output from the oscillator 17. Therefore, in the output signal q of the OR gate 19, the fetch period T _F
Only high (H) level constant, the rest period is a character clock signal having a period T _C. This output signal q is input to the next AND gate 20.

Also, the fetch period signal p output from the timing circuit 13
Is inverted at the inverter 21 and input to one end of the OR gate 22. At the other end of the OR gate 22, a frequency divider 23 for dividing the frequency of the character clock signal m by half
Is input. Therefore, this OR gate 22
In the output signal s, the fetch period T _F only the signal level with a period 2T _C is inserted divided signal u vary, and all the rest of the time H level. Therefore, the output signal of the AND gate 20 for calculating a logical product of the output signal s and an output signal q of the OR gate 19, the frequency division signal u of the fetch period T _F only period 2T _C is inserted, the time remaining the correction character clock signal k as a character clock signal m of the period T _C.

Next, the operation of the memory read control circuit of the CRT display device configured as described above will be described with reference to the time chart of FIG.

First, when the blanking signal j rises with the character code D of one screen sentence and each head address value AD stored in the code buffer 3, the rising of the character clock signal m which is the first reference from the rising time. , The blanking signal j is taken into the first flip-flop 14a. Then, the output signal o of the flip-flop 14a rises to the H level. Therefore, counting from the time t ₀ of fetch period T _F is started. As a result, the period T _C of the character clock signal m, which is based on the period of the corrected character clock signal k output from the character clock signal generation circuit 12, is 2
The period becomes twice as long as 2 _TC . The period 2T _C of this twice returns to the original period T _C upon completion fetched period T _F.

The CRT controller 11, at time t ₀ in synchronism with the rising edge of the first correction character clock signal k fetch period T _F is started, the read address signal a is sent specifying the address B for code buffer 3. Then
And it outputs the start address value AD ₁ of the code buffer 3 are stored in the corresponding address B. Start address value AD ₁ output is stored in the internal register of the temporarily CRT controller 11 via the buffer circuit 6.

Note that the data bus is 8 bits of the CRT control unit 11, upon fetching the upper start address, when reading over twice in the order of lower, in FIG. 3, first, the address B at time t ₀ sends a code buffer 3, it fetches the upper address at time t _1, and stored in an internal register. At the same time, sends the next address at time t ₁ in the code buffer 3, fetches the lower address in time t _2, the stored internal registers remain attached to the previous upper address.

Then, the blanking period T in response to the rise of the first correction character clock signal k after _B ends, and sends to the start address value AD ₁ read address signal code buffer 3 re-incorporated in a a read of previously. Thus, the code buffer 3 first character codes D ₁₁ in the first row stored in the corresponding address AD ₁ is output. Further, the CRT control unit 11
Sequentially outputs the addresses of the corresponding rows in synchronization with the character clock. As a result, the character codes D ₁₂ , D ₁₃ ... Of the corresponding line are sequentially sent from the code buffer 3 to the character generator 7.

The character generator 7 inputs each character code D
Of the dot matrix 8 corresponding to the character code D corresponding to the character code D stored at the position designated by the dot code in the vertical dot position designated by the line address signal b. Synchronously, it is sent to the next parallel / serial converter 9.

The parallel / serial converter 9 converts the input parallel dot data signal d into a serial dot data signal f based on the corrected character clock signal k and the dot clock signal e applied from the CRT control unit 5. Further, the serial dot data signal f is converted into a video signal g by the D / A converter
Displayed on the RT display unit 4.

If the memory read control circuit of the thus constructed CRT display device, in the correction character clock signal k, in the preset within fetched period T _F in the blanking period T _B of the video signal g, the cycle There has twice the period of the periodic T _C of the character clock signal m as a reference. The period other than the fetch period T _F is the period T _C of the character clock signal m.

Therefore, in the fetch period _TF during which the CRT control unit 11 reads the start address value AD from the code buffer 3, the rising period of the character clock signal k is long, so that the read time of the start address in the row table method can be spared. . Therefore, reading wrong data,
It is possible to suppress occurrence of an error such as a loss of the read data.

Further, the character generator 7 and a parallel / serial converter 9 so operates in the period T _C of the basic character clock signal m, display speed to CRT display unit 4 is not lowered.

That is, conversely, even if the frequency f _C of the basic character clock signal m is doubled, the period of the corrected character clock signal k within the fetch period _TF is the same as the period of the conventional CRT display device shown in FIG. It is. Therefore, by doubling the frequency f _C of the basic character clock signal m and shortening the cycle of the corrected character clock signal k input to the character generator 7 and the serial / parallel converter 9 to half, the CRT display unit 4 Display speed can be improved. In this case, the refresh frequency can be doubled by setting the frequencies of the dot clock signal e, the horizontal synchronizing signal h, and the vertical synchronizing signal i to double, so that
The image quality of the character image displayed on the CRT display unit 4 can be greatly improved.

The present invention is not limited to the embodiments described above. When the number of bits of the start address value AD to be read is large, the number of flip-flops 14a to 14e is increased,
In addition, by setting the fetch period _TF to be long, it is possible to read out the head address value AD in a plurality of times.

[Effect of the Invention] As described above, according to the memory read control circuit of the CRT display device of the present invention, the cycle of the character clock signal is increased only during the fetch period in the blanking period.
Therefore, the frequency of the character clock signal and the dot clock signal can be increased without shortening the access time of the code buffer of the CRT control unit, and the refresh frequency can be increased, without significantly increasing the manufacturing cost. The image quality of the displayed characters can be greatly improved.

[Brief description of the drawings]

1 to 3 show a memory read control circuit of a CRT display device according to an embodiment of the present invention. FIG. 1 is a block diagram showing the whole, and FIG. 2 shows a character clock signal generation circuit. FIG. 3 is a time chart showing the operation, FIG. 4 is a block diagram showing a conventional CRT display device, FIG. 5 is a diagram showing the storage contents of a general code buffer, and FIG. FIG. 7 is a time chart showing the relationship between a general video signal, a horizontal synchronizing signal, and a character clock signal. 1 ... Main control unit, 3 ... Code buffer, 4 ... CRT display unit,
6 ... buffer circuit, 7 ... character generator, 9 ...
Parallel / serial converter, 10 ... D / A converter, 11 ... CRT controller, 12
… Character clock signal generation circuit, 13… Timekeeping circuit, 17
... oscillator, 18 ... divided signal insertion circuit, 23 ... divider.

Claims (1)

(57) [Claims] A row table for storing a character code (D) for one screen to be displayed on a CRT display section (4) and a head address (AD) value indicating a storage location of a head character code of each line in the character code. A code buffer (3) for reading the head address value of the code buffer in response to a character clock signal within a blanking period (T _B ) of a video signal, and replacing the address of the read head address value with the read address. Each character code stored after the corresponding address is sequentially transmitted from the code buffer and transmitted to the code buffer, and each transmitted character code is converted into a video signal in response to the character clock signal. In a CRT display device for displaying each corresponding character pattern on a CRT display unit, a frequency-divided signal is output by dividing the character clock signal. A frequency divider (23), and a clock circuit (13) for clocking the time required to read the head address value from the code buffer from the start time of the blanking period as a predetermined fetch period (T _F ). A frequency division signal insertion circuit (18) for inserting the frequency division signal into the character clock signal only during the fetch period.