JP2866675B2 - Character display device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a character display device that converts a character code stored in a code buffer into a video signal and displays the video signal on a CRT display unit.

2. Description of the Related Art A character display device incorporating a CRT used as a terminal of an information processing device or the like is configured as shown in FIG. 4, for example.

That is, at the time of the writing operation, the main control unit 1 constituted by the main processor or the like stores the character code of the character to be displayed on the CRT display unit 4 in the latch circuit 2b, and stores the character code in the CRT control unit through the buffer circuit 2a. 5 is set to the write address. Next, the main controller 1 sends a command to the CRT controller 5 to write the corresponding character code into the code buffer 3. Then CR
The T control unit 5 sends a write control signal to the latch circuit 2b, and sends an address signal a of a write address set through the buffer circuit 2a to the code buffer 3. Then, the character code is stored in the corresponding address of the code buffer 3. The code buffer 3 stores, in addition to the character codes, head address values indicating the storage locations of the head character codes of the respective lines on the display screen. Generally, such a storage method is called a low table method.

When reading and displaying the characters written as above,
The CRT controller 5 sends an address signal a for reading the first address value of the first row to the code buffer 3 in synchronization with the internally generated character clock signal e. When the address signal a is input, the code buffer 3 outputs the corresponding head address value b. When reading the start address value b via the buffer circuit 6, the CRT control section 5 sends the start address value b to the code buffer 3 again as a read address signal a. Subsequently, consecutive addresses indicating the storage locations of the characters for one line following the head address are sequentially transmitted to the code buffer 3 sequentially in synchronization with the character clock.

As a result, the code buffer 3 sequentially sends the character codes c on the same line to the character generator 7 from the first character code at the storage location designated by the first address value.

The character generator 7, as shown in FIG.
A dot pattern of a character corresponding to each character code c is stored as, for example, a dot matrix 8 of [16 × 16]. Then, the character codes c and CR are read from the code buffer 3.
When the line address signal d and the character clock signal e are input from the T control unit 5, the line address signal d of the character dot pattern indicated by the character code c is input.
The 16 dots forming one horizontal row of dot rows belonging to the vertical dot positions indicated by (1) are output as parallel dot data signals g.

Since the line address signal d output from the CRT control unit 5 indicates the vertical dot position of the dot matrix 8 in FIG. 5, the line address signal d has 16 values from LA = 0 to 15. Every time one line (for one scan) is displayed on the CRT display unit 4, the count is incremented by a counter built in the CRT control unit 5. When the display of the dot data for one line of characters is completed, the initial value LA is cleared to 0.

Therefore, in this case, the line address signal d is composed of 4 bits.

The parallel / serial converter 9 converts the input parallel dot data signal g into a serial dot data signal i in synchronization with the dot clock signal h input from the CRT control unit 5, and outputs the next digital / analog converter. (Hereinafter abbreviated as D / A converter). The D / A converter 10 converts the digital serial dot data signal h into an analog dot data signal, that is, a video signal j, and sends it to the next CRT display unit 4. The CRT display unit 4 displays the input video signal j on the display screen using the horizontal synchronization signal k and the vertical synchronization signal m input from the CRT control unit 5.

[Problems to be Solved by the Invention] However, the following problems still exist in the character display device using the CRT configured as shown in FIG.

Conventionally, CRTs used as terminals for information processing devices, etc.
In most cases, characters displayed on a character display device in which is embedded are only alphanumeric characters that can be displayed by ASCII codes.
However, in recent years, the processing capability of the information processing apparatus has been improved, and it has become possible to handle character codes such as kana kanji, and it is desired that a character display apparatus also displays kana kanji in addition to the conventional alphanumeric katakana. .

However, the kana-kanji character has a more complicated character pattern than the alphanumeric katakana, and as shown in FIG. I have. Therefore, the number of scans (the number of lines) on the CRT display unit 4 for displaying one character pattern is doubled as compared with the conventional alphanumeric katakana dot pattern 8 shown in FIG. Therefore, there are 32 values LA specified by the line address signal d specifying the dot position in the vertical direction from LA = 0 to 31. To specify 32 values, the line address signal d
Requires 5 bits of data.

Therefore, even if the character generator 7 in the conventional character display device is replaced with a kana-kanji dot matrix.
Even if 8a is replaced with a stored character generator, the conventional character display device cannot cope with kana-kanji display unless the number of bits of the line address signal d output from the CRT control unit 5 is changed. .

It is sufficient to newly develop a CRT control unit 5 capable of outputting a line address signal of 5 bits or more, but the development cost and the manufacturing cost are greatly increased.

The present invention has been made in view of such circumstances, and adds a status indicating a vertical position in a dot pattern character of a corresponding line to each head address value in a code buffer, and compares this status with a conventional line address signal. By creating an extended line address signal with
Even if a character generator that stores an enlarged dot matrix such as kana-kanji is used, a general-purpose inexpensive CRT control unit can be used, and a display device that can display complex characters such as kana-kanji without increasing manufacturing costs. The purpose is to provide.

[Means for Solving the Problems] In order to solve the above problems, the character display device of the present invention comprises:
CR for displaying one dot pattern character in multiple lines
T display part, each character code to be displayed on the CRT display part, each head address value indicating the storage location of the character code at the head of each line, and the head address value added to each head address value, and the corresponding line is displayed in the vertical direction of the dot pattern character. A row table type code buffer for storing a status indicating whether the position is located at the position, and reading out each head address value of the code buffer and the status attached to the corresponding head address value in one line cycle and indicating the corresponding head address value A CRT control unit for sequentially outputting each character code on the same line from the first character code of the storage location and outputting a line address signal cleared in one line cycle, and a line address signal output from the CRT control unit; An address conversion circuit that adds the read status bit to each bit data and outputs it as an extended line address signal Path and the dot matrix of each dot pattern character to be displayed on the CRT display unit, and the dot matrix specified by the extended line address signal output from the address conversion circuit in the dot matrix specified by the character code output from the code buffer A character generator that outputs a horizontal dot row existing in a row as a parallel dot data signal, a parallel / serial converter that converts a parallel dot data signal output from the character generator into a serial dot data signal, Converts the serial dot data signal output from the serial converter to an analog dot data signal and converts
And a digital / analog converter for sending to the T display unit.

[Operation] In the character display device configured as described above, the CRT
To display one dot pattern character on the display,
Since the number of dots in the vertical direction of a dot pattern character is large, the conventional number of scans for one line is insufficient. The code buffer is a so-called low table type memory, in which each character code displayed on the display screen is stored, each head address value indicating a storage location of the first character code of each of the divided lines, and a corresponding line. A status indicating where the dot pattern character is located in the vertical direction is stored.

Then, the CRT control unit reads each head address value, sequentially specifies each address below the head address, and sequentially outputs the character code of each line stored in each address, but the status is read simultaneously and the CRT is read. It is combined with the line address signal output from the control unit and sent to the character generator as an extended line address signal.

The line address signal is cleared to the initial value by scanning one line, but the head address does not change unless scanning of all the lines for one dot pattern character divided into a plurality of lines is completed. Therefore, the extension line address signal can designate all the vertical dot rows of the dot matrix stored in the character generator.

Thus, an extended dot pattern character such as a kana kanji can be displayed on the CRT display unit by the conventional CRT control unit.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of the character display device of the embodiment. The same parts as those in FIG. 4 are denoted by the same reference numerals.

During the write operation, the main control unit consisting of the main processor
From 11, a character code and an address to be displayed on the CRT display unit 4 are set in the latch circuit 2 b and the CRT control unit 5. Then, the CRT controller 5 sends a write control signal to the latch circuit 2b and sends an address signal a set through the buffer circuit 2a to the code buffer 13. Thus, the character code to be displayed on the CRT display unit 4 is stored in the code buffer 13.

FIG. 2 is a dot matrix of [32 × 32] in FIG.
FIG. 8 is a diagram showing the storage contents of a code buffer 13 when storing a character code of a dot pattern character which must be displayed by being divided into two lines as shown by 8a. In the character code area 13a, the character codes D of the divided lines are sequentially stored. In the examples,
Since the first and second lines have the same character, the addresses AD ₂ , AD ₄ ,... Corresponding to the even lines are not set. For example the character code D ₁₁ of the first character of the first line is stored in the address AD _1, each character code of the first row second and subsequent are sequentially stored below. The character codes D ₃₁ of the first character of the third line in the address AD ₃ are stored.

The start address area 13b has a 13-bit start address value AD indicating the storage location of the character code D of the start character of each line, and a 1-bit status indicating the vertical position of the dot pattern character in the dot pattern character. S is stored. For example at the beginning of the start address region 13b, the status S (S of indicating that located above the start address value AD ₁ and the dot pattern character of the first row [0]
= 0) is stored, and the second is the first address value of the first row
A status S (S = 1) of AD1 and [1] indicating that it is located below the dot pattern character is stored. That is, each head address value AD of the even-numbered row matches the head address value AD of the odd-numbered row, and only the status S is different.

In the character generator 14, dot patterns of Kana-Kanji are stored as a [32 × 32] dot matrix 8a in an area designated by the character code of the Kana-Kanji, for example, as shown in FIG.

The CRT control unit 5 includes a register 5a for temporarily storing each head address value AD read from the code buffer 13 via the buffer circuit 6, and 4-bit data for specifying a vertical dot position of the dot matrix 8a. A counter 5b for counting the values of the line address signal d from LA = 0 to LA = 15 is provided.

Further, the address conversion circuit 15, as shown in FIG.
For each bit data of the 4-bit line address signal d output from the CRT control unit 5, one of the statuses S read simultaneously with each head address value AD from the code buffer 13 is added.
The bit generator adds bit data to the most significant bit and generates a 5-bit extended line address signal n as a character generator.
Send to 14.

The parallel / serial converter 9 and the D / A converter 10 are almost the same as the parallel / serial converter 9 and the D / A converter 10 of the conventional device in FIG.

The operation of the thus configured character display device will be described.

It is assumed that each character code of the kanji displayed on the CRT display unit 4 is stored in the code buffer 13 in the low table format shown in FIG. During a read operation, CR
The T control unit 5 sends an address signal a for reading the _first address value AD ₁ of the first row and the attached status S to the code buffer 13. Code buffer 13, the address signal a is inputted, and outputs the data p of 14 bits consisting of the corresponding start address value AD ₁ and status S.
The 1-bit status S of the 14-bit data p is input to the address conversion circuit 15, and the remaining 13-bit head address value AD ₁ is input to the CRT control unit 5 via the buffer circuit 6.

With CRT controller 5 temporarily stores the register 5a of the start address value AD ₁ input, the count value of the counter 5b 0
To clear. Therefore, at this time, the value of the extended line address signal n applied to the character generator 14 is LA = 0.

Then, the start address value AD ₁ of the read address signal a
To the code buffer 13 again. Then, it sends the first character code D ₁₁ of 13-bit storage location start address value AD ₁ code buffer 13 to specify the character generator 14. Then, the CRT control unit 5 sequentially outputs each address corresponding to each character on the same line after the _first address value AD1 in synchronization with the character clock. Thus, the code buffer 13 stores the character codes D ₁₂ , D ₁₃ ,
Are sequentially transmitted to the character generator 14. Also,
With CRT controller 5 sends a character clock signal e having a predetermined period T _C to the character generator 14 and a parallel / serial converter 9, a dot clock signal h having a period T _D to the parallel / serial converter 9 Send out.

When the character clock signal e is input from the CRT control unit 5, the character generator 14
In the dot matrix 8a designated by the character code inputted from the address conversion circuit 15, one horizontal row of dot rows belonging to the vertical dot position indicated by the value LA (= 0) of the extension line address signal n inputted from the address conversion circuit 15 Each of the 32 dots d _{0 to} d ₃₁ constituting the pixel is output as a parallel dot data signal g.

A parallel dot data signal g sequentially output from the character generator 14 in synchronization with the character clock signal e
Is input to the next parallel / serial converter 9. The parallel / serial converter 9 fetches each dot data of the parallel dot data signal g into the shift register in response to the input of the character clock signal e, and synchronizes the dot data with the dot clock signal h from the CRT control unit 5. Each dot data taken into the shift register is sequentially output. That is, the input parallel dot data signal g is converted into a serial dot data signal i and transmitted to the next D / A converter 10. The D / A converter 10 converts the digital serial dot data signal i into an analog dot data signal,
That is, it is converted into a video signal j and transmitted to the CRT display unit 4. The CRT display unit 4 displays the input video signal j on the display screen using the horizontal synchronization signal k and the vertical synchronization signal m input from the CRT control unit 5.

When the display processing of each dot data for one line (one scan) is completed, the CRT control unit 5 increases the count value of the counter 5b by one. Since the value of the status S input to the address conversion circuit 15 does not change, the value LA of the extended line address signal n applied to the character generator 14 increases by 1 (LA = 1).

Thus, when the next character clock signal e is input to the character generator 14, it belongs to the vertical dot position indicated by the value LA (= 1) of the extended line address signal n of the dot matrix 8a specified by the previous character code. 32 dots forming one horizontal row of dot rows are output as parallel dot data signals g.

In this way, the counter 5b counts up every time one line (scan) is displayed, and when the count value exceeds the maximum value 15 which can be displayed by 4 bits, one line, that is, the upper half of the dot pattern character is displayed. Therefore, the count value is cleared to 0. Then, the _first address value AD ₁ and [1] in the second row of the first address area 13b of the code buffer 13
Is read out. As a result, the value LA of the extension line address signal n applied from the address conversion circuit 15 to the character generator 14 is 16, which is [10000], as shown in FIG.

CRT controller 5 is applied to the code buffer 13 the first address value AD ₁ as the address signals a, each character code of the first line from the first character code D ₁₁ in the first row stored in the address AD ₁ D ₁₁ , D ₁₂ ,.
Send to 14.

The character generator 14 outputs each dot in the horizontal direction of each dot pattern 8a of the character code designated by the code buffer 13 as a parallel dot data signal g.

However, since the value (LA) of the extended line address signal n output from the address conversion circuit 15 starts from LA = 16 this time, each dot data in the lower half of the dot matrix 8a in FIG. It is displayed on the CRT display unit 4 for each line (scan).

Therefore, the dot pattern character is displayed on the CRT display unit by the upper half display of the first line and the lower half display of the second line this time.
Lines are displayed.

As described above, in the case of Kana-Kanji characters in which the number of dots in the vertical direction in the dot matrix is larger than that of the conventional alphanumeric characters, one dot pattern character is divided into a plurality of lines having the same character code, and a low table code is used. buffer
When the CRT control unit 5 reads the head address value AD of each line in the same procedure as in the conventional method, the status S indicates the position of the corresponding line in the vertical direction of the dot pattern character. Are read out at the same time, and the status S is added to the line address signal d output from the CRT control section 5 as upper bits. Therefore, the vertical dot position of the dot matrix 8a, which can be specified by the extended line address signal n input to the character generator 14, can be more than doubled as compared with the conventional display device shown in FIG.

As a result, even if the same character code is specified over two lines, different positions in the vertical direction of the dot matrix 8a can be specified by the extended line address signal n. Not
Kana kanji with a larger number of vertical dots in the dot matrix compared to conventional alphanumeric characters
Can be displayed.

Therefore, complicated characters such as kana-kanji can be displayed without significantly modifying the conventional character display device exclusively for alphanumeric characters, and the manufacturing cost of the entire device can be reduced.

The present invention is not limited to the embodiments described above. In the embodiment, the dot pattern characters displayed on the CRT display unit 4 are divided into two lines and displayed. However, the dot matrix 8a such as a kana-kanji character shown in FIG.
If the number of dots in the vertical direction is three or four times the number of dots in the vertical direction of the conventional dot matrix 8 of alphanumeric katakana, it can be divided into three or four lines and displayed. In addition,
In this case, the status S to be added to each start address value AD of the start address area 13b of the code buffer 13 needs to be composed of 2 bits or more.

[Effects of the Invention] As described above, in the character display device of the present invention, one dot pattern character is displayed in a plurality of lines, and the top and bottom positions of the corresponding line are set to the head address value of each line in the code buffer. An extended line address signal is created by adding the indicated status and the status and the conventional line address signal. Therefore, even if a character generator that stores a dot matrix that is vertically expanded compared to conventional alphanumeric characters such as kana kanji is used, the conventional CRT control unit can be used as it is, and the manufacturing cost will increase significantly Complex characters such as kana-kanji can be displayed without the need.

[Brief description of the drawings]

1 to 3 show a character display device according to an embodiment of the present invention. FIG. 1 is a block diagram showing the whole, FIG. 2 is a diagram showing the contents stored in a code buffer, and FIG.
FIG. 4 is a diagram showing the operation of the address conversion circuit, FIG. 4 is a block diagram showing a conventional character display device, FIG. 5 is a diagram showing a general alphanumeric dot matrix, and FIG. It is a figure which shows the dot matrix of a kana-kanji. 4: CRT display unit, 5: CRT control unit, 8, 8a: dot matrix, 9: parallel / serial converter, 10: D / A converter, 11: main control unit, 13: code buffer, 13a: character code Territory, 1
3b: Start address area, 14: Character generator,
15 ... Address conversion circuit.

Claims (1)

(57) [Claims] A CRT display unit for displaying one dot pattern character in a plurality of lines, and a head code indicating a storage location of a character code to be displayed on the CRT display unit and a head character code of each line. A row table type code buffer (13) for storing an address value and a status indicating the vertical position of the dot pattern character which is added to each head address value, and a row table type code buffer (13); The head address value of the code buffer and the status attached to the head address value are read out, and the character codes on the same line are sequentially output from the head character code of the storage location indicated by the head address value, and the one line is output. A CRT control unit (5) for outputting a line address signal cleared in a cycle, and each bit data of the line address signal output from the CRT control unit An address conversion circuit (15) for adding the read status bits to output as an extended line address signal, and storing a dot matrix of each dot pattern character to be displayed on the CRT display unit; A character generator for outputting, as a parallel dot data signal, a horizontal dot row existing in a dot row specified by an extended line address signal output from the address conversion circuit in a dot matrix specified by an output character code;
A parallel / serial converter (9) for converting a parallel dot data signal output from the character generator into a serial dot data signal; and converting a serial dot data signal output from the parallel / serial converter into an analog dot data signal. And a digital / analog converter (10) for converting the video signal into a video signal and transmitting the video signal to the CRT display unit.