JPS5814678B2 - display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display device such as a cathode ray tube display (CRT) that displays characters, numbers, figures, etc., and particularly to a display device that can display arbitrary patterns in each area of a display unit section on a display screen. This display unit section is a zone that displays one character, that is, one character is divided into, for example, 12 x 8 dots 7.
This is 12×8 dots when displayed in trix.

Furthermore, the above-mentioned display unit section is basically expanded in integer multiples, and any pattern can be displayed in this expanded area.

Generally, when characters, symbols, figures, etc. are to be displayed on a CRT device, expected characters, symbols, etc. are stored in advance in a character generator.

That is, since the character generator converts data information, for example, dot information for display corresponding to each character code information, dot information corresponding to code information such as characters, symbols, etc. is stored in advance.

Therefore, only the characters and symbols stored in the character generator can be displayed, and the characters for display are extremely limited.

Furthermore, if an attempt was made to increase the number of display characters, the memory of the character generator would have to have a large capacity, making it expensive.

The present invention solves the above-mentioned problems, and enables the character generator to display any pattern in each area of the display unit section on the display screen, regardless of the characters, symbols, etc. stored in advance. This is what I did.

The present invention will be described in detail below with reference to an embodiment of the drawings.

FIG. 1 shows a display unit section composed of 12 dots vertically and 8 dots horizontally, which displays one character, and also shows a state in which arrows are displayed as dots in this display unit section.

FIG. 2 shows the data pit pattern indicated by the arrow shown in FIG. 1, and as can be seen from FIGS. 1 and 2, the data bit pattern is displayed as it is in the display unit section.

That is, data such as characters and symbols to be displayed is transferred from the central processing unit (CPU) side as data pits (dot information) as shown in FIG.

In this case, the display information for one display unit section is 12
Of the byte (12 x 8 bits) of data, the bit pattern of the first byte (8 bits) is made to correspond to the first dot row (the uppermost horizontal 8 dots) of the display unit section, and the second 1 byte of data is It corresponds to the second dot row (second horizontal 8 dots from the top) of the display unit section, and the same goes for the rest, so that the 12th 1 byte of data corresponds to the 12th dot row of the display unit section.

Therefore, when a data pattern as shown in FIG. 2 is sent, a display as shown in FIG. 1 will be displayed.

In this way, by transferring information such as characters and symbols to be displayed in the data pit pattern as described above, it is possible to display the characters and symbols without converting them into dot information by the character generator, and thereby the display unit section can be displayed. This means that any display can be made in this area.

Further, when displaying complex Chinese characters or figures, for example, it is desirable to expand the display unit section by an integer multiple and display any pattern in this expanded area.

That is, as shown in FIG.
)a2)a3)By displaying in an area of 4 display unit sections using a4, a rich variety of display formats can be obtained.

Therefore, there is a mode in which information such as arbitrary characters and symbols is displayed in each area of one display unit section (this is especially called pinary mode), and a plurality of display unit sections, that is, four display unit sections as in the above embodiment. CRT by switching the mode (especially called image mode) that displays information such as arbitrary characters and symbols in this area using
Any display can be made depending on the device.

Next, a specific configuration of the display device of the present invention is shown in FIG. 4, and the configuration of FIG. 4 will be described below.

1 is a buffer register that stores transfer information from the central processing unit (CPU).

The information transferred from the CPU includes various command information and data information, and this command information includes read commands, write commands, and data commands, and the data information includes row address information and column address information of character memory and display memory, which will be described later. Contains mode setting information and display data.

The above instruction information is introduced into buffer register 1, 1a, and data information is introduced into 1b.

2, 3, and 4 are gate circuits corresponding to instruction information, and when a write instruction is transferred to buffer 1, line 100 is activated, gate circuit 2 is turned on, flip-flop 5 is set, and a read instruction is transferred again. Similarly to the above, the gate circuit 3 is turned ON and the flip-flop 6 is set to 7 bits, and when a data command is further transferred, the gate circuit 4 is turned OFF.
N and turns on the gate circuit I on the data information line 101.

8 and 9 are registers for storing row address information and column address information in the data information transferred to the buffer register 1, and 10, 11 and 12 are gate circuits corresponding to mode settings in the data information.

When this mode setting information is in the image mode (transferred as display information as dot information, which is a bit pattern, and displayed in an area using multiple display unit sections), the gate circuit 1
0 is ONL and sets the flip-flop 13, and in pinary mode (transferred as display information in the form of dot information, which is a bit pattern, and displayed in each area of one display unit section), the gate circuit 11 is ONL and sets the flip-flop 14. The gate circuit 12 turns ON and the flip-flop 14 is set in the character mode (normal display mode, that is, when a character code is transferred as display information).

Micro order ■ is introduced into register 8 that stores row address information, micro order ■ is introduced into register 9 that stores column address information, and further micro order ■ is introduced into gate circuits 10, 11, and 12. has been introduced.

These micro orders are output from a control section (not shown).

In the above-described transfer method between the CPU and the CRT display device, the CPU transfers read and write command information to the buffer register 1, and then the CRT display device returns confirmation information indicating that the information has been received.

Thereafter, row address information of the character memory and display memory is transferred to the buffer register 1 as data information, and then when confirmation information is returned, column address information is transferred to the buffer register 1.

When this confirmation signal is returned, the display information is transferred to the buffer register 1.

In this case, the display information is transferred one byte at a time.

Next, 16 is a character memory having a capacity of at least one screen or more, and stores character code signals such as characters and symbols to be displayed and a mode code signal corresponding to the pinary mode or image mode.

The character code signal described above is transmitted from the buffer register 1 to the lines 101 and 102 to the gate circuits 17 and 2:1 and 1.
8 into the character memory 16.

The gate circuit 17 described above receives the flip-flop 150 set output set during character memory, and
Further, the gate circuit 1B is provided with a Norip Flop 50 set output which is set when the micro order (2) output from the control section and the buffer register 1 write command are transferred.

Therefore, if there is a write command in character mode,
When the gate circuit 17 is ON, the character code signal is sent from the line 102 to the gate circuit 1 via the OR gate circuit 23.
8, and at this time, microog (2) is outputted, and the gate circuit 18 is then ONL and introduced into the character memory 16.

On the other hand, the mode code signal is sent to the binary mode code generator 1.
9 and image mode code generator 20 to gate circuit 2
The signal is further introduced from the gate circuit 18 to the character memory 16 via 1, 22 and 23.

The gate circuit 21 is introduced with a flip-flop 140 set output that is set in the binary mode, and when there is a write command in the binary mode, a code signal from the binary mode code generator 19 is sent to the gate circuit 21 and the OR gate circuit 23. 18, and is introduced from the gate circuit 18 into the character memory 16.

Furthermore, the gate circuit 22 receives the seven outputs of the flip-flop 13 that are set during the image mode, and when there is a write command during the image mode, the code signal from the image mode code generator 20 is sent to the gate circuit 22 and the OR game circuit 23. The signal is sent to the gate circuit 18 via the gate circuit 1B, and introduced into the character memory 16 from the gate circuit 1B.

The reason why the binary mode code and the image mode code are stored in the character memory 16 in this way is convenient for exchanging information between the character memory 16 and the CPU.

This will be explained later, but in these modes, the display information from the buffer register 1 is sent as dot information, so it is not introduced into the character memory 16, so that part becomes blank, and what is done here when exchanging information with the CPU. This is to prevent this from happening.

24 is an address circuit that addresses the 160 columns of character memory; information from the column address register 9 that stores the start address of the data sent to the CPU is introduced from the gate circuit 25 and preset; A signal is introduced from timing circuit 26 to sequentially advance the address from .

27 is an address circuit that addresses a row of the character memory 16; information from the row address register 8 that stores the start address of data sent from the CPU is introduced from the gate circuit 28 and preset; A signal is introduced from the timing circuit 29 to advance the address sequentially from the address.

The set outputs of the flip-flops 13, 14, and 15, which are set in the character mode, pinary mode, and image mode, are input to the gate circuits 25 and 28 through the OR gate 30. The code signal from the gate circuit 18 introduced is sent to the column address circuit 2.
4 and the row address circuit 27, the data is introduced and stored at a predetermined location in the memory.

Further, in order to exchange information with the CPU, the character memory 16 sends a code signal to the gate circuit 31 through a line 104, and is transferred from the gate circuit 31 to the CPU.

Into this gate circuit 31 is introduced a Frisop Flop 60 set output which is set when a read instruction to the buffer register 1 is transferred, and information in the character memory 16 is transferred to the CPU in response to the read instruction.

A display memory 32 stores display information as dot information and has a capacity for one screen.

Information to the display memory 32 is input from the buffer register 1 to the character memory 16 through lines 101 and 102 in the character mode, and at the same time, information is input from the line 103 to the buffer register 33, the character generator 34, and the OR gate circuit 35. In addition, dot information for display from buffer register 1 is introduced in line 1 in pinary mode and image mode.
01, 102, and 103, the gate circuit 36 and the OR gate circuit 35 are introduced.

Therefore, in order to introduce information into the buffer register 33 described above at the same time as information is introduced into the character memory 16,
Flip-flop 150 set output (F/F
15) is introduced, and the character code from the buffer register 33 is converted into dot information by the character generator 34 and then introduced from the OR gate circuit 35 to the display memory 32.

Furthermore, the set outputs of the Norip flops 14 and 130, which are set in the pinary mode and the image mode, are introduced into the gate circuit 36 to which the dot information is directly sent from the bathophore register 1 via the OR gate circuit 37. The dot information is introduced from the gate circuit 36 to the display memory 32 via the OR gate circuit 35.

38 is an address circuit for addressing columns of the display memory 320, and information from the column address register 9 mentioned above is introduced from the gate circuit 39 and preset.
Further, a signal is introduced from the timing circuit 40 in order to advance the address sequentially from this set address.

41 is an address circuit for addressing 320 rows of the display memory; information from the row address register 8 mentioned above is introduced from the gate circuit 42 and preset;
Further, a signal is introduced from the timing circuit 43 in order to advance the address sequentially from this set address.

The gate circuits 39 and 42 described above have a character mode,
The set outputs of flip-flops 13, 14, and 150, which are set in the binary mode and image mode, are inputted via the OR gate 30.

Therefore, the dot information from the gate circuit 35 introduced into the display memory 32 is transmitted to the column address circuit 3.
8 and the row address circuit 41, the data is introduced and stored at a predetermined location in the memory.

On the other hand, the display memory 32 is read out by a column and row address circuit (not particularly shown) for display synchronized with the scanning of the CRT display section 44, and dot information is sent from line 105 to the CRT display section 44 via a gate circuit 45. Display is performed by being sent.

During this display operation, the micro order (2) is given to the gate circuit 45 from the control section.

In the image mode, gate circuits 46 to 49 perform a
,,a22a3) Dot information for a4 from a1→a2→
This constitutes an address circuit control unit that sequentially sends data from a3 to a4 and causes the character memory 16 and display memory 32 to be addressed in a corresponding relationship.

The gate circuits 46 and 48 are respectively introduced with the outputs of the NoriPflossop 130 set when the image mode is set, and the gate circuit 48 is connected to the micro order output from the control section. Micro-orders output from ■ have been introduced.

The gate circuit 47 receives the output of the gate circuit 46 and the information "+1" sent from the control section, and the gate circuit 4
This “+1” information from 7 is sent to the row address circuits 27 and 41.
will be introduced to

This is because the row address circuits 27 and 41 count up with the information of 1 liao after addressing the information on the last line of the display unit section a1 or a2 in FIG. This is to cause the address for a4 to be performed.

Further, the gate circuit 49 receives the "-1" information sent from the output of the gate circuit 48 and the control section, and the "-1" information is transmitted from the gate circuit 49 to the row address circuit 2.
7 and 41.

This is done after addressing the information on the last line of the display unit section a2 or a4 in FIG.
This is to cause the row address circuits 27 and 41 to count down with the information ``'' to address the display unit section a3 or C.

Next, the above-mentioned operation shown in FIG. 4 will be explained.

[1] In the character mode, a write command is first transferred from the CPU and stored in the buffer register 1.

As a result, a write command is output to line 100, gate circuit 13 is opened, and Norisop flop 5 is set.

(At this time, the flip-flop 6 is reset.) Subsequently, after sending a confirmation signal back to the CPU, the start address of the line in which the character code is stored is transferred as DATA, and is stored in the bathophore register 1.

At this time, a DATA command is output to line 100, gate circuit 4 is opened, gate circuit 7 is enabled, and the row address information being transferred is output to line 101.

In addition, it receives a DATA command from the control unit and outputs the ■ signal, and the row address information is temporarily stored in the register 8 of the row.
is memorized.

Subsequently, after returning the confirmation signal, the column address information is transferred, and the second DATA command causes the gate circuits 4 and 7 to perform the same operation as described above, and furthermore, the signal ■ is output and the column address information is transferred to the column register 9. is temporarily stored.The mode instruction is then transferred as DATA when the confirmation signal is returned.

At this time, the third DATA command causes the game circuits 4 and 7 to perform the same operation as described above, and further outputs the signal (2).

Since the current mode is character mode, the gate circuit 12 is opened and the Frithop flop 15 is set.

The gate output of the gate circuit 12 is introduced via an OR gate 30 to gate circuits 25, 39 and 28, 42, respectively.

Therefore, address information indicating the start address of the column is transferred from the register 9 to the character memory 160 and the column address circuit 24.
They are also input to display memory 320 and column address circuit 38, respectively.

Address information indicating the starting address of a row is input from the register 8 to the row address circuit 27 of the character memory 16 and to the row address circuit 41 of the display memory 32.

Therefore, character memory 16 and display memory 32
is addressed to the designated start address by the row and column address circuits.

Subsequently, after a confirmation signal is returned, the character code, which is display information, is transferred to the buffer register 1.

At this time, gate circuits 4 and 7 are activated by the fourth DATA command.
performs the same operation as above.

Furthermore, ■signal is output.

For this purpose, the character code signal from the buffer register 1 is input to the gate circuit 17 via lines 101 and 102 and further to the buffer register 33 via line 103.

In this case, since the flip-flop 15 is set in the gate circuit 17, the gate is opened, and the flip-flop 5 is set by the write command, and the signal
The gate circuit 18 is opened, and the buffer register 33 is also enabled by the signal (2) and the flip-flop 150 set output (F/F 15).

Therefore, the character code from line 102 is introduced and stored in character memory 16 via gate circuits 17, 23 and 18, and at the same time, from line 103 via buffer register 33, character generator 34 and OR gate circuit 35, The dot information converted by the character generator 34 is stored in the display memory 3.
2 is introduced and stored.

Information is introduced into the character memory 16 and display memory 32 by writing to the start address position specified by the column and row address circuits, and information sent thereafter is written to the start address position specified by the column and row address circuits, and the information sent thereafter is written to the start address position specified by the column and row address circuits. are sequentially addressed by

In this case, with respect to the display memory 32, one line shown in FIG. 2 is introduced with the first dot information, and the second line with the next dot information is sequentially stored and introduced.

In addition, the display section 44 displays columns synchronized with the scanning of the display section.
The dot information written in the display memory 32 is read out by the row address circuit (not shown), and the gate circuit 45 is opened by the signal ■ and the information is sent to the display section 44, thereby starting the display operation. After that, the dot information sequentially written into the display memory 32 is sent to the display section 44 and displayed.

(2) The transfer method from the CPU in the pinary mode is the same as in the character mode described above.

Particularly in this case, the flip-flops are set by the write instruction, and since the mode instruction is binary mode, the gate circuit 11 is opened and the control flop 14 is set (at this time, the flip-flops 13 and 15 are reset).

Then, as in character mode, the row and column registers 8
, 9, the head address information is introduced.

Furthermore, since the gate circuits 25, 28 and 39, 42 are made conductive by the flip-flop 140 cents through the OR gate 30, the address circuits 24, 27 and 3B, 4 of the character memory 16 and the display memory 320 columns and rows are turned on.
1, the head address information is introduced.

On the other hand, by setting the flip-flop 14, the gate circuit 36 becomes conductive, and the gate circuit 21 from the binary mode code generator 19 becomes conductive.

In addition, 50 sets of flip-flops provide 18 gate circuits.
The seven solar power outputs have also been introduced.

Therefore, the dot information from the buffer register 1 is introduced into the display memory 32 through the gate circuit 36 and the OR gate circuit 35 via lines 101, 102, and 103, and the code signal from the binary mode code generator 19 is The code signal is introduced into the gate circuit 18 via the gate circuit 21 and the OR gate circuit 25, and at this time, the code signal is written into the character memory 16 by outputting the signal ■.

The dot information is written to the top address of the display memory 32, that is, to the first line in FIG.

Further, the dot information sent thereafter is stored and introduced into the second line sequentially.

This display operation is the same as in character mode.

The above-mentioned writing of the pinary mode code to the character memory 16 is done because the character memory 16 is left as a space at this time, and it becomes unclear what was displayed when exchanging information with the CPU. This is because the storage capacity increases when .

In this pinary mode, the dot information from the bath register 1 is directly introduced into the display memory 32 and displayed without going through the character generator 34, so dot information can be introduced arbitrarily, so that it can be displayed in units of one display section. Any sentence order or symbol can be displayed.

[3] In the image mode, when displaying arbitrary complex kanji, etc., it cannot be displayed in one display unit section and must be displayed across multiple display unit sections.

In such a case, the above pinary mode will reduce the CPU
Although it is possible to use software to synthesize the dotted information that spans multiple display unit sections, this increases the burden on the software.

For this reason, an image mode is provided to display images in a plurality of display sections using hardware control.

In this embodiment, there are four display unit sections.

The transfer method from the CPU is the same as in the character mode described above.

Particularly in this case, flip-flop 5 is set by a write command, and since the mode instruction is image mode, gate circuit 10 is opened and flip-flop 13 is set (flip-flops 14 and 15 are reset at this time).

Then, as with the character mode, the row and column registers 8
, 9, the head address information is introduced.

In addition, since the output of the gate circuit 10 is conducted through the OR gate 30 to the gate circuits 25, 2B and 39.42, the character memory 16 and the display memory 320 columns,
Head address information is introduced into the row address circuits 24, 27 and 38, 41.

On the other hand, the flip-flop 130 set causes the gate circuit 36 to conduct, and the gate circuit 22 from the image mode code generator 20 to conduct.

Furthermore, gate circuits 46 and 48 are enabled by the flip-flop 130 set.

Furthermore, since the flipflop 5 is set by the write command, its set output is introduced into the gate circuit 18.

Therefore, the dot information from the buffer register 1 is introduced to the display memory 32 from the gate circuit 36 and the OR gate circuit 35 via lines 101, 102, and 103, and the code signal from the image mode code generator 20 is introduced to the gate circuit 22. , are introduced into the gate circuit 18 via the OR gate circuit 23, and at this time, the code signal is written into the character memory 16 by the output of the signal ■.

The dot information is written to the top address of the display memory 32, and the subsequent dot information is written in the same way as in the pinary mode.

However, when writing dot information to the display memory 32, the character memory 16 and the display memory 320 row address circuits 27 and 41 are connected to the gate circuits 46 to 4.
9.

In other words, as shown in FIG.
When the writing to the position corresponding to al is completed, the control section outputs the ■ signal and opens the gate circuit 46, and the gate circuit 47 introduces the information of "+1" into the row address circuits 27 and 41, and as a result, al, A2, a which is the next line from the position corresponding to the display unit section of a3, C, D, E...
4. Move to the position corresponding to F, G, ■......

Therefore, the column address circuits 24 and 38 address the position corresponding to the display unit section a2.

The time series address circuits 24 and 38 are connected to the timing circuit 26.
, 40, control is performed to proceed to the next display unit section position after addressing the position corresponding to the same display unit section twice.

Thereafter, when the writing to the display unit section position a2 is completed, the ■ signal is outputted after the control, the gate circuit 48 is opened, and the information of "-1" is introduced from the gate circuit 49 to the row address circuits 27 and 41. As a result, a,, a3, C...
. . , and the column address circuits 24 and 3B advance to the next display unit section position, so that the position corresponding to the display unit section a3 is addressed.

Thereafter, the gate circuits 46 to 49 move the display unit section a4 to the position corresponding to C.

By this control, any display can be made using the area of 4 display unit sections.

On the other hand, when the address to the position corresponding to the display unit section a4 in FIG. Control of the address position in the row direction is performed.

By displaying a combination of such image mode and character mode or pinary mode, it is possible to enrich the display formats.

As detailed above, the display device of the present invention includes a character memory that stores display information in the form of data codes and a character memory having a storage capacity for at least one display screen, and a character memory that stores display information in the form of dot patterns on the display screen. a display memory having a storage capacity for one display screen to store corresponding information; address circuit means for the character memory and display memory; and a display section for displaying dot pattern information read from the display memory on the screen. , a character generator that converts the display information consisting of the data code into a dot pattern; the control means for controlling the introduction path of the character memory and the display memory for the display information that is coming; and the code generation means for generating a specific code to represent the dot pattern information as a code; When the central processing unit instructs the data code information, the display information consisting of the data code is introduced into both the character memory and the display memory via the character generator, and when the dot pattern information is instructed, the display information consisting of the data code is introduced into the display memory. The display information is introduced into the display memory without going through the character generator, and the code information from the code generation means is introduced into the character memory so that the display information in both memories corresponds to each other. and
Any character, symbol, etc. can be displayed using this dot information, and when the dot information is sent, code information indicating that dot pattern information has been sent correspondingly is written in the character memory. This corresponds to the information held in the display memory, so when this character memory converts information with the central processing unit, the part where the dot information was sent becomes blank, making it difficult to understand what was done there. Gana《Nari,
It's extremely convenient.

In addition, when displaying an arbitrary display using this dot information, it is possible to expand the display format by expanding one display unit section in integer multiples and displaying an arbitrary pattern in this expanded area. It has the characteristic that it can be done.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a display section unit related to the display device of the present invention, FIG. 2 is a diagram showing a data bit pattern related to FIG. 1, and FIG. FIG. 4 is a diagram illustrating the configuration of the display device of the present invention. 1: Buffer register, 2, 3, 4, 7, 10, 11 and 12: Gate circuit, 5, 6, 14, 15: Flip switch, 9 and 8: Register, 16: Character memory, 24 and 27: Character memory Address circuit, 3
2: Display memory, 33: Buffer register, 3
4: Character generator, 36: Gate circuit, 38
and 41: display memory address circuit, 44:
Display section (display screen), 102, 101, 103: input information lines, 46 to 49: game circuits that control character memory and display memory address circuits.

Claims (1)

[Claims] 1. At least 1 device that stores display information consisting of a data code.
a character memory having a storage capacity for a display screen; a display memory having a storage capacity for one display screen for storing display information consisting of a dot pattern in correspondence with a display image; and a combination of the character memory and the display memory. address circuit means; a display section for displaying dot pattern information read from the display memory on the screen; a character generator for converting the display information consisting of the data code into a dot pattern; , a control means for controlling a path through which display information sent from the central processing unit is introduced into the character memory and the display memory in response to instruction information indicating whether it is data code information or dot pattern information; and dot pattern information. code generating means for generating a specific code for representing information as a code, and the control means transmits the display information consisting of the data code to the character memory and the character memory when the data code information is instructed from the central processing unit. The display information is introduced into both the display memory and the display memory via the character generator, and when the dot pattern information is specified, the display information consisting of dot pattern information is introduced into the display memory without going through the character generator, and the above-mentioned information is introduced into the character memory. A display device configured to introduce code information from a code generation means so that display information in both memories correspond to each other.