JPS606876Y2 - Dot pattern display device - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a dot pattern display device for displaying patterns such as characters having a dot matrix structure.

Generally, a dot pattern display device, such as a CRT display device, displays characters on a CRT screen in a 7×5 dot matrix structure, and is equipped with a character generator that stores this character pattern. .

There are also devices that use the character generator or instead store the character patterns in a ROM (read-on memory) or RAM (random access memory) for normal program storage.

By the way, when characters are displayed in a 7x5 dot matrix structure and the ROM or RAM has a 1 word = 8 bit structure, the storage state of character patterns in the ROM or RAM is as shown in Figure 1. Become.

That is, in the example shown in FIG. 1, the character pattern of the English character "FJ" is stored, and in order to store the character pattern of each character in this way, a storage capacity of 7 bytes is required.

The reason for this is that data is generally read out from ROM or RAM one byte at a time, and the CRT screen is scanned from the top to the bottom, that is, from the first line to the seventh line of the dot matrix for each character. This is because it will be displayed.

For this reason, as can be seen from FIG. 1, in each byte area at least 3 bits of area cannot be used and is wasted.

This invention was made to improve the above-mentioned situation, and its purpose is to change the method of storing character patterns in ROM or RAM from the conventional method, so that each character can be stored in fewer bytes. To provide a dot pattern display device capable of storing patterns and thus efficiently using memory.

An embodiment of this invention will be described below with reference to FIGS. 2 to 4.

FIG. 3 shows the countries in which the CRT display device of this embodiment is configured.

In FIG. 3, ROM1 is a microprogram that controls various operations of the CRT display device, which will be described later.
The character pattern etc. of each character to be displayed on the display 7 is stored, and one word is composed of 8 bits.

The control unit 2 includes various registers for storing the screen configuration of the CRT display 7, a generation circuit for horizontal and vertical timing signals SYC, a cursor control circuit, and shift signal generation circuits for the work area 3 and conversion register 4. It is composed of a circuit for generating address data AD for the video RAM (random access memory) 5, a circuit for generating a timing signal T for the P-8 (parallel-serial) converter 6, etc., and various data are transferred from the ROM 1 to the above. It is set in each circuit and executes control operations.

By the way, the character pattern of each character is stored in the ROM 1 in the state shown in FIG.

That is, in the example of FIG. 2, the character pattern of the English letter "FJ" is stored, but as shown in the figure, in this invention, the character pattern is in a state corresponding to a 5x7 dot matrix structure, that is, , which is stored in a state corresponding to the conventional 7×5 dot matrix structure shown in FIG. 1, with rows and columns mutually converted.

By storing the character pattern in this manner, only 5 bytes of storage capacity are required to store the character pattern of each character, which is 2 bytes less than the conventional method.

When each character is to be displayed on the CRT display 7, a 5-byte character pattern is read out from the ROM 1, transferred to a work area 3 consisting of a RAM, and temporarily stored.

Next, a shift signal for shifting one bit to the left is output from the control unit 2 and applied to the work area 3, and as shown in FIG. is output from.

This carry is then input to the conversion register 4 bit by bit from the first byte carry by a shift signal output from the control unit 2 to the conversion register 4, and the carry for 5 bytes is input to the conversion register 4 bit by bit. When all are input, a predetermined address data is outputted from the control section 2 to the video RAM 5, and written in the area designated by this address data.

When input processing of the 5 bytes of the most significant bits to the conversion register 4 is completed, the next shift signal is output from the control unit 2 to the work area 3, and the 5 bytes of the 7th bit are carried from the work area 3. is output, then input to the conversion register 4, and from the conversion register 4 to the video RAM 5.
Each writing process is executed.

Hereinafter, similar processing is performed on 5 bytes of data for the 6th bit, 5th bit, etc.
As a result, the rows and columns of the character pattern stored in the ROM 1 as shown in FIG. 2 are mutually converted into the video RAM 5, and the character pattern becomes the state shown in FIG. It is something that will be remembered.

On the other hand, the video RAM 5 is a RAM that stores each character pattern in a one-to-one correspondence with the screen configuration of the CRT display 7, and address data that is periodically and sequentially updated and output from the control unit 2 during display operation. It is addressed by AD and undergoes a refresh operation.

The parallel data for each display character read out from the video RAM 5 by this refresh operation is P-8.
It is converted into a video signal (serial data) by a converter 6 and displayed on a CRT display 7.

Next, the operation of the above embodiment will be explained.

First, when the rFJ key is input from the keyboard to display the English letters rFY, for example, the character pattern stored in a predetermined area of the ROM 1 in the state shown in FIG. 2 is transferred to the work area 3.

Next, a shift signal is output from the control unit 2 to the work area 3, and the most significant bit (third bit) of 5 bytes of data is carried, that is, 5 bits of parallel data'.
It is output as 11111yo.

Further, shift signals are sequentially output from the control section 2 to the conversion register 4, and the carries are sequentially input to the conversion register 4 as serial data starting from the first byte.

The 5-bit serial data '11111' input to the conversion register 4 is then sent from the control unit 2 to the video RA.
It is written in the area indicated by the address data AD output to M5.

In addition, to work area 3, shift signals are sequentially output for the 7th bit, 6th bit, etc. Carry (5-bit parallel data) '00001 yo,'00001 yo,'... is output, input to conversion register 4, and 5-bit serial data '000' is output.
01J, converted to ``00001.,...'',
The data is then written into the corresponding area of the video RAM 5.

When all the character patterns of the English characters 1F are written in the video RAM 5 in this way, the video RAM 5
The character pattern of the English character 1F is stored in the state shown in FIG.

The video RAM 5 then undergoes a refresh operation,
The above alphabetic characters 1F and YO are sent to the corresponding display position on the CRT display 7 via the p=s converter 6 and displayed.

As explained above, this invention stores the character pattern of each character in ROM or RAM by mutually converting the rows and columns of the dot matrix of characters actually displayed on a display screen such as a CRT. In addition, when displaying each character, the rows and columns of the character pattern read from the ROM or RAM are mutually converted to match the dot matrix of the character pattern of the character displayed on the CRT screen on a one-to-one basis. Therefore, in the case of a CRT display device having a 7×5 dot matrix configuration, for example, the RO for storing character patterns is provided.
The storage capacity of M or RAM can be reduced by 3 bytes for each character pattern, allowing efficient use of memory.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a conventional dot pattern storage state, Figs. 2 to 4 are diagrams showing an embodiment of the present invention, Fig. 2 is a dot pattern storage state diagram, and Fig. 3 is a system configuration. 4 are diagrams for explaining the dot pattern conversion operation. 1...ROM, 2...control unit, 3...
...Work area, 4...Conversion register,
5...Video RAM, 5...P-5 converter, 7...CRT display.

Claims (1)

[Scope of utility model registration request] In a dot pattern display device that displays vertical characters on a screen using a vertical character pattern composed of a dot matrix structure, there is provided a character generator that stores a horizontal character pattern obtained by reversing the rows and columns of the character pattern. , a conversion means for reversing the columns and rows of the horizontal character pattern read from the character generator to convert it into a vertical character pattern, and displaying vertical characters on the screen using the character pattern obtained by this conversion means. A dot pattern display device comprising display means for displaying a dot pattern.