JPS6011887A - Character pattern reading system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a character slam reading system for a character generator used in a display device or the like.

(b) Prior Art and Problems A dot display method is one of the means for displaying characters in a character display device. This is a method in which characters are displayed in a dot configuration, for example, within a 24×24 (dot) square. A memory for reading out 8 bits at a time is usually used as the memory for this character. Therefore, character punctuation data for displaying kanji characters as (24×24) dots requires three (24×8) bit memories (M). This will be explained with reference to figure φ. Figure 1 (a
1 is a character slam memory for the kanji character ``image'', and as shown in the figure, it is composed of three memories M+1Mt and M. A single kanji like this requires the maximum number of dots (24 x 24) to make up the entire character (this is called a full-width j). On the other hand, the alphabet is shown in Figure 1 (b
), it may be displayed as (12 x 24) dots (all of which are called half-width J), and in this case, the alphabet rAJ
uses Memo II (M + + =) k as shown, while the alphabetic character “B” uses memory < M s +-”-”-)
w is used to store each character adpakun signal. Furthermore, the letter slam on the evening side of the English letter rBJ is Memo IJ.
The right part ζ of M is stored (using the free space). This causes the following drawbacks. When the character "Image J" in Figure 1 (a) is pressed and released, ζ is in the memory M.
It is sufficient to read in 8-bit units in the order of + 9Mt 1Ms. When reading out the alphabetic character rAJ shown in FIG.

After escaping in units of all 8 bits, memory M is next.

It is necessary to read out the left half of the data in units of 4 bits. On the other hand, the character rBJ is rBJ? ] l - When outputting, read out the memory Msk in units of 8 bits (After 7, the right half of memo 9M must be read out in units of 4 bits. This way -
Since the access order to this memory MI-Ms and the data output unit are different, is the character generator's character slam reading system? The disadvantage was that the 81 circuit was complicated.

(c) Object of the Invention The present invention has been devised to overcome all of the above-mentioned drawbacks, and its entire purpose is to provide a character-bump reading method that facilitates the reading of character-bump data.

(d) Invention! The present invention has a character storage section which is composed of a plurality of MXN-bit capacity arrangement u sections, and a character storage section L2.A character dot bang signal constituting one character has the character MiE memory S, and the character memory section L2. Character generator and character dot pattern information - IH bit by bit M lr! l In the character generation method, the data in the first register of N bits, the second register of N/2 bits, and the storage section of the number of phases is read out sequentially and the data is stored in the first register and the second register of N/2 bits. a second register ζ; The first register includes a control means for selecting in a predetermined order determined by the entire character structure and extracting it in N/2 bit units; and a second register), and then all the character dot-bang signals of the first register and the second register are extracted in a predetermined order and in units of N/2 bits. It is a method.

As shown in Figure 2 below, the present invention can store one character (24 x 24 bits,
(This is called a full-width character) In the character generator that makes up all the characters, if half-width characters (12x24) are sorted and stored in random order in the storage section tC, when reading out all the half-width characters, the above-mentioned All character dot bang signals in the memory section,
Once read into a register, on the output side of the register,
This is designed to select all predetermined data.

(e) Embodiments of the Invention The present invention will be explained below with reference to all the drawings. Is Figure 2 an embodiment of the present invention? ll--Illustrative black diagram.

In Figure 2, the full-width (24 x 24 characters) character "image"
The character bang signal (dot signal) is stored in three memories (R
OM) Mt, Mt and M31c are stored. Memories M, ~M3 have a total of '8' of (8x24) bits.
Ru. On the other hand, the half-width (12x24) character rAJ and the double-letter slam signal of "■3" are stored in the memories M H' + M2' and Ms' + -ζ, as explained in Fig. 1(b) and f. , the character 1'AJ is the memory MI' and M,
'i', and the characters r13J are stored in the memos IJM, ', and M22'l. Note that memory M2. ' and memory Mtt' are memories with ]/2 capacity of memory M2', and registers R1 and 1 (41! (4X2
) bit register, so registers R7 and R3 are 4
This is a bit register. When reading the full-width character "image" character stamp number 1d, 1m1] upper part is control@signal C1
In a hurry, the C switching unit 2 connects the contact point (.[), and the control signal C2'fc is emitted intermittently. Because of this, the switching units 3 and 4 are switched by one contact e-h, so that the 8-bit character slam signal D1 from the memory M1 is changed to the character slam signal Dt(
8bi.

(g) is divided into registers R and Rsl and sent, and furthermore, the character slam signal D3 from the memo 9 is set to register R41. The control section 1 issues a control signal Csk 1' to the multiplexer 5. This %11) signal C3 is the take'? signal in the registers R1 to R4. ! : This is a signal for outputting in units of 4 bits. Therefore, a 4-bit signal (video signal) is output from the four output terminals I, J, and L of the multiplexer 5, and sent to FOR (exclusive OR circuits) 6-9.

A control signal (a control signal P for completely inverting the video signal) is given to FOR6-9ζ from the control unit 1, and the inversion control of the video level is performed in FOR9. ANI that was cut
) A blanking signal Q is applied from the gates 10 to 13 (control section), thereby performing blanking control. The video signals from the AND gates 10 to 13 are sent to the parallel-to-serial conversion register 14, and are sent to the display control section 15 as video signals S in 11 columns. This serial video signal S is added to a brightness modulation circuit (not shown), and the image J is displayed on the display section.

In contrast, in the case of half-width characters rAJ and rBJ, the control section 1 issues a control signal C8' (IL-2), switches the switching section 2's contact point, and then issues a control signal C7.

Since the switching units 4 and 17 are switched in the order of the contacts e-h, the character slam signal DI' from the memo IJM,' is set to the register R1i, and the character slam signal DI' from the memo IJM,' is set to the register R1i, and the character slam signal DI' from the memo IJM, 1' and M22' is set. Character slam signals D21' and D22' are set in registers R2 and R,1, respectively.

Furthermore, the character slam signal D3' from the memo IJM,' is sent to the register R4t. This register R8~R4
When reading out the signal tone set to 1, the control section 1 issues a selection signal 2. When reading the character rAJ, this selection signal Z selects the p+jki+ bits of register R1, then the signal (4 bits) of register R2, all output terminals I-L.
Output from. In contrast to this, in the case of the character rBJ [Moss,
From the output terminals (1) to (L) of the multiplexer 5, first the signal of the register R4 (8 bits) is read out 4 bits at a time, and then the signal of the register R8 (4 bits, G) is read out. The circuit operations after FOR6 to FOR9 are the same as those described above, so the explanation will be omitted. As is clear from the above, memo IJM, '~M
The character slam signals stored in s' in random order are converted to predetermined bits by the multiplexer 5. 71. (4-focus) video signal units are extracted.

Note that the block diagram shown in Figure @2 has the following features and effects. The register 14 for parallel to serial conversion in FIG. 2 needs to use a circuit element that operates at high speed, but the FO
The video processing circuit 18 composed of R6 to R9 and AND gates 10 to 13 has the advantage that it requires circuit elements that are slower than at least the (low) path elements of the register 14. In the conventional system, the video processing circuit 18 was connected after the register 14, which required high-speed circuit control.

(f) Effect of the invention The present invention has the following advantages.

(1) Character dot signals are stored and read out from fcROM sequentially (cyclically) regardless of the order in which they are stored.
Since reading is sufficient, the cycle time may be slow.

+21 ROM reading system? The read order can be controlled using a register that can be performed at a relatively low transfer rate and can operate at high speed compared to ROM#.

(3) Since the video processing circuit is located before the parallel-to-serial conversion register, the video signal can be controlled by all low-speed elements.
It becomes easy to control the Dorito display on the screen.

[Brief explanation of the drawing]

FIG. 1 is a memory button configuration diagram explaining the present invention, and FIG.
The figure is a block diagram illustrating an embodiment of the present invention, and the symbols used in the figure are as follows. 1 is a control unit, 2, 3, 4.17 are switching units, 5 is a multiplexer, 6.7', 8.9 are FOR (exclusive OR circuit)
, 10. ] 1.12.13 is an AND gate, 14 is a register, 15 is a display control section, 16 is a display section, C,, C2
, C, is a control signal, CL is a control signal (for shift, Dl, Dt, I) 3, Dr' + D1+
'+D2. t'+Ds' is a character slam signal, e. f, g, h, 41 ports are contacts, I, J, l<, L are output terminals, M1+ Mt + Ms + M+' + Mt+
'+M2t'+M3' is memory (read-only memory)
, P are control signals, Q is a blanking signal, R, , R4 are registers (8 bits), R, , gs are registers (4 bits), and 2 is a selection signal. Agent Patent Attorney Hiroshi Matsuoka - Intestinal Stomach #/ /+l? #,? ￥-1 review (b) Hz rzi child〒N3

Claims (1)

[Claims] The character storage section includes a character storage section including a plurality of unit storage sections each having a certain capacity, and includes a character generator in which a character dot-bang signal constituting one character is stored in the character storage section. a character generator l which reads a signal a plurality of times in units of a fixed block, a register for temporarily storing a character dot bang signal in units, and means for sequentially reading data in the unit storage section of the count and setting the register; The control means selects and retrieves each unit block in a predetermined order determined by the entire character structure of the data in the set register, and the character dot slam signal is read out sequentially in units of fixed blocks from the plurality of unit storage sections. A character dot reading method characterized in that, after being set in a register, character dot bang signals from the register are taken out in a predetermined order in units of monthly fixed blocks.