JP2577429B2 - Display control device - Google Patents

Description

The present invention relates to a display control device for displaying character data on an image display.

(Prior Art) Generally, an electronic device such as an electronic desk calculator has a ROM (hereinafter referred to as a CGROM) that generates character data corresponding to a specific character such as a numeral or an alphabet in order to display the image as an image. ) Is built-in. This CG
The ROM generates character data corresponding to a specific address. Then, the generated character data is temporarily stored in the accumulator and then written into the display RAM. The display RAM has a storage area corresponding to each display segment of the display, and character data is written to a storage area corresponding to a data display position on the display.

FIG. 5 shows the configuration of a control device for performing such image display control. When reading specific character data from the CGROM 1, first, the upper address and the lower address of the address signal are stored in the X register 2 and the Y register 3, respectively. Then, the address designation circuit 4 designates the address for CGROM1,
Character data corresponding to the address is read from the CGROM 1 and stored in the accumulator (ACC) 5.

The character data stored in the accumulator 5 is written into the display RAM 6, and the writing position is specified by another address signal. That is, the address signal for designating the write position is first supplied to the X register 7 and the Y register 8 corresponding to the upper and lower addresses.
Is stored in Then, by the addressing circuit 9,
Character data is stored at a storage position corresponding to the stored address.

As described above, in the conventional display control device, the address designation for the CGROM 1 and the address designation for the display RAM 6 are performed by different address signals.

(Problems to be Solved by the Invention) The present invention has been made in view of the above-mentioned circumstances, and conventionally, when displaying one character data, the address designation for the CGROM and the address designation for the display RAM are performed by different addresses. It is an object of the present invention to provide a display control device which can improve a point which has to be performed by a signal and which can share a part of an address signal to simplify an address designation when displaying character data.

The present invention relates to a display control device for controlling a multi-digit display having a plurality of display segments, a bus to which addresses and data are transferred, and a character data. Are stored in a plurality of mxn bit storage areas, and one storage area is selected by an address designation by a high-order bit portion of the character data designation address on the bus, and the character data of the storage area is stored on the bus. Character data storage means for sequentially reading out data in m-bit units based on n successive address designations by the lower-order bit portion of the character data designation address, and a plurality of display segments of the display device, respectively provided. Is a plurality of mxn bits of display data storage area corresponding to each display digit of the display. Display data storage means to be connected to the plurality of display data storage areas of the display data storage means and the bus. Bidirectional transfer type selecting means for selecting a corresponding display data storage area and switching a data transfer direction between the selected display data storage area and the bus according to a read / write signal. The selection of one storage area of the character data storage means in accordance with the address designation by the high-order bit portion of the character data designation address and the designation of the display in accordance with the address designation by the high-order bit portion of the display digit designation address. The display data storage area corresponding to one display digit is selected, and a lower bit part common to both addresses is used. By n consecutive addressing operations, n times of character data reading in m bits from the character data storage means and n times of characters in m bits to the selected display data storage area are performed. Data writing and data writing can be performed in parallel via the bus.

(Operation) In the display control device having the above configuration, the character data storage device and the image display storage device are connected on the same bus, and the lower bit address on the bus reads data from the character data storage device as it is. And used for writing data to the image display storage device,
Thus, the character data is read from the character data storage device to the data bus in units of a predetermined number of bits, and the character data is read from the data bus to the image display storage device in units of the predetermined number of bits only by continuous address designation by the lower bit portion. Is written in parallel with the writing of the character data. Further, the image display storage device has a plurality of data storage areas respectively corresponding to a plurality of display digits of the display, and each data storage area can switch the data transfer direction by a read / write signal. It is connected to the bus via a directional data selection means. Therefore, not only writing of the character data read from the character data storage unit, but also transfer of character data via the bus between the data storage areas of the image display storage device can be performed in units of display digits. The display device of the device can also improve the efficiency of the frequently performed shift operation of the display digit position of the character data.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.
In this embodiment, the display has a nine-digit configuration, and displays one character data for each digit in a matrix of 4 × 7 dots.
16 character data having a bit size of 7 bits
The case where the type is stored will be described as an example.

FIG. 1 shows a configuration of a display RAM which is a display data storage means provided in a display control device according to an embodiment of the present invention. The display RAM 10 corresponds to each display segment of an image display. Nine storage areas, that is, storage areas 11 to 19 are provided. These storage areas 11 to 19
Each has a storage space of 4 × 7 dots, and is composed of, for example, cell arrays M11 to M47 of 4 rows and 7 columns as shown in the storage area 11. These storage areas 11 to 19
Are the corresponding storage area selection switch circuits 21 to
It is connected to a data bus 30 via 29.

At the time of data reading, these switch circuits 21 to 29 output signal φrr from the row decoder described with reference to FIG.
The switch is controlled by 1 to φrr9, and one of them is set to the ON state. Similarly, at the time of data writing, switch circuits 21 to 29 are switch-controlled by signals φwr1 to φwr9 output from the row decoder, and one of them is set to the on state. This row decoder, which will be described in detail with reference to FIG. 2, has a configuration for decoding upper four bits of address signals A1 to A4 among address signals transmitted through a 7-bit address bus. Therefore, the storage area of the display RAM is selected based on the contents of the address signals A1 to A4.

C1 to C7 are output signals from the column decoder described with reference to FIG. 3, and are obtained by decoding lower three bits of the address signals A5 to A7 among the seven bits of the address signal.
Data is sequentially written to the selected storage area by the decode signal. That is, the display RAM 10 and the data bus 3
When data is exchanged between 0, the lower address signals A5 to A7 are updated and the output signals C1 to C7 are selectively switched to the active state, whereby the cells in the storage area are arranged in column units. Are sequentially driven.

S1 to S36 are output data sent from the display RAM 10 to the display, the output data S1 to S4 correspond to the first digit display segment of the display, the output data S5 to S8 are the second digit, and
S33 to S36 correspond to the ninth digit display segment.

The data bus 30 includes four data lines 31 to 34, and output signals CGO1 to CGO4 from the CGROM are transmitted to the respective data lines 31 to 34 via clocked inverters 41 to 44, respectively. Clocked inverters 41 to 44 are controlled by a timing signal DEC that controls the operations of the row decoder and the column decoder. That is, the upper address signal A1
When the storage area of the display RAM is selected based on A4 to A4 and the cell in the column direction is selected based on the lower address signals A5 to A7, the cross inverters 41 to 44 are activated by the timing signal DEC. Controlled. Therefore, CGROM
Are read out in 4-bit units of CGO1 to CGO4, and are sequentially stored in the selected storage area of the display RAM 10 in column units.

FIG. 2 shows a specific circuit configuration of a row decoder for controlling the switch circuits 21 to 29. This decoder comprises inverters 45 to 48, NAND gates 51 to 59, and NOR gates 61 to 59.
78. The output of any one of the NAND gates 51 to 59 becomes "0" level in accordance with the contents of the address signals A1 to A4, and this is connected to one input of each of two NOR gates provided corresponding to each NAND gate. Supplied. The other input of each of these NOR gates is supplied with a clock signal ▲ which becomes “0” level during reading.
▼ and clock signal ▲ which becomes “0” level during writing ▲
▼ are supplied respectively. Therefore, when writing data to the display RAM 10 shown in FIG. 1, the output signals φrr1 to φrr9 depend on the contents of the address signals A1 to A4.
One of them becomes the “1” level. Also, display RAM10
When data is read from the memory cell, one of the output signals φwr1 to φwr9 becomes “1” level according to the contents of the address signals A1 to A4.

FIG. 3 shows a specific circuit configuration of a column decoder, which comprises inverters 71 to 73 and NAND gates.
81 to 87. That is, this decoder is configured to set any one of the output signals C1 to C7 to the “0” level according to the contents of the lower three bits of the address signals A5 to A7.

FIG. 4 schematically shows the basic structure of a CGROM. The CGROM 90 has 16 bits each having a 4 × 7 bit size.
Pieces of character data are stored. Then, one of the 16 character data is selected based on the contents of the address signals A1 'to A4' of the upper 4 bits. The selected character data is read out through the inverters 91 to 94 by continuous addressing using the lower three bits of the address signals A5 to A7. Therefore, 4 × 7
Bit character data is output data ▲ ▼
The data is read out by seven consecutive address designations in units of 4 bits of ~ ▲ ▼.

As described above, in the display control device of the present invention, the address specification for writing character data to the display RAM 10 and the address specification for reading character data from the CGROM 90 are both lower three hit address signals A5 to A7.
The character data can be displayed with a simple address designation. Also, CGROM90
Since the character data read operation and the data write operation of the display RAM 10 can be executed in parallel, the character data can be written to the display RAM 10 without going through an accumulator.

Signals on the same bus can be used as address signals A1 to A4 for selecting a storage area of the display RAM and address signals A1 'to A4' for selecting character data to be read from the CGROM. It is. in this case,
The selection of the storage area and the selection of the character data are executed alternately. Also, address signals A1 to A4 and address signal A1 '
To A4 'may be supplied by independent buses. In this case, selection of character data and selection of a storage area can be performed simultaneously, so that character data can be displayed very efficiently. it can.

[Effects of the Invention] As described above, according to the present invention, an address specification for reading out character data and an address specification for writing it into the display RAM can be performed by the same address signal. Therefore, address designation for displaying character data can be simplified.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a display RAM provided in a display control device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining a row decoder provided in the display RAM shown in FIG. 1,
FIG. 3 is a diagram for explaining a column decoder provided in the display RAM shown in FIG. 1, FIG. 4 is a diagram for explaining a CGROM provided in the display control device of the present invention, and FIG. It is a figure explaining an apparatus. 10: display RAM, 11 to 19: storage area, 21 to 29: area selection switch circuit, 90: CGROM.

Claims (1)

(57) [Claims] 1. A display control device for controlling a multi-digit display having a plurality of display segments, comprising: a bus to which addresses and data are transferred; and a plurality of mxn-bit storage areas for storing a plurality of character data. 1 by the address designation by the upper bit part of the character data designation address on the bus.
Character data storage means in which one storage area is selected, and character data in the storage area is sequentially read out in m-bit units based on n consecutive addressing by the lower bit portion of the character data specifying address on the bus; A display data storage unit provided corresponding to each of a plurality of display segments of the display, and having a plurality of mxn-bit display data storage areas each corresponding to each display digit of the display; A display data storage area connected between each of the plurality of display data storage areas of the display data storage means and the bus and corresponding to an address specified by an upper bit portion of a display digit specification address on the bus. And in accordance with a read / write signal, a data transfer direction between the selected display data storage area and the bus. Switching means for selecting one storage area of the character data storage means in accordance with the address designation by the upper bit part of the character data designation address, and selecting the display digit designation address. The display data storage area corresponding to one display digit of the display is selected in accordance with the address designation by the upper bit part, and n successive address designations by the lower bit part common to the two addresses Through the bus, n times of reading of character data in units of m bits from the character data storage means and n times of writing of character data in units of m bits to the selected display data storage area are performed via the bus. A display control device characterized in that the display control device can be executed in parallel.