JPS60101587A - Display memory access unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a character generator (C1aracLer
The present invention relates to a display memory access device in which a central processing unit can access CG for as long as possible in a text display device using Genera Lor (hereinafter referred to as C).

[Background of the invention]

In recent years, there has been a demand for higher functionality in the display functions of personal computers, and this has been achieved by making good use of the limited functions of a single-chip central processing circuit (microprocessor, hereinafter abbreviated as MI). Several proposals have been made.

In response to this demand, in order to enable high-speed display, a character generator (CG) is used to display characters (hereinafter referred to as text display). There is also a method using OM (read-only memory). The 1 blue report marked on the CG is a character pattern, and when a character code is given as an atlus, information corresponding to that code, that is, a character pattern is output. A personal computer system that uses this powerful CG method for displaying text has the advantage of fast display processing.However, as detailed display is required, As a result, it has become apparent that this method still has some shortcomings.

Figure 1 is a block diagram of a conventional display circuit in a personal computer, where 1 is M +') U, 2 is address bus, 3 is data bus, 4 is M I) LJ read/write operation. C7JvJ control signal line (hereinafter abbreviated as 1&1/W line); 5 is a 1' tres decoder that decodes the address of the circuit necessary for display; 6 is a display device for display, such as a cathode ray tube ( The cathode ray tube control circuit (CaLbod) generates various timing signals to control the CRT.
e Ray Tube Controller, below 1
7 is a multiplexer for switching between the MPLI address bus 2 or 1/W cotton 4 and the display address line 19 from the CRTC 6 by a signal supplied by the display timing signal line 18; 9 is a graphics display memory, 9 is a text display memory, 10 is a selection signal generation circuit for creating a switching signal for the selector 14, and 11 is a C
G, 12.13 is a parallel-serial conversion circuit 16 that converts the parallel output information into a signal suitable for displaying on the display 15;
is a clock oscillation circuit, 17 is a circuit that generates a clock for each character, and 20 is a C with the same memory contents as CGII.
It is G.

FIG. 2 is a timing chart 1 to 1 from when the data read from the text display memory 9 is inputted as an address by the CGII until it is parallel-serial converted.

In FIG. 1, the display memories 8.9 and 1.9 are controlled by various timing signals generated from the CRT CG. The α contents are periodically output as display data. The display data read from the display memory 8 is P1-IJ, and becomes visual information via the parallel-to-serial conversion circuit 12 as direct visual information. On the other hand, the display data read out from the display memory 9 is in character unit I:, and this data is
By giving the address to the GII, the CGII outputs a character pattern, that is, display information such as letters and symbols, which becomes visible information via the parallel-to-serial conversion circuit 13. Hereinafter, the stored contents of the P1 image in the display memory 8 will be referred to as graphic data, and the stored contents of the character code in the display memory 9 will be referred to as te, tono, to data. The selection signal generating circuit 10 selects the +-, +J visual information 3713 given to the display 15 by the selector eye based on the visible information 11. In this figure, the visible information of line 22 is selected. In short, selection 1j! The signal generating circuit 10 and selector I4 perform a combined display of a graphic display on the display 15 based on graphic data and a text I/display based on text data.

The MPU 1 is used to load or update the display memory 8.9 hegebraic data and text data, and inputs data via the address specified via the address bus 2 and the data bus 3. Perform output. Further, the R1W line 4 transmits a signal indicating the input/output direction of this data. The multiplex memory 7 is switched by a signal supplied by the display timing signal line 18, and the display memory 8.9
A composite address signal and a composite R/W signal for driving are outputted to a composite address bus 23 and a composite R/W line 24.

When the display memory 8.9 is being accessed from the MPUI, the address decoder 5 decodes a signal indicating that the display memory is being accessed and supplies it to the display memory 8.9 via the C signal lines 25, 26, respectively.

The display memory 8.9 stores certain predetermined values: 1. It is a small memory block, for example, if the MPUI is
When handling 8-bit) units, the memory block is a high 1 unit. ■It has enough storage capacity to display one screen with block memory. As a specific example, in order to enable high-definition graph ink display of 640 dots in the horizontal direction and 400 dots in the vertical direction, Pino I-RA
M constitutes a memory block.

Next, the timing chart shown in FIG. 2 will be explained.

The figure is a timing chart when M I ) U l handles Hyde units, and the clock in character units (hereinafter referred to as character clock) is the timing chart for the case where M ) divided by eight. The CRT CG operates in synchronization with the character clock, and the display address stored in the display memo 9 is no exception.
It is synchronized with the

Therefore, the text data read from display memory 9 is given to call in synchronization with the character clock. CG data is normally output after a certain period of time LAC (hereinafter referred to as 1-multi-access IL5 period) has elapsed since text data, that is, an address is given, and disappears at the same time as -1 address changes. In the parallel-to-serial conversion circuit ζ,
CG data (8-bit parallel data) is taken in during the period of 1 hour of the LOAD signal sent from the signal line 27, and at the same time parallel-to-serial conversion is started to output serial data.

Such a parallel-to-serial conversion circuit can be easily realized using a shift register.

Next, the disadvantages of text display using the CG method will be described in comparison with graph ink display.

ni1 As mentioned above, in the case of text display, the stored contents of the display memory 9 are character codes, but
In the case of graph ink display, the storage contents of the display memory 8 are bit image data. Therefore, assuming that one character is composed of 8 x 8 toso I-, the display memory required to display one character is 8 high I- in the case of graph ink display, whereas in the case of text display, One character coat corresponds to 2I, so Ehi 1-
I forgive you. Therefore, when updating display data for one character, eight write operations are required for each hide when displaying graph ink, whereas when displaying text, it is updated with one write operation. ζkiru. In other words, text display is eight times faster than graph ink display.

However, when the display becomes a direct product ♀1■ display and the screen frequency decreases, the following drawbacks occur in text display.

When MP[Jl reads Pino 1-image data to perform a certain process, for example, screen copying, it is necessary not to read display data, Ivl PUaj, and embedded data from the CG ROM during one character period. However, for example, if the access time is at most 200 ns,
Use OM to gear rough and one click frequency is 2.5 MI.
When displaying high 11j of Iz, one character period, that is, 4
．． If you try to read data twice during OOn sO, the access time is 4 (- is 200 ns (the period during which data is output is 0 seconds, and 31 is output twice in one character period) (Yes, as shown in Figure 1 in Sub-2, it is necessary to separately provide a CG20 exclusively for M1), which is disadvantageous in terms of cost, and is inevitable since 1"J. Then, when considering LSI conversion, CG I?
OM is 1. This is disadvantageous in terms of space factor as it becomes a target to be taken into S1. t “CG R
Conventionally, OM only had to take into account so-called alpha new logic, but if we were to consider something that could even output kanji, we would need something very large.

[Purpose of the invention]

The purpose of the present invention is to eliminate such drawbacks of the prior art,
The MPU does not use a CG ROM dedicated to the MPU.
An object of the present invention is to provide a display memory access device that makes it possible to read bit image data of a character pattern stored in a GROM.

[1 Requirement of the Invention] In order to achieve the above object, the present invention provides CGRO
A display lotus and a M1 access lotus moxibustion device are installed on each of the M address bus and data bus, and the display data output in parallel is connected in parallel and serially in the middle of the display data bus. A latch circuit is installed to hold the data for the period required to convert it and display it on the display, and the two switching devices are simultaneously controlled to switch and control the period required to read the display data from the CGROM. Is M l” U CGI by using circuits and minimizing the necessary amount?
This is the minimum period required to be able to access OM &J,C
GROM's 7 Treshas and data bus MP IJ
It was made open to the public.

[Embodiments of the invention]

FIG. 3 is a diagram of one embodiment of the present invention, in which the same 1.1υ is used as 11 for those having the same functions as in the case of FIG. In Fig. 3, 29.30 is a selector that performs the scraping J exchange, and 28 is a selector that connects selectors 29 and 30 to a signal line 32.
The path I and IJ switching control circuit 31 controlled by the display data bus 34 is a latch circuit that holds the data on the display data bus 34 for a period necessary for display.

FIG. 4 shows that in the system shown in FIG.
l;? ! FIG. 2 is a diagram illustrating the basis of the present invention in timing when M P U l accesses.

First, the operation of the circuit shown in FIG. 3 will be explained. In the conventional circuit shown in Fig. 1, the address bus and data bus are directly connected to the display memory and the parallel-to-serial conversion circuit, and the 0Gll outputs display data. In the example circuit, CGII connects text data bus 35 from display memory 9 and M as address buses.
The address bus 2 from the PUI is switched for input, and the data bus is switched to the display data bus 34 leading to the latch 31 and the successive lotus 33 directly connected to the MPU data bus 3. These lot switching is performed using the selector 29.3o, and the switching timing is the same, and the text data bus 35, the display data bus 34, and the MPU address bus 2 and the read bus 33 are switched at the same time. selected. The selectors 29 and 3o are switched by a signal line 32, and in FIG.
2 is high, the selector 29 selects the text data bus 3.
5 and the selector 3o selects the display data bus 34, respectively. Of course, when the signal line 32 is in the low state, the selector 29 connects the MPU address bus 2 to the selector 3o.
select the readout bus 33, respectively. The bus switching control circuit 28 is synchronized with the dot clock and character clock output from the oscillator 16, and produces a signal that changes depending on the dot clock position. In other words, the signal line 32 is in a low state only for a certain period within the N character period,
The signal is in a high state during other periods, and the fixed period in a low state is a period defined in units of dot clocks. In short, when the output signal line 32 of the lotus switching control circuit 28 is in a high state, it is a display access period, and when it is in a low state, that is, a certain period within the N character period is an MPU access period.

Such a bus ljJ conversion control fa number can be easily created using a frequency divider, a shift register, an i gate, an or gate, and an inverter using the dot clock and character clock as inputs. Furthermore, how long an MPU access period is provided between which characters is determined by the frequency of the character clock and the access time of the CG 11. -, 5' (Details will be explained later with reference to FIG. 4.

The launch circuit 31 is what is called a reherlanoch (i3). When the relay line 32 is in a high state, it is in a through state and directly supplies the data on the display data bus 34 to the parallel-to-serial conversion circuit 13. , when in the low state, the data that was in the through state in the high state before changing to the low state is held as it is, regardless of the display data bus 34.When the PL signal line 32 goes to the high state, , the launch circuit 31 enters the through state.In short, the role of the launch circuit 31 is to transfer display data on the display data bus 34 when the signal line 32 changes from a high state to a low state, that is, from a display access period to an MPU access period. The purpose is to hold the display data until the next display access period.The reason why it is necessary to temporarily launch the display data is that when the parallel-to-serial conversion circuit 13 attempts to capture the display data, This is because the CG data bus is switched to the readout bus 33 in the selector 30, and incorrect data is taken in.Detailed timing will be explained later with reference to FIG.

Next, we will discuss in detail how the MPU access period is determined based on what factors. As mentioned above, the MPU access period is greatly influenced by the character clock frequency and the CG access time, but in addition to this, the MPU access period is also affected by the data output period necessary for the next display processing, for example, parallel-to-serial conversion, and the MPU access period. P U IJ< CG RO
It depends on the amount of data required to read the M data. Set the period of the character clock to L(-H, CG access time to tAC1, set the time required for display processing to Lp5p
, If the time required for the M P Ll reading process is (MPu), the M P U-j' access period is at least LA6
+ We must secure time for LHPu. Also, whether to set the MplU access period once per small character display period is determined by setting it once per N characters.
All you need to do is grow one seedling of the following formula.

NXtC/-f ≧ N x (LA(-+ tDsP
) → tA(, + Lt4pu, °, N ≧ (L
A, + LMp, 7) / (Lol -LAO--L
vsp) In other words, the N character display period (N X LCA) or the display data processing time for N characters N
tT)5p) and MPU access period (tAc+LMP
It is better to be a person than the sum of u).

For example, in order to compare with the conventional example, consider the conditions of high-definition display with a character clock frequency of 2.5 Ml1zO and a CG access time of 200 ns.In addition, the time required for display processing is 50 ns, and the MPU read processing is Assuming that the time is 100 ns, from the above calculation formula, 2
It is sufficient to set an M, PU access period of 300 ns in character period. However, the time required for display processing is 5゜ns,
The condition that the MPU read processing time is 100 ns is a reasonable value based on experience, and can be relaxed by providing a latch circuit in the read lot 33.

FIG. 4 shows timing charts 1 to 1 in the circuit shown in FIG. 3 under the above conditions, while applying the switched address to CG until parallel-to-serial conversion is performed. Hereinafter, FIG. 4 will be explained in more detail.

Text data is output from display memory 9 in synchronization with the character clock, as in the case of FIG. on the other hand,
It is assumed that the MPU address is output asynchronously until the MPU takes in the data and executes the next instruction.

Under the above conditions, the two character display period, that is, 800ns,
It is necessary to divide one character display period of 250 ns into two characters and MPtJPt upper period of 300 ns.

That is, the lotus switching control circuit 28 outputs the lotus switching signal shown in FIG. 4 to the signal line 32. This hash switching signal causes the MPU address to be sent to the CG address bus 36 during the two-character display period. ), it will be in the form of input. This will cause the MP on the CG data bus 37 that is output from Ge ζ There is no particular problem because the display data read immediately after the MPU access period is output for a valid period of 1ζ with respect to the LOAII signal of the parallel/serial conversion circuit 1/&. Display data read immediately before the NIPU access period
M) Nam). Therefore, the pre-read display data is
) At the same time as the transition to the U-ac-p period, it became necessary to perform an operation, and the U-7 to F-circuits 31 became necessary. Also,
The provision of the launch circuit 31 does not pose any particular problem since the display data read out immediately after the MPLJ acknowledgment period is in a through state. In other words, from Ranochida data node 38, as shown in Figure 4, LO
Since the valid period display data is output in contrast to the D signal G, visual information can be obtained from the parallel-to-serial conversion circuit without any problems.

In short, by minimizing the period for reading display data from the CG, the circuit configuration is such that M1) U can access the CG storage contents without any problem in fQing visible information.

As mentioned above, when adopting the method of using CG for high-definition display,
By making the most of the ability (access time) of the CG, we have described the method by which M I) U accesses the CG, but this is not limited to this example; It is also possible to implement a system in which the MPU access period is set at a period of G.

〔Effect of the invention〕

As explained above, according to the present invention, even when high-definition display is required and the screen frequency increases, the MPU can access the CG memory by making full use of the CG memory capacity, and the screen hardware Rough copy 1~
It is no longer necessary to install a separate CG memory (1υG) dedicated to MPU access in order to perform software processing.

[Brief explanation of the drawing]

Is the diagram 1 of the personal computer display thread? Fig. 2 is a block diagram showing a conventional example of &; Fig. 2 is a timing chart for text display processing in the conventional art; Fig. 3 is a block diagram showing an embodiment of the present invention; Fig. 4 is a diagram of the same embodiment. 2 is a timing chart regarding text display processing of FIG. 1-MPU, 2-address bus, 3-data bus, 5
・-Address decoder, 6-CRTCl 9-Text display memory, TIC, 20-CG dedicated to MPU access, 28-Has switching control circuit, 29.3
o-Selector, 31- Lunch.

Claims (1)

[Claims] A central processing unit, a display memory that records information in character codes, a character generator that outputs character pattern information for display when the character code is entered manually, and a display memory that is output in parallel. A parallel-to-serial conversion circuit that converts information into a signal suitable for display on a display, a launch circuit that converts display character pattern information from parallel to serial and holds it for only the period necessary to display it on a display, and a character pattern. a switching lrj circuit that switches the input to the generator to the output of the display memory or the address bus of the central processing unit; and a switching circuit that switches and connects the output of the second F middle generator to the latch circuit or the data bus of the central processing unit. circuit, and a switching control circuit 118 for periodically and simultaneously switching the two glue J switching circuits, and the switching control circuit operates from the time when the display memory output is input to the character generator until it is output to the launch circuit. Except for the minimum period necessary for A display memory access device characterized by performing periodic switching control at a timing that ensures the minimum period required until the output is completed on a data bus of an arithmetic processing unit.