JPH01277890A - Display control system - Google Patents

Abstract

PURPOSE:To adapt the display control system to plural kinds of display devices by sectioning a display means into plural display areas, sectioning a storage means corresponding to said sections, and calculating the leading address of each section area for the leading address of one section and displaying respective display areas in parallel. CONSTITUTION:The display means 3 where plural picture elements are arrayed in a matrix is sectioned into the plural display areas 8 and 9 directionally and the storage means 6 stored with image data display on the display means 3, on the other hand, is also sectioned into display corresponding areas. A leading address is indicated for the display areas having the smallest address as to the plural display areas 8 and 9 of the display means 3 to read and display data, and the leading address of each section area is calculated by an arithmetic means for said leading address. The display areas 8 and 9 are brought into parallel display control on the display device 3 which is sectioned into the display areas 8 and 9 by using the obtained leading addresses and initially found leading address. Consequently, this system is adapted to plural kinds of display means, e.g., CRT 2 and a liquid crystal display device 3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a control method for driving the display of a liquid crystal display device used as a display device of, for example, a personal computer.

2. Description of the Related Art Cathode ray tubes (hereinafter abbreviated as CRT) have been used as display devices for so-called personal computers and the like. On the other hand, as electronic devices have become smaller in recent years, liquid crystal display devices used in such personal computers and the like have also become smaller.

The above-mentioned CRT uses a so-called interlace method or non-interlace method, in which the screen is scanned by an electron beam and the screen is rewritten. It is known that such CRTs have few problems such as flickering in terms of afterglow characteristics. - On the other hand, liquid crystal display devices fulfill the above-mentioned requirement for miniaturization in that their appearance is rectangular and flat, but when used in personal computers, Japanese word processors, etc., the display area is as large as possible. area will be required. Such a liquid crystal display device has, for example, 1
When displaying 0-digit alphanumeric characters, the so-called segment drive method is used, but when attempting to display complex figures, kanji, etc., many devices use the matrix drive method, in which pixels are arranged in rows and columns. It is used.

Problems to be Solved by the Invention In the case of liquid crystal display devices, problems such as flickering occur on relatively large screens depending on the liquid crystal material, driving method, duty ratio during driving, etc. It is known that no drive system is used. As such a driving method, if the display area of the liquid crystal display device is divided into a plurality of areas and each area is simultaneously scanned and displayed simultaneously, the duty ratio can be improved and the display quality can be improved. However, for this purpose, it is necessary to determine the start address of each division for each display area in the image memory in which image data to be displayed on the liquid crystal display device is stored.

If an attempt is made to obtain and display each of the leading addresses using software, such software cannot be used, for example, in a CRT display device, and there is a problem in that the compatibility of the software is lost. Furthermore, even when attempting to perform so-called scroll display of display images, there is a problem in that the control becomes significantly complicated.

An object of the present invention is to provide a display control method that solves the above-mentioned technical problems, can support multiple types of display devices, and can perform scroll control and the like with high display quality. .

Means for Solving the Problems The present invention is a system for display controlling a display means having a plurality of pixels arranged in a matrix, the display means being divided into a plurality of display areas along the column direction, and displaying. Divide the display-equivalent area in the storage means that stores the image data to be displayed on the storage device into sections corresponding to the classification of the display device, specify and read out the starting address of one section of the storage device, and read out the starting address of one section of the storage device; This is a display control system characterized in that the first address of each segmented area ItA is calculated for each segmented area ItA, and each display area on the display means is displayed in parallel.

Operation According to the present invention, a plurality of pixels are arranged in a matrix on the display means. This display means is divided into a plurality of display areas along the direction, and the storage means that stores the image data displayed on the display means also has a minimum A leading address is specified in the address display area for readout and display, and at this time, a calculating means calculates the leading address for each segmented area with respect to the leading address. In the display device divided into the plurality of display areas, display control of each display area can be performed in parallel using the start address obtained by such calculation and the start address originally determined.

Embodiment FIG. 1 is a block diagram showing the basic configuration according to an embodiment of the present invention. The configuration shown in the first diagram is such that a display control device 1, which is a display control device that performs display in, for example, a personal computer or a Japanese word processor, has the following functions:
For example, a CRT2 and a liquid crystal display device (
(hereinafter abbreviated as LCD) 3. CRT2 and L
The CD 3 is connected to a control device main body 4, and a central processing unit 5 including a microprocessor, an image memory 6 including a random access memory, etc. are connected to the control device main body 4. Ru.

The LCD 3 includes a liquid crystal display element 7 in which pixels of, for example, 640 x 480 dots are arranged in a matrix, and the liquid crystal display element 7 has an upper region 8 in which the address associated with rask scanning is in the first half, and a lower region in which the address is in the latter half. It is classified.

The upper region 8 includes, for example, eight segment electrode drive circuits U.
XO, UXI.

..., UX7, and common electrode drive circuits YO, Yl.

..., the display is driven at Y3. That is, the common electrode drive circuits YO to Y3 each perform display drive for 60 lines, and the segment electrode drive circuits YXO to YX7 each perform display drive for 80 dots on the selected line.

For the lower region 9, the segment electrode drive circuit LXO
, LXI, ..., LX7 and common electrode drive circuit Y4
-Y7 are used. segment electrode drive circuit Uχ,
The control device main body 4 is connected to the LX and common electrode drive circuit Y.
lines 11, 1 respectively through buffer 10 in
2.13, the data latch signal DL, the lie>' control signal HS, and the area sub-leg signal S are each commonly supplied.

In addition, display data DUO~ for the upper region 8 is provided to the segment electrode drive circuits OX, LX via a data bus 14.15.
D13 and display data for the lower area 9 DLO~DL
3 is supplied.

Further, the buffer 16 of the control device main body 4 is supplied to the CRT 2 with a horizontal synchronizing signal H5, a vertical synchronizing signal 2, and each color signal R, G, and B in parallel through lines 17, 18, 19, and 20, 21, respectively.

The control device main body (hereinafter abbreviated as the device main body) 4 is composed of, for example, a plurality of registers, and receives various control information supplied from the central control device 5, such as the display start address of the image memory 6 and the capacity of one line of the image memory 6. The CRT control section 23 includes a control storage section 22 that stores an offset value representing the , line selection information for scroll control, scroll information name, etc., and a CRT control section 23 that performs various controls for the image memory 6 for the CRT 2, and similar processing. is performed for LCDB.
A CD control section 24 is included. These control units 23.
24 is supplied with various synchronization signals from a timing generation section 25.

The address buses 26, 27, 28 from the central processing unit 5 and the control unit 23, 24 are connected to a multiplexer 29, so that address data is selectively supplied to the image memory 6. The multiplexer 30 also performs writing/reading switching in the image memory 6.

As mentioned above, the CRT2 and LCD3 are buffered 16.1
A CRTiII] control unit 31 and an LCD1%lJ control unit 32 are provided which drive the display via 0. These control parts 3
1.32 is provided with an interface circuit 33.34 for supplying data to each buffer 16.10.

FIG. 2 is a diagram showing the correspondence between the memory map of the image memory 6, the corresponding display areas 221 of the CRT 2 and LCD 3, the upper area 8, and the lower area 9. With reference to these drawings, in this embodiment, the display section 2 of the CRT 2
a is composed of 640 x 480 pixels, the liquid crystal display element 7 is also composed of 640 x 480 pixels as a whole, and the upper area 8 and lower area 9 are 640 x 2 pixels as described above.
It is composed of 40 pixels.

The image memory 6 is designed to have a storage capacity that exceeds the display area 2a, 8°9, and therefore a display corresponding area 35 as shown in FIG. 2 is provided in the image memory 6. will be accomplished.

This display corresponding area 35 is divided into an upper area 36 and a lower area 37 each having a capacity of 640×240. Such an upper region 36 has an address M (0,0
>, M (1°0), ..., M (79,0), M (0
,1),...

The address M (79,240> is set. Also, in the lower area 37, the address M (
0,240), M(1,240),...

M (79,240), M (1,240),...1
M(79,479) (hereinafter referred to generically as M) is set. Such address data M
The value changes depending on the setting position of the display corresponding area 35 in the image memory 6.

FIG. 3 is a block diagram showing a configuration example of the LCD usage system (crocodile section 24) in FIG. 1. Referring also to FIG. 3,
The control storage unit 22 is connected to the front stage of the LCD control unit 24, and the control storage unit 22 stores, for example, the scanning start address SA of the upper area 36 supplied from the central processing unit 5, and the offset as described below. A register 38,39 is provided in which the quantity FS is recorded. Register 38.3
The outputs of 9 are respectively input to latch circuits 40 and 41 that constitute the LCD control section 24.

A region control signal VS, which will be described later, is commonly supplied to the launch circuits 40 and 41 from a signal line 42. The output of the latch circuits 40 and 41 is the lower area 8 of the liquid crystal display element 7.
Scan start address UA and offset JLF at
The signals are respectively input to latch circuits 43 and 44 which respectively output S. Further, the output of the latch circuit 40 is inputted to an input terminal B of a selection means 45 implemented by, for example, a multiplexer.

On the other hand, the output of the adder 46 is supplied to the input terminal A of the selection means 45. The output of the selection means 45 is sent to the latch circuit 4.
7, the output of which is supplied to the lower area 9 of the liquid crystal display element 7.
A latch circuit 4 outputting a scan start address LA at
8 is input. - On the other hand, the adder 46 is supplied with the input of the latch circuit 41 and the feedback input of the latch circuit 47.

FIG. 4 is a block diagram showing an example of the configuration of the LCD control section 32 in FIG. 1. Referring to FIG. 4, the display data DA from the image memory 6 is input to, for example, four 8-bit shift registers, and the output thereof is, for example, 16 bits.
The signal is input to a bit shift register 50. The scroll data from the central processing unit 5 is sent to the scroll register 5.
1, for example, 4-bit parallel data D1
゜D2. It is output as D3.

The output of the scroll register 51 is input to, for example, a 1-pin down counter 52, and its output S1 is input to an AND circuit 5.1 via an OR circuit 53. The output of the AND circuit 54 is applied to, for example, a 4-bit down counter 55, and is also applied to a 1/4 frequency divider circuit 5.
6 and 1/2 frequency divider circuit 57. On the other hand, the output of the scroll register 51 is output from the AND circuits 58 to 6.
1. Commonly given to 64-67. On the other hand, the clock signal CK is input to the four shift registers, and is also input to the AND circuit 62 and the D-type flip-flop circuit 6.
8, an AND circuit 69, an inversion circuit 70, and a D-type flip-flop circuit 93, respectively.

The 16-bit output of shift register 50 is input to selection circuit 71, and one of the 16 bits is selected by 4-bit input from AND circuits 58-61.

The display data DA is serially input to a shift register 72, and 4 bits from AND circuits 64 to 67 are input to a 0 selection circuit 73, which is input in parallel to a selection circuit 73, and one of the 16 bits is selected. and output. The outputs of these selection circuits 71.73 are serially input to four shift registers 74-77, 78-81, respectively, and display data UDO-UD3, LDO-LD
3, each 4 bits are output in parallel.

The outputs of the shift registers 74-77 are sent to latch circuits 82.
83 or the latch circuit 84 to input terminals B and A of the selection circuit 85 in parallel. shift register 7
Similarly, the outputs of the selection circuits 86, 87 and 88 are sent to the input terminals B and 8 of the selection circuit 89, respectively.
A is input in parallel to each other. The AND circuit 6
One output is input to the AND circuit 54 via the inversion circuit 90, and the other outputs are commonly given to the down counter 55, the 1/4 frequency divider circuit 56, and the shift register 78, 74.

In addition, the output of the inverting circuit 70 is
/2 frequency divider circuit 92 sequentially. The inverted output of the 1/8 frequency divider circuit 91 is input to the 17'2 frequency divider circuit 92,
Further, the inverted output is output as a data latch signal DL.

5 and 6 are time charts illustrating an example of the operation of the configuration of this embodiment. Alter these drawings 9
The operation of this embodiment will be explained with reference to FIG. The area control signal (hereinafter referred to as a vertical synchronization signal) VS is generated every 240 pulses of the line control signal (hereinafter referred to as a horizontal synchronization signal) HS, and is generated every 240 pulses of the line control signal (hereinafter referred to as a horizontal synchronization signal) HS.
A frame, ie, an upper area 8 and a lower area 9, are displayed simultaneously and are generated every period when one screen of the LCD 3 is displayed. The following will explain the scroll display. The display start address UA, which is generated by the central processing unit F5 or the like based on an application program set in advance, and the offset size FS, which is the row direction size of the image memory 6, are stored in the latch circuit 38° that constitutes the control storage unit 22. They are set to 3 and 9 respectively.

After this set operation is completed, when the first vertical synchronizing signal VS1 is generated, the data from the registers 38 and 39 is latched into the latch circuits 40 and 41 at the rising edge. At this time, the previous data is still held in the latch circuits 43, 44, and 48. Here, depending on the rising position of the vertical synchronization signal VSI, the selection circuit 45 enables the input terminal B, passes the output of the latch circuit 40, and
Set to 7.

The latch circuit 47 is activated by the rising edge of the first signal HS1 of the horizontal synchronizing signal H8 shown in FIG.
0 data is set, and then the 4-square synchronization signal HS
Every time FS occurs, the preset [FS] of the latch circuit 41 is added to the latch circuit 47, and is set in the latch circuit 47 again. That is, addresses M(0,1) and M(0,2>) in the memory map of the image memory 6 shown in FIG.
, . . . address data are sequentially generated.

During this time, on the LCD 3, the image memory 6 is sequentially read out using data from the latch circuits 43, 44, 48, which hold the previous data, and the stored contents are displayed.

By the first rising edge of the vertical synchronization signal VS2 of the horizontal synchronization signal HS239, the address data UA stored in the latch circuit 40 is set in the latch circuit 46, and the offset value FS set in the latch circuit 41 is set in the latch circuit 46. It is set to 44. Further, the address data of latch circuit 47 is set in latch circuit 48. This latch circuit 48 holds the operation start address LA of the lower area 9 in the memory map of the image memory 6 shown at 2121, that is, the address M (240) by the above-described addition operation.

After this, the newly changed latch circuit 43°44.4
The contents of the image memory 6 are read out based on the contents of the image memory 8.

That is, in the image memory 6 shown in FIG. 2, both the upper area 36 and the lower area 37 are sequentially read out and displayed in parallel from start addresses M(0,0) and M(0,240), respectively.

At this time, when the operation start address is changed every byte of the vertical synchronization signal S by the scroll control, the upper area 36 and lower area 37 of the image memory 6 are alternately read byte by byte by the multiplexer 3o shown in the first figure. and is supplied to the LCD control section 32. This L CD 1t
The i18 section 32 operates as follows.

The data latch signal DL shown in FIG. 5 is configured to generate (number of pixels per line/4), that is, 640/4=160 pulses in this embodiment, between two horizontal synchronizing signals H8, and is supplied to the LCD 3. be done. LCD3 drive circuit U
The falling edge of this pulse causes display data 00.X, LX to be supplied from the data bus 14.15. DUO
~DU3, and import the display data of DLO~DL3.

After the 1-byte data regarding the upper region 36 has been captured,
79717071 for 11 minutes of data latch pulse DL
The circuit 93 delays each address M from the upper bit side.
(i,j)3 to M(i,j)0 are output to the data bus 14 in parallel. Subsequently, data DLO regarding the lower region 37 is sent to the data bus 15 by the next data latch pulse DL.
By repeating the process of 0 or more outputting DL3, the upper area 8 and lower area 9 of the LCD 3 can be driven to be displayed in parallel from the top address side.

FIGS. 7 and 8 are time charts illustrating detailed movements of this embodiment. The operation of this embodiment will be described with reference to these drawings. As described above, the image memory 6 outputs the display corresponding area 35 based on the address control as described above by the LCD control unit 24.
The upper area 36 and the lower area 37 are read out alternately on a byte-by-byte basis, and are supplied to a parallel/serial conversion circuit (not shown) in the LCD control section 32 and inputted as a serial signal as display data DA shown in the fourth figure.

In the LCD control unit 32, the clock signal CK, lower instruction signal LT and horizontal synchronization signal H9 are timing pulse 2.
5, and the clock signal CK is a clock signal output in synchronization with the display data DA. Further, the above-mentioned instruction signal LT indicates that the currently output data is in the lower area 3 of the image memory 6.
6 and the lower region 37, and is generated at a high level when the data corresponds to the upper region 37, and at a low level when the data corresponds to the upper region 36, for example.

Further, the upper scroll signal US and the lower scroll signal LS are instruction signals for horizontal scroll movement ft, and are output when a target line is reached during a read cycle based on a scroll command from the central processing unit 5, and the scroll display is When performing this, for example, it is output at a high level.

Hereinafter, with reference to the above-mentioned drawings, a description will be given of the case where the lower region 9 of the liquid crystal display element 7 is scrolled by 3 points to the left in the drawing. As explained with reference to FIG. 3, the operation start address of the image memory 6 is generated in synchronization with the vertical synchronization signal VS, and is read out by the reference clock synchronized with the horizontal synchronization signal HS. That is, the start address r of the upper area 3G in the memory map shown in FIG.
, 1 (0, 0>) are input to the shift register 1. At this time, the lower area instruction signal LP is not output, and the 1 error input to the shift register 72 is prevented. I can escape.

Next, the first atto L of the image area 37 in the image memory 6,
The 8-bit data LO to L7 of M (0,240>) are read out and input to the four shift registers as display data DA, and since the lower instruction signal LP is at a high level, the 8-bit data LO to L7 are input to the shift register 72. At this time, the data UO to U7 are input to the shift register 50.

At this time, the selection circuit 71 selects the "3" terminal of the shift register 50 because the AND circuits 58 to 61 are conductive, and the data is delayed by 420 times and is individually assigned to the shift 1/distaff 4 to 77. It is kept quiet. That is, the 8-bit data LO to L7 are stored in the shift register 72.
At the time of input, each shift register 74 to 77 holds data UO-U3.

On the other hand, in the selection circuit IB73, the AND circuits 64 to 67 are in a cutoff state, so the "0" terminal is selected by the selection circuit 73, and the cross signal shown in No. 71'3 (6) from AND@n54 is output. At the time when S2 is output, display data L3 is output from selection circuit 73, and data L3 to L6 are held in shift registers 78 to 81. Also, FIG. 2 (10) from the 1/4 frequency divider circuit 56
When the signal S6 shown in FIG. 1 rises and the display data U8 to U15 of the next upper region 8 (that is, the data at address M<1.0>) is supplied as the display data DA, it is held in the launch circuit 82.86. .

At this time, the shift registers 74-77 are serially inputted with data U4-U7 remaining from the 1-byte data as described above, and the shift registers 78-81 are serially inputted with similar data U4-U7 regarding the lower area 37. LIO is input respectively. Further, due to the rising edge of the 77th (11) illustrated signal S7 which is the output of the 1/2 frequency divider circuit 57, the data UO-U3 of the latch circuit 82 is transferred to the latch circuit 83, and the data L3-U3 of the latch circuit 86 is transferred to the latch circuit 83. L6 will be latched by the latch circuit 87, respectively. At the same time, the data U4-U7 of the shift registers 74-77 are latched by the latch circuit 84, and the data L7-LIO of the shift registers 78-81 are launched into the latch circuit 88, respectively.

In Table 1, during the period when the 1/72 frequency divider circuit 92 and the signal S12 shown in FIG. 7 (17) are at high level, the upper display data DUO□-DU3 and the lower display data DLO~ Output as DL3. Furthermore, during the low level period of the signal S12, the latch circuit 84.8
8 data is similarly outputted and inputted to the LCD 3. Such movements (%) are repeated sequentially.

The central processing unit 5 outputs the upper scroll signal 18 US as a high level and the lower scroll signal LS as a low level.
Provides scroll display of llJ. Therefore A.N.
The D circuits 58 to 61 become conductive and the selection circuit 7
1 outputs the output terminal "3" of the shift register 50 as valid.

Furthermore, the AND circuits 64 to 67 are cutoff circuits, and therefore the selection circuit 73 is connected to the output terminal "0" of the shift register 53.
Output as valid.

The 4-bit data is taken out in synchronization with the shift movement ft- of the shift registers 50 and 72, and the data is transferred to the shift register 7.
4 to 77; 78 to 81 are retained as described below. It is also held in the latch circuits 83, 84, 87° 88 and outputted in conjunction with the selection circuits 85, 89.

In addition, in the drawing, when performing a rightward scroll operation, the operation start address in the upper area 36 of the image memory 6 is internally decreased by 1 byte, and (address M (0, 0)
(previous address) If the above-mentioned 8-bit left scroll is supported for the non-scroll area, and 8 bits ~ scroll amount is supported for the right-scroll area, right scroll will be expressed as a result. become.

Effect of Light As described above, according to the present invention, in a display device divided into a plurality of display areas, each display area can be controlled to display in parallel.

[Brief explanation of the drawing]

10 is a block diagram showing the configuration of a display control device 1 according to an embodiment of the present invention, and FIG. 2 shows an image memory 6 connected to a CRT.
A diagram showing the display area of CD3 at a corresponding distance f, Figure 3 is LC
A block diagram showing the configuration of the control unit 24 for D, FIG. 4 is for LC.
A block diagram showing the configuration of the D control section 32, FIG. 5 is a time chart explaining the basic operation of this embodiment, FIG. 6 is a time chart explaining the principle of scrolling operation of this embodiment, and FIG. and FIG. 8 is a time chart showing details of the scrolling operation of this embodiment.

Claims (1)

[Claims] A system for display controlling a display means having a plurality of pixels arranged in a matrix, the display means being divided into a plurality of display areas along the column direction, and displaying on the display means. The display-equivalent area in the storage means in which image data is stored is divided into modes corresponding to the divisions of the display means, and the start address of one section of the storage means is specified and read, and each section is read out with respect to the start address. A display control method characterized by calculating a start address for each area and displaying each display area in a display means in parallel.